JP2007198880A - Semiconductor integrated circuit and duty measurement/correction method using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To measure and correct the duty of a clock signal accurately without using any external signals. <P>SOLUTION: A semiconductor device 20 has a duty measurement/correction circuit 1 and a PLL circuit 4 as a semiconductor integrated circuit. The duty measurement/correction circuit 1 comprises a duty measurement circuit section 2 and a duty correction circuit section 3, and a clock signal CLKA before correction in which a duty ratio is changed is input. The delay time of the delay circuit of the duty measurement circuit 2 when a signal Out output from the duty measurement circuit section 2 changes from a low level to a high one is measured as the duty of the clock signal CLKA before correction by the duty measurement circuit section 2. In this case, the delay circuit of the duty correction circuit section 3 paired with the delay circuit of the duty measurement circuit section 2 is selected, and the duty of the clock signal CLKA before correction is corrected by the duty correction circuit section 3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a duty measurement / correction method for measuring and correcting a duty of a clock signal.

  In semiconductor devices such as digital LSIs and SoCs (System On a Chip), various clock supply circuits are used, and a PLL (Phase Locked Loop) circuit (also called a frequency multiplier circuit) and a DLL (Delay locked Loop) are frequently used. Has been. In recent years, with the progress of miniaturization and higher integration of semiconductor elements, the frequency of clock signals output from clock supply circuits has increased, and the frequency and duty of clock signals have been increased due to changes in circuit thresholds due to manufacturing variations. Variations may occur. For this reason, it is important to measure and correct the frequency and duty of the clock signal with high accuracy. As the duty measurement, a highly accurate measurement of the duty is performed using an external sampling clock signal having a frequency several times larger than that of the clock signal (see, for example, Patent Document 1).

In the duty measurement of a clock signal described in Patent Document 1 or the like, there is a problem that the duty cannot be measured only by a signal generated inside the semiconductor device, and the duty cannot be corrected. In the case of a state-of-the-art digital LSI or SoC, there is a problem that a higher-speed external sampling clock signal is required because the clock signal has a higher frequency. In addition, the circuit configuration becomes complicated in order to perform highly accurate duty measurement and correction. If these circuits are provided in a semiconductor device, the cost of the semiconductor device increases, while these circuits are provided outside the semiconductor device. However, there is a problem that the evaluation cost increases.
Japanese Patent Laid-Open No. 2001-124813 (FIGS. 1 and 2)

  The present invention provides a semiconductor integrated circuit capable of accurately measuring and correcting the duty of a clock signal without using an external signal, and a duty measuring and correcting method using the same.

  In order to achieve the above object, a semiconductor integrated circuit of one embodiment of the present invention has a duty ratio of 50% and a clock signal having a “High” level period or a “Low” level period shorter than 50% and the clock signal input thereto And a delay time of the delay means selected immediately after the output signal changes from the “Low” level to the “High” level. And a duty measurement circuit unit for measuring the duty as a duty.

  Furthermore, in order to achieve the above object, the duty measurement / correction method using the semiconductor integrated circuit of one embodiment of the present invention has a “High” level period or a higher period than the first clock signal with a duty ratio of 50% and 50%. The step of inputting the second clock signal having a short “Low” level period to the duty measurement circuit unit and the duty correction circuit unit, and a plurality of first delay means provided in the duty measurement circuit unit, the second clock signal. The first delay time of the first delay means selected immediately after the signal is delayed and the output signal of the duty measurement circuit section changes from the “Low” level to the “High” level is the second clock signal. Measuring the duty of the second clock signal, and a plurality of second delays provided in the duty correction circuit unit for delaying the second clock signal The second delay means having a second delay time obtained by subtracting the first delay time from a time of 50% duty of the first clock signal is selected from the extension means, and the second delay is selected. And correcting the duty of the second clock signal using time.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of accurately measuring and correcting the duty of a clock signal without using an external signal, and a duty measuring / correcting method using the same.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor integrated circuit according to Embodiment 1 of the present invention and a duty measurement / correction method using the same will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a semiconductor device. In this embodiment, a duty measurement / correction circuit is provided in the semiconductor device as the SoC.

  As shown in FIG. 1, the semiconductor device 20 is provided with a duty measurement / correction circuit 1 and a PLL circuit 4 as semiconductor integrated circuits, and based on a corrected clock signal CLKC output from the duty measurement / correction circuit 1. Various circuits (not shown) in the semiconductor device 20 operate.

  The duty measurement / correction circuit 1 includes a duty measurement circuit unit 2 and a duty correction circuit unit 3, and is output from the PLL circuit 4 and has an ideal duty ratio of 50% and 50% due to a change in circuit threshold due to manufacturing variations. An uncorrected clock signal CLKA having a changed duty ratio is input to a typical clock signal CLK. Here, the frequency of the pre-correction clock signal CLKA output from the PLL circuit 4 is a high-speed signal, for example, 800 MHz.

  The duty measurement circuit unit 2 includes delay circuits DA1 to DAn, XOR circuit EX1, flip-flops FF1 to FF3, inverter INV1, inverter INV2, selector SEL1, and selector SEL2.

  The inverter INV2 receives the pre-correction clock signal CLKA and outputs the inverted signal to the selector SEL2. The selector SEL2 receives the pre-correction clock signal CLKA and its inverted signal, selects one of the signals based on the control signal SGB, and outputs it as the pre-correction clock signal CLKB.

  The flip-flop FF1 with a reset function is provided between the selector SEL2 and the delay circuits DA1 to DAn, inputs the pre-correction clock signal CLKB as a clock, the output signal is inverted by the inverter INV1, and the inverted signal is again Input as data. The flip-flop FF1 latches data when the pre-correction clock signal CLKB rises. The flip-flop FF1 with a reset function receives a reset signal and outputs a signal A according to the signal level of the reset signal.

  The delay circuits DA1 to DAn are provided in parallel between the reset function flip-flop FF1 and the selector SEL1, and serve to delay the signal A output from the reset function flip-flop FF1 for a predetermined period.

  Here, it is preferable to use, for example, an inverter chain having an inverter as a minimum delay unit for the delay circuits DA1 to DAn. The number of inverters constituting the inverter chain is preferably set to an even number. The delay time of the delay circuits DA1 to DAn is calculated by using, for example, SPICE (Simulation Program with Integrated Circuit Emphasis) which is a circuit simulator from device data, or data obtained from TEG (Test Element Group) evaluation. May be used. Note that the delay time of the XOR circuit EX1, the flip-flops FF1 to FF3, the inverter INV1, the inverter INV2, the selector SEL1, and the selector SEL2 provided in the duty measurement circuit unit 2 is sufficiently longer than the delay times of the delay circuits DA1 to DAn. short.

  The selector SEL1 is provided between the delay circuits DA1 to DAn and the flip-flop FF3, receives the control signal SGA, selects one of the delay circuits DA1 to DAn based on the control signal SGA, and receives a predetermined time from the signal A. A delayed signal AD is output.

  The flip-flop FF2 is provided between the flip-flop FF1 and the XOR circuit EX1, inputs the uncorrected clock signal CLKB as a clock, latches the signal A data when the uncorrected clock signal CLKB falls, and outputs the signal B To do.

  The flip-flop FF3 is provided between the selector SEL2 and the XOR circuit EX1, inputs the uncorrected clock signal CLKB as a clock, latches the signal AD data when the uncorrected clock signal CLKB falls, and outputs the signal C .

  The XOR circuit EX1 receives the signal B output from the flip-flop FF2 and the signal C output from the flip-flop FF3, and outputs a logically output signal Out. This signal Out is used for duty measurement. Here, when the signal B level of the flip-flop FF2 is different from the signal C level of the flip-flop FF3, the XOR circuit EX1 outputs a “High” level signal, and the signal B level of the flip-flop FF2 and the flip-flop FF3 When the signal B level is the same, a “Low” level signal is output. Note that the XOR circuit is also referred to as an Exclusive-OR circuit, an EX-OR circuit, or an Ex-OR.

  The duty correction circuit 3 includes delay circuits DB1 to DBn, a 2-input AND circuit AND1, an 2-input OR circuit OR1, a selector SEL3, and a selector SEL4.

  Each of the delay circuits DB1 to DBn receives the pre-correction clock signal CLKA and delays the pre-correction clock signal CLKA for a predetermined time. Here, for example, an inverter chain having an inverter as a minimum delay unit is preferably used for the delay circuits DB1 to DBn. The number of inverters constituting the inverter chain is preferably set to an even number. As a method for calculating the delay times of the delay circuits DB1 to DBn, for example, the device data may be calculated using SPICE, which is a circuit simulator, or may be calculated using data obtained from TEG evaluation. Note that the delay times of the two-input AND circuit AND1, the two-input OR circuit OR1, the selector SEL3, and the selector SEL4 provided in the duty correction circuit unit 3 are sufficiently shorter than the delay times of the delay circuits DB1 to DBn.

  The selector SEL3 is provided between the delay circuits DB1 to DBn and the two-input OR circuit OR1, receives the control signal SGA, selects one of the delay circuits DA1 to DAn based on the control signal SGA, and outputs a pre-correction clock. A signal D delayed by a predetermined time from the signal CLKA is output.

  The 2-input OR circuit OR1 is provided between the selectors SEL3 and SEL4, receives the pre-correction clock signal CLKA and the signal D, and outputs a logically calculated signal E. Here, the signal E becomes “Low” level when the pre-correction clock signal CLKA and the signal D are “Low” level, and otherwise becomes “High” level.

  The 2-input AND circuit AND1 receives the pre-correction clock signal CLKA and the signal D, and outputs a signal F obtained by logical operation. Here, the signal F becomes “High” level when the pre-correction clock signal CLKA and the signal D are “High” level, and becomes “Low” level otherwise.

  The selector SEL4 receives the control signal SGB, selects either the signal E or the signal F based on the control signal SGB, and outputs it as the corrected clock signal CLKC.

  Next, the operation of the duty measurement / correction circuit will be described with reference to FIGS. 2 to 6. FIG. 2 shows the relationship between the duty of the clock signal and the delay time of the delay circuit, and FIG. 3 shows the delay time of the delay circuit. FIG. 4 is a diagram showing switching between the “High” level period and the “Low” level period of the clock signal in the duty measurement / correction, and FIG. 4A shows the correction of the “High” level period. FIG. 4B is a diagram illustrating correction of the “Low” level period, FIG. 5 is a timing chart illustrating the operation of the duty measurement / correction circuit using the “High” level period of the clock signal, and FIG. Is a timing chart showing the operation of the duty measurement circuit section when a delay circuit having a delay time shorter than the “High” level period of the clock signal before correction is selected, and FIG. FIG. 6 is a timing chart showing the operation of the duty measurement / correction circuit when a delay circuit having a delay time longer than the “High” level period of the lock signal is selected. FIG. 6 shows the duty measurement using the “Low” level period of the clock signal. FIG. 6A is a timing chart showing the operation of the correction circuit, and FIG. 6A is a timing chart showing the operation of the duty measurement circuit section when a delay circuit having a delay time shorter than the “Low” level period of the pre-correction clock signal is selected. (B) is a timing chart showing the operation of the duty measurement / correction circuit when a delay circuit having a longer delay time than the “Low” level period of the pre-correction clock signal is selected.

As shown in FIG. 2, the ideal clock signal CLK has a duty of 50% for the “High” level period TH, a duty of 50% for the “Low” level period TL, and TH = TL. For the known clock signal CLK, the sum of the delay time T _DA of the delay circuit _DA and the delay time T _DB of the delay circuit DB is
TL, TH = T _DA + T _DB ............ Formula (1)
And set. Here, the sum is the “Low” level period TL.

As shown in FIG. 3, the maximum delay time _{T DAn} of the delay circuit DAn, gradually reducing the delay time, to set the delay time _{T DA1} of the delay circuit DA1 minimized. On the other hand, the delay time T _DA1 of the delay circuit DB1 is maximized, the delay time is gradually decreased, and the delay time T _DAn of the delay circuit DAn is set to the minimum. The delay circuit DA and the delay circuit DB are selected by the control signal SGA. For example, the delay circuit DA1 and the delay circuit DB1 are selected. The delay time interval for each delay circuit is
T _{DAm + 1} −T _DAm = T _DBm −T _{DBm + 1} ... (2)
It is preferable to set the same. Here, the value of m is 1 to (n−1).

  As shown in FIG. 4A, when the “High” level period of the pre-correction clock signal CLKA is shorter than the “High” level period TH (50%) of the clock signal, the delay circuit is selected and “High” is selected. The level period is corrected to approach the “High” level period TH (50%) of the clock signal.

  On the other hand, as shown in FIG. 4B, when the “Low” level period of the pre-correction clock signal CLKA is shorter than the “Low” level period TL (50%) of the clock signal CLK, the delay circuit is selected. The “Low” level period is corrected to approach the “Low” level period TL (50%) of the clock signal CLK. Note that the selection of the correction for the “High” level period and the correction for the “Low” level period is performed based on the control signal SGB.

  As shown in FIG. 5A, in the duty measurement when a delay circuit having a delay time shorter than the “High” level period of the pre-correction clock signal is selected, first, the selector SEL2 performs the pre-correction based on the control signal SGB. The clock signal CLKA is selected and output as the pre-correction clock signal CLKB.

  Next, the flip-flop with reset FF1 cancels the reset based on the reset signal, inputs the pre-correction clock signal CLKA as a clock, and outputs the signal A. Here, since the data is latched when the pre-correction clock signal CLKA rises from “Low” to “High”, the signal A has a cycle twice that of the pre-correction clock signal CLKA.

Subsequently, the selector SEL1 selects any one of the delay circuits DA1 to DAn based on the control signal SGA. A signal AD delayed from the signal A by a predetermined time (T _DA ) is output from the selector SEL1. Here, the delay time T _DA of the delay circuit DA is shorter than the “High” level period of the pre-correction clock signal CLKA.

  The flip-flop FF2 receives the pre-correction clock signal CLKB as a clock and the signal A as a data signal. When the pre-correction clock signal CLKA falls from "High" to "Low", the "High" level signal A is latched, and the "High" level signal B is output from the flip-flop FF2. The flip-flop FF3 inputs the pre-correction clock signal CLKB as a clock and the signal AD as a data signal. When the pre-correction clock signal CLKA falls from “High” to “Low”, the “High” level signal AD is latched, and the “High” level signal C is output from the flip-flop FF3. Here, the signal B and the signal C are synchronous signals having the same period and level.

  Next, the XOR circuit EX1 receives the signal B and the signal C, and outputs a signal obtained by logical operation as the signal Out. Since the signal B and the signal C are synchronous signals having the same period and level, the signal Out is at the “Low” level, and the signal can be observed from outside the duty measurement / correction circuit 1.

  As shown in FIG. 5B, in the duty measurement / correction when the delay circuit having a delay time longer than the “High” level period of the pre-correction clock signal is selected, the pre-correction clock signal CLKA is converted into the 2-input AND circuit AND1. Are input to the 2-input OR circuit OR1.

Next, the delay circuit DA having a delay time longer than the “High” level period of the pre-correction clock signal CLKA is selected by the selector 1 based on the control signal SGA, and the signal AD delayed by a predetermined time is output from the selector SEL1. The At this time, the delay circuit DB having the delay time T _DB subtracted by the delay time T _DA of the delay circuit DA from the “High” level period TH (50%) of the clock signal CLK is selected by the selector 3 based on the control signal SGA. A signal D selected and delayed by a predetermined time is output from the selector SEL3.

  Subsequently, the flip-flop FF3 inputs the pre-correction clock signal CLKB as a clock and the signal AD as a data signal. When the pre-correction clock signal CLKA falls from “High” to “Low”, the “Low” level signal AD is latched, and the “Low” level signal C is output from the flip-flop FF3. At this time, the signal B output from the flip-flop FF2 is at the “High” level, and the signal C is an inverted signal of the signal B.

  Next, the XOR circuit EX1 receives the signal B and the signal C, and outputs a signal obtained by logical operation as the signal Out. Since the signal C is an inverted signal of the signal B, the signal Out is at “High” level, and the signal can be observed from outside the duty measurement / correction circuit 1.

Therefore, the signal Out is most close to the "High" level period of the delay time _{T DA} is the uncorrected clock signal CLKA of the delay circuit DA immediately changes to "High" level from "Low" level. That, if increasing the number n of the delay circuit DA, it is possible to substantially the same as the "High" level period of the correction clock signal before the delay time T _DA of the delay circuit DA. The number n of the delay circuits DA may be appropriately selected according to the level required for the measurement of the pre-correction clock signal CLKA. The selector SEL1 functions as a selection unit that selects a delay circuit having a value closest to the duty of the pre-correction clock signal CLKA.

Subsequently, the delay circuit DB is selected using the control signal SGA for selecting the delay circuit DA closest to the “High” level period of the pre-correction clock signal. Delay time _{T DB} delayed signal D of the delay circuit DB is outputted from the selector SEL3.

  The 2-input OR circuit OR1 receives the signal D and the pre-correction clock signal CLKA, performs a logical operation, and outputs a signal E. The 2-input AND circuit AND1 receives the signal D and the pre-correction clock signal CLKA, performs a logical operation, and outputs a signal F. Here, the “High” level period of the signal E is substantially the same as the “High” level period TH (50%) of the clock signal CLK.

  Next, the selector SEL4 receives the signal E and the signal F, selects the signal E based on the control signal SGB, and outputs it as the corrected signal CLKC. The corrected clock signal CLKC is used as a clock signal necessary for the operation of various circuits (not shown) provided in the semiconductor device 20. The selector SEL3 functions as selection means for selecting a delay circuit necessary for correcting the pre-correction clock signal CLKA.

  Here, at the time of duty correction, the operation of the flip-flop FF1 may be stopped using a reset signal. In this case, since the operations of the duty measurement circuit unit 2 other than the selector SEL2 and the inverter INV2 are stopped, power saving can be achieved. Note that the number n of the delay circuits DA may be appropriately selected according to the level required for the correction of the pre-correction clock signal CLKA.

  As shown in FIG. 6A, in the duty measurement when the delay circuit having a delay time shorter than the “Low” level period of the pre-correction clock signal is selected, first, the selector SEL2 is connected to the inverter INV2 based on the control signal SGB. The inverted signal of the pre-correction clock signal CLKA inverted by is selected and output as the pre-correction clock signal CLKB.

  Next, the flip-flop FF1 with reset cancels the reset based on the reset signal, inputs the inverted signal of the pre-correction clock signal CLKA as a clock, and outputs the signal A. Here, since the data is latched when the pre-correction clock signal CLKA falls from “High” to “Low”, the signal A has a cycle twice that of the pre-correction clock signal CLKA.

Subsequently, the selector SEL1 selects any one of the delay circuits DA1 to DAn based on the control signal SGA. A signal AD delayed from the signal A by a predetermined time (T _DA ) is output from the selector SEL1. Here, the delay time T _DA of the delay circuit DA is shorter than the “Low” level period of the pre-correction clock signal CLKA.

  The flip-flop FF2 receives the pre-correction clock signal CLKB as a clock and the signal A as a data signal. When the pre-correction clock signal CLKA rises from "Low" to "High", the "Low" level signal A is latched and the "Low" level signal B is output from the flip-flop FF2. The flip-flop FF3 inputs the pre-correction clock signal CLKB as a clock and the signal AD as a data signal. When the pre-correction clock signal CLKA rises from “Low” to “High”, the “Low” level signal AD is latched, and the “Low” level signal C is output from the flip-flop FF3. Here, the signal B and the signal C are synchronous signals having the same period and level.

  Next, the XOR circuit EX1 receives the signal B and the signal C, and outputs a signal obtained by logical operation as the signal Out. Since the signal B and the signal C are synchronous signals having the same period and level, the signal Out is at the “Low” level, and the signal can be observed from outside the duty measurement / correction circuit 1.

  As shown in FIG. 6B, in the duty measurement / correction when the delay circuit having a delay time longer than the “Low” level period of the pre-correction clock signal is selected, the pre-correction clock signal CLKA is converted into the 2-input AND circuit AND1. Are input to the 2-input OR circuit OR1.

Next, the delay circuit DA having a delay time longer than the “Low” level period of the pre-correction clock signal CLKA is selected by the selector 1 based on the control signal SGA, and the signal AD delayed by a predetermined time is output from the selector SEL1. The At this time, the delay circuit DB having the delay time T _DB subtracted by the delay time T _DA of the delay circuit DA from the “Low” level period TL (50%) of the clock signal CLK is selected by the selector 3 based on the control signal SGA. A signal D selected and delayed by a predetermined time is output from the selector SEL3.

  Subsequently, the flip-flop FF3 inputs the pre-correction clock signal CLKB as a clock and the signal AD as a data signal. When the pre-correction clock signal CLKA rises from “Low” to “High”, the “High” level signal AD is latched, and the “High” level signal C is output from the flip-flop FF3. At this time, the signal B output from the flip-flop FF2 is at the “Low” level, and the signal C is an inverted signal of the signal B.

  Next, the XOR circuit EX1 receives the signal B and the signal C, and outputs a logically operated signal as the signal Out. Since the signal C is an inverted signal of the signal B, the signal Out is at “High” level, and the signal can be observed from outside the duty measurement / correction circuit 1.

Therefore, the signal Out is most close to the "Low" level period of the delay time _{T DA} is the uncorrected clock signal CLKA of the delay circuit DA immediately changes to "High" level from "Low" level. That is, if the number n of the delay circuits DA is increased, the delay time T _DA of the delay circuit DA becomes substantially the same as the “Low” level period of the clock signal before correction. The number n of the delay circuits DA may be appropriately selected according to the level required for the measurement of the pre-correction clock signal CLKA.

Subsequently, the delay circuit DB is selected using the control signal SGA that selects the delay circuit DA closest to the “Low” level period of the pre-correction clock signal. Delay time _{T DB} delayed signal D of the delay circuit DB is outputted from the selector SEL3.

  The 2-input OR circuit OR1 receives the signal D and the pre-correction clock signal CLKA, performs a logical operation, and outputs a signal E. The 2-input AND circuit AND1 receives the signal D and the pre-correction clock signal CLKA, performs a logical operation, and outputs a signal F. Here, the “Low” level period of the signal F is substantially the same as the “Low” level period TL (50%) of the clock signal CLK.

  Next, the selector SEL4 receives the signal E and the signal F, selects the signal F based on the control signal SGB, and outputs it as the corrected signal CLKC. The corrected clock signal CLKC is used as a clock signal necessary for the operation of various circuits (not shown) provided in the semiconductor device 20.

  Here, at the time of duty correction, the operation of the flip-flop FF1 may be stopped using a reset signal. In this case, since the operations of the duty measurement circuit unit 2 other than the selector SEL2 and the inverter INV2 are stopped, power saving can be achieved. Note that the number n of the delay circuits DA may be appropriately selected according to the level required for the correction of the pre-correction clock signal CLKA.

To determine whether the “High” level period or the “Low” level period of the pre-correction clock signal CLKA has a duty of 50% or less, for example, the delay circuit D _An having the maximum delay time is selected and controlled. When the output signal CLKB of the selector SEL2 is selected from the signal SGB, either the pre-correction clock signal CLKA or its inverted signal, and the signal Out output from the duty measurement circuit unit 2 changes to the “High” level, the duty is 50%. It can be determined that:

As described above, in the semiconductor integrated circuit of this embodiment and the duty measurement / correction method using the same, delay circuits DA1 to DAn, XOR circuit EX1, flip-flops FF1 to FF3, inverter INV1, inverter INV2, selector SEL1, and Duty measurement circuit 2 comprising a duty measurement circuit unit 2 comprising a selector SEL2 and a duty correction circuit 3 comprising a delay circuit DB1 to DBn, a 2-input AND circuit AND1, an 2-input OR circuit OR1, a selector SEL3 and a selector SEL4 A correction circuit 1 is provided. The pre-correction clock signal CLKA with the changed duty ratio is input to the duty measurement circuit unit 2 and the duty correction circuit 3. The delay time T _DA of the delay circuit DA of the duty measurement circuit unit 2 when the signal Out output from the duty measurement circuit unit 2 changes from the “Low” level to the “High” level is set as the duty of the clock signal CLKA before correction. It is selected by the selector SEL1 and can be measured by the duty measurement circuit unit 2. At this time, the delay circuit DB of the duty correction circuit unit 3 paired with the delay circuit DA of the duty measurement circuit unit 2 is selected by the selector SEL3, and the duty correction circuit unit 3 can correct the duty of the clock signal CLKA before correction. it can.

  For this reason, without using an external sampling clock signal having a frequency several times larger than the internal clock signal of the semiconductor device 20 as in the prior art, only the signal in the semiconductor layer 20 is used and the clock signal CLKA before correction is used. Duty measurement and correction can be performed with high accuracy. In addition, the circuit configuration is relatively simpler than before, duty measurement and correction can be performed simply, and there is no need to use an expensive measuring device.

  In this embodiment, an inverter chain is used for the delay circuit, but a resistor, an RC delay circuit, or the like may be used. Further, although one of the plurality of delay circuits is selected using the selector and the clock signal is delayed, a plurality of selection means for selecting one of the plurality of delay circuits using the selector may be provided. . In this case, the number of delay circuits can be reduced as compared with the case of the one-stage configuration by increasing the delay time of the first-stage delay circuit and decreasing the delay time of the second-stage and subsequent delay circuits. It becomes possible. Further, the duty measurement / correction circuit 1 directly receives the pre-correction clock signal from the PLL circuit 4, but may directly input the pre-correction clock signal via the circuit.

  Next, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a configuration of the semiconductor device. In this embodiment, two types of clock signals are input to the duty measurement / correction circuit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 7, the semiconductor device 20 a is provided with a duty measurement / correction circuit 1 a, a PLL circuit 4, and a PLL circuit 4 a as a semiconductor integrated circuit, and a corrected clock output from the duty measurement / correction circuit 1. Various circuits (not shown) in the semiconductor device 20 operate based on the signal CLKC.

  The duty measurement / correction circuit 1 a includes a duty measurement circuit unit 2, a duty correction circuit unit 3, and a register 5. The clock selection circuit 6 inputs, for example, a clock signal with a frequency of 800 MHz output from the PLL circuit 4 and a clock signal with a frequency of 400 MHz output from the PLL circuit 4a, for example, and selects one of the clock signals. Output. An ideal clock signal CLK output from the clock selection circuit 6 and having a duty ratio of 50% or 50% due to a change in the circuit threshold due to manufacturing variations or the like, the uncorrected clock signal CLKA whose duty ratio has changed is measured for duty. The signal is input to the circuit unit 2 and the duty correction circuit unit 3.

  Next, the operation of the duty measurement circuit will be described with reference to FIGS. 8 and 9. FIG. 8 is a diagram showing the degree of delay time of the delay circuit, and FIG. 9 is a combination table of delay circuits stored in the register. FIG. 9A is a diagram showing a combination table of delay circuits when the pre-correction clock signal is 800 MHz, and FIG. 9B is a diagram showing a combination table of delay circuits when the pre-correction clock signal is 400 MHz. It is.

As shown in FIG. 8, the delay time T _DAn of the delay circuit DAn provided in the duty measurement circuit unit 2 is maximized, the delay time is gradually decreased, and the delay time T _DA1 of the delay circuit DA1 is set to the minimum. . Similarly, the delay time T _DAn of the delay circuit DAn provided in the duty correction circuit unit 3 to the maximum, gradually decreases the delay time, to set the delay time T _DA1 of the delay circuit DB1 minimized. The delay circuit DA is selected by the control signal SGA, and the delay circuit DB is selected by the control signal SGC. The delay time for each delay circuit is
T _DAm = T _DBm・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (3)
It is preferable to set the same. Here, the value of m is 1 to n. The delay time interval for each delay circuit is preferably changed to be the same.

  As shown in FIG. 9A, the delay circuits DA provided in the duty measurement circuit unit 2 selected by the selector SEL1 based on the control signal SGA are the delay circuits DA1 to DA ((1/2) n). On the other hand, the delay circuits DB provided in the duty correction circuit unit 3 selected by the selector SEL3 based on the control signal SGC are delay circuits DB1 to DB ((1/2) n). For example, when the delay circuit DA selected by the selector SEL1 based on the control signal SGA is the delay circuit DA1, the delay circuit DB selected by the selector SEL3 based on the control signal SGC is the delay circuit DB ((1/2 N), and the sum of the delay time of the delay circuit DA and the delay time of the delay circuit DB is the “High” level period TH (50%) of the ideal clock signal CLK, or “ It is set at time T1, which is the Low ”level period TL (50%).

  As shown in FIG. 9B, the delay circuit DA provided in the duty measurement circuit unit 2 selected by the selector SEL1 based on the control signal SGA is the delay circuits DA1 to DAn, while the control signal SGC Basically, the delay circuits DB provided in the duty correction circuit unit 3 selected by the selector SEL3 are the delay circuits DB1 to DBn. When the delay circuit DA selected by the selector SEL1 based on the control signal SGA is, for example, the delay circuit DA1, the delay circuit DB selected by the selector SEL3 based on the control signal SGC becomes the delay circuit DBn, and the delay circuit DA The delay time of the delay circuit DB is equal to the ideal “High” level period TH (50%) × 2 of the clock signal CLK, or the ideal “Low” level period TL ( 50%) × 2, which is set to time T1 × 2.

  Here, when the frequency f of the pre-correction clock signal CLKA becomes f / 2, the number of delay circuits is set to double, and the sum of the delay time of the delay circuit DA and the delay time of the delay circuit DB is set to double. In other words, the gear ratio is changed. Since the duty measurement and correction of the pre-correction clock signal CLKA can be performed in the same manner as in the first embodiment, the description thereof is omitted.

As described above, in the semiconductor integrated circuit according to the present embodiment, the duty measurement circuit unit including the delay circuits DA1 to DAn, the XOR circuit EX1, the flip-flops FF1 to FF3, the inverter INV1, the inverter INV2, the selector SEL1, and the selector SEL2. 2, a combination table of the duty correction circuit 3 including the delay circuits DB1 to DBn, the 2-input AND circuit AND1, the 2-input OR circuit OR1, the selector SEL3, and the selector SEL4, and the delay circuit DA and the delay circuit DB is stored. A duty measurement / correction circuit 1 including a register is provided. The pre-correction clock signal CLKA selected by the clock selection circuit 6 and having a changed duty ratio having the frequency f or the frequency f / 2 is input to the duty measurement circuit unit 2 and the duty correction circuit 3. The delay time T _DA of the delay circuit DA of the duty measurement circuit unit 2 when the signal Out output from the duty measurement circuit unit 2 changes from the “Low” level to the “High” level is set as the duty of the clock signal CLKA before correction. It is selected by the selector SEL1 and can be measured by the duty measurement circuit unit 2. At this time, the delay circuit DB of the duty correction circuit unit 3 paired with the delay circuit DA of the duty measurement circuit unit 2 is selected by the selector SEL3, and the duty correction circuit unit 3 can correct the duty of the clock signal CLKA before correction. it can.

  For this reason, it is stored in the register 5 using only the signal in the semiconductor layer 20 without using an external sampling clock signal having a frequency several times larger than the internal clock signal of the semiconductor device 20 as in the prior art. From the combination table of the delay circuit DA and the delay circuit DB, the duty measurement and correction of the two types of pre-correction clock signals CLKA having different frequencies can be performed with high accuracy. In addition, the circuit configuration is relatively simpler than before, duty measurement and correction can be performed simply, and there is no need to use an expensive measuring device.

  In this embodiment, the combination of the frequencies of the pre-correction clock signal output from the PLL circuit is f and f / 2, but other combinations may be used.

  Next, a semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 10 is a block diagram illustrating a configuration of the semiconductor device. In this embodiment, three types of clock signals are input to the duty measurement / correction circuit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 10, the semiconductor device 20 b is provided with a duty measurement / correction circuit 1 a, a PLL circuit 4, a PLL circuit 4 a, and a PLL circuit 4 b as semiconductor integrated circuits, which are output from the duty measurement / correction circuit 1. Various circuits (not shown) in the semiconductor device 20 operate based on the corrected clock signal CLKC.

  The clock selection circuit 6 is output from the PLL circuit 4, for example, a clock signal having a frequency of 800 MHz, output from the PLL circuit 4a, for example, a clock signal having a frequency of 400 MHz, and output from the PLL circuit 4b, for example, a frequency A 200 MHz clock signal is input, and one of the clock signals is selected and output. An ideal clock signal CLK output from the clock selection circuit 6 and having a duty ratio of 50% or 50% due to a change in the circuit threshold due to manufacturing variations or the like, the uncorrected clock signal CLKA whose duty ratio has changed is measured for duty. The signal is input to the circuit unit 2 and the duty correction circuit unit 3.

  Next, the operation of the duty measurement circuit will be described with reference to FIG. 11. FIG. 11 is a diagram showing a combination table of delay circuits stored in the register. FIG. 11 (a) is a case where the clock signal before correction is 800 MHz. FIG. 11B is a diagram illustrating a combination table of delay circuits when the pre-correction clock signal is 400 MHz, and FIG. 11C is a delay when the pre-correction clock signal is 200 MHz. It is a figure which shows the combination table of a circuit. Here, the degree of delay time of the delay circuit DA and the delay circuit DB is set to be the same as that shown in FIG. 8 of the second embodiment.

  As shown in FIG. 11A, the delay circuits DA provided in the duty measurement circuit unit 2 selected by the selector SEL1 based on the control signal SGA are the delay circuits DA1 to DA ((1/4) n). On the other hand, the delay circuits DB provided in the duty correction circuit unit 3 selected by the selector SEL3 based on the control signal SGC are the delay circuits DB1 to DB ((1/4) n). For example, when the delay circuit DA selected by the selector SEL1 based on the control signal SGA is the delay circuit DA1, the delay circuit DB selected by the selector SEL3 based on the control signal SGC is the delay circuit DB ((1/4 N), and the sum of the delay time of the delay circuit DA and the delay time of the delay circuit DB is the “High” level period TH (50%) of the ideal clock signal CLK, or “ It is set at time T1, which is the Low ”level period TL (50%).

  As shown in FIG. 11B, the delay circuits DA provided in the duty measurement circuit unit 2 selected by the selector SEL1 based on the control signal SGA are the delay circuits DA1 to DA ((1/2) n). On the other hand, the delay circuits DB provided in the duty correction circuit unit 3 selected by the selector SEL3 based on the control signal SGC are delay circuits DB1 to DB ((1/2) n). For example, when the delay circuit DA selected by the selector SEL1 based on the control signal SGA is the delay circuit DA1, the delay circuit DB selected by the selector SEL3 based on the control signal SGC is the delay circuit DB ((1/2 N), and the sum of the delay time of the delay circuit DA and the delay time of the delay circuit DB is “high” level period TH (50%) × 2 of the ideal clock signal CLK, or the ideal clock signal CLK. “Low” level period TL (50%) × 2 is set to time T1 × 2.

  As shown in FIG. 11C, the delay circuit DA provided in the duty measurement circuit unit 2 selected by the selector SEL1 based on the control signal SGA is the delay circuits DA1 to DAn, while the control signal SGC Basically, the delay circuits DB provided in the duty correction circuit unit 3 selected by the selector SEL3 are the delay circuits DB1 to DBn. When the delay circuit DA selected by the selector SEL1 based on the control signal SGA is, for example, the delay circuit DA1, the delay circuit DB selected by the selector SEL3 based on the control signal SGC becomes the delay circuit DBn, and the delay circuit DA The delay time of the delay circuit DB and the delay time of the delay circuit DB are equal to the ideal clock signal CLK “High” level period TH (50%) × 4 or the ideal clock signal CLK “Low” level period TL ( 50%) × 4, which is set to time T1 × 4.

  Here, when the frequency f of the pre-correction clock signal CLKA becomes f / 2, the number of delay circuits is set to double, and the sum of the delay time of the delay circuit DA and the delay time of the delay circuit DB is set to double. When the frequency f becomes f / 4, the number of delay circuits is set to 4 times, and the sum of the delay time of the delay circuit DA and the delay time of the delay circuit DB is set to 4 times, that is, the gear ratio is changed. Since the duty measurement and correction of the pre-correction clock signal CLKA can be performed in the same manner as in the first embodiment, the description thereof is omitted.

As described above, in the semiconductor integrated circuit according to the present embodiment, the duty measurement circuit unit including the delay circuits DA1 to DAn, the XOR circuit EX1, the flip-flops FF1 to FF3, the inverter INV1, the inverter INV2, the selector SEL1, and the selector SEL2. 2, a combination table of the duty correction circuit 3 including the delay circuits DB1 to DBn, the 2-input AND circuit AND1, the 2-input OR circuit OR1, the selector SEL3, and the selector SEL4, and the delay circuit DA and the delay circuit DB is stored. A duty measurement / correction circuit 1 including a register is provided. The pre-correction clock signal CLKA selected by the clock selection circuit 6 and having a changed duty ratio having the frequency f, the frequency f / 2, or the frequency f / 4 is input to the duty measurement circuit unit 2 and the duty correction circuit 3. . The delay time T _DA of the delay circuit DA of the duty measurement circuit unit 2 when the signal Out output from the duty measurement circuit unit 2 changes from the “Low” level to the “High” level is set as the duty of the clock signal CLKA before correction. It is selected by the selector SEL1 and can be measured by the duty measurement circuit unit 2. At this time, the delay circuit DB of the duty correction circuit unit 3 paired with the delay circuit DA of the duty measurement circuit unit 2 is selected by the selector SEL3, and the duty correction circuit unit 3 can correct the duty of the clock signal CLKA before correction. it can.

  For this reason, it is stored in the register 5 using only the signal in the semiconductor layer 20 without using an external sampling clock signal having a frequency several times larger than the internal clock signal of the semiconductor device 20 as in the prior art. From the combination table of the delay circuit DA and the delay circuit DB, the duty measurement and correction of the three types of the pre-correction clock signal CLKA having different frequencies can be performed with high accuracy. In addition, the circuit configuration is relatively simpler than before, duty measurement and correction can be performed simply, and there is no need to use an expensive measuring device.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in this embodiment, the duty measurement / correction circuit is used to measure and correct the duty of the clock signal before correction, but the duty correction circuit unit is omitted and only the duty measurement is performed using the duty measurement circuit unit. May be.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A clock signal that is output from the PLL circuit and has a duty ratio of 50% or shorter than 50% and having a “High” level period or a “Low” level period, and the delay that delays the clock signal. A duty having a plurality of delay means having different times and measuring the delay time of the delay means selected by the selector as the duty of the clock signal immediately after the output signal changes from the “Low” level to the “High” level A semiconductor integrated circuit comprising a measurement circuit unit.

(Additional remark 2) The said delay means is a semiconductor integrated circuit of Additional remark 1 comprised from the inverter chain.

1 is a block diagram showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. The figure which shows the relationship between the duty of the clock signal which concerns on Example 1 of this invention, and the delay time of a delay circuit. FIG. 3 is a diagram illustrating the degree of delay time of the delay circuit according to the first embodiment of the invention. FIG. 6 is a diagram showing switching between a “High” level period and a “Low” level period of a clock signal in duty measurement / correction according to the first embodiment of the present invention. 4 is a timing chart showing the operation of the duty measurement / correction circuit using the “High” level period of the clock signal according to the first embodiment of the present invention. 4 is a timing chart showing the operation of the duty measurement / correction circuit using the “Low” level period of the clock signal according to the first embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. The figure which shows the grade of the delay time of the delay circuit which concerns on Example 2 of this invention. The figure which shows the combination table of the delay circuit stored in the register | resistor which concerns on Example 2 of this invention. FIG. 6 is a block diagram showing a configuration of a semiconductor device according to Example 3 of the invention. The figure which shows the combination table of the delay circuit stored in the register | resistor which concerns on Example 3 of this invention.

Explanation of symbols

1, 1a Duty measurement / correction circuit 2 Duty measurement circuit unit 3 Duty correction circuit unit 4, 4a, 4b PLL circuit 5 Register 6 Clock selection circuit 20, 20a, 20b Semiconductor device AND1 2-input AND circuit CLK Clock signal CLKA, CLKB Correction Before clock signal CLKC Corrected clock signal DA1, DA1, DAn, DB1, DB2, DB3 Delay circuit EX1 XOR circuit FF1, FF2, FF3 Flip-flop INV1, INV2 Inverter OR1 Two-input OR circuit SEL1, SEL2, SEL3, SEL4 Selector SGA, SGB, SGC Control signal SSA Frequency selection signal T _DA Delay circuit DA Delay time T _DB Delay circuit DB delay time TH “High” level period TL “Low” level period

Claims (5)

A clock signal having a duty cycle of 50%, a “High” level period or a “Low” level period shorter than 50%;
The delay of the delay means, which is selected immediately after the output signal changes from the “Low” level to the “High” level, having a plurality of delay means having different delay times for inputting the clock signal and delaying the clock signal. A duty measurement circuit unit for measuring time as a duty of the clock signal;
A semiconductor integrated circuit comprising: A second clock signal having a “High” level period or a “Low” level period shorter than the first clock signal having a duty ratio of 50% and 50%;
Immediately after the second clock signal is input and there are a plurality of first delay means having different delay times for delaying the second clock signal, and the output signal changes from “Low” level to “High” level. A duty measurement circuit unit that measures a first delay time of the first delay means selected as a duty of the second clock signal;
A plurality of second delay means for receiving the second clock signal and delaying the second clock signal, the first clock signal having a duty of 50%; A duty correction circuit unit that selects the second delay means having a second delay time obtained by subtracting the delay time, and corrects the duty of the second clock signal using the second delay time;
A semiconductor integrated circuit comprising: A second clock signal having a “High” level period or a “Low” level period shorter than the first clock signal having a duty ratio of 50% and 50%;
A third clock signal having a frequency different from that of the second clock signal and having a short "High" level period or a "Low" level period;
A register for storing a combination table of information of a plurality of first and second delay means having different delay times for delaying the second and third clock signals;
The second or third clock signal is input, and the second or third clock signal has a plurality of first delay means having different delay times, and the output signal is based on the combination table. A duty measuring circuit unit for measuring a first delay time of the first delay means selected immediately after the signal is changed from “Low” level to “High” level as a duty of the second or third clock signal; ,
The second or third clock signal is input, and the second or third clock signal is delayed, and the second delay means has a different delay time. Based on the combination table, the second and third clock signals are delayed. Selecting the second delay means having a second delay time obtained by subtracting the first delay time from half the time of one or two cycles of the second or third clock signal, and setting the second delay time to A duty correction circuit unit that corrects the duty of the second or third clock signal using,
A semiconductor integrated circuit comprising:   4. The semiconductor integrated circuit according to claim 2, wherein each of the first and second delay means includes an inverter chain. Inputting a second clock signal having a “High” level period or a “Low” level period shorter than the first clock signal having a duty ratio of 50% and 50% to the duty measurement circuit unit and the duty correction circuit unit;
Immediately after the second clock signal is delayed by a plurality of first delay means provided in the duty measurement circuit unit, and the output signal of the duty measurement circuit unit changes from “Low” level to “High” level. Measuring a first delay time of the selected first delay means as a duty of the second clock signal;
The first delay time is subtracted from the time of 50% duty of the first clock signal from among a plurality of second delay means provided in the duty correction circuit section for delaying the second clock signal. Selecting the second delay means having the second delay time, and correcting the duty of the second clock signal using the second delay time;
A duty measurement / correction method using a semiconductor integrated circuit.

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