JP5439964B2 - Delay comparison circuit, delay comparison method, delay circuit, and semiconductor integrated circuit - Google Patents

Description

  The embodiments referred to in this application relate to a delay comparison circuit, a delay comparison method, a delay circuit, and a semiconductor integrated circuit.

  Digital DLL (Delay Locked Loop) is used in various circuits, for example, as a (phase) clock generation circuit necessary for realizing high-speed data transfer with a synchronous DRAM (SDRAM). ing.

  Specifically, a DDR (Double Data Rate) memory interface provided with a first delay line for measuring the clock period and a second delay line for controlling the phase (timing) for capturing data in the clock period. It has been known.

  When such two delay lines (digital DLL) are provided, it is necessary to check a delay difference (phase difference) between the delay lines, and a delay comparison circuit is used for that purpose.

  FIG. 1 is a block diagram schematically showing an example of a conventional delay comparison circuit, and FIG. 2 is a timing diagram for explaining the operation of the delay comparison circuit shown in FIG.

  In FIG. 1, reference numeral 101 denotes a first delay line, 102 denotes a second delay line, 103 denotes a first additional delay circuit, 104 denotes a second additional delay circuit, and 105 denotes a flip-flop.

  As shown in FIG. 1, the conventional delay comparison circuit includes, for example, first and second delay lines 101 and 102, first and second additional delay circuits 103 and 104, and a flip-flop 105.

  The output signals do1 and do2 of the first and second delay lines 101 and 102 are supplied to a system (for example, a DDR type SDRAM system) and input to the first and second additional delay circuits 103 and 104, respectively. The

  The first and second additional delay circuits 103 and 104 have a plurality of delay units (buffers), and delay the output signals do1 and do2 of the input first and second delay lines 101 and 102 by a buffer. Add and output to flip-flop 105.

  That is, the output signal dc1 of the first additional delay circuit 103 is supplied to the data input terminal D of the flip-flop 105, and the output signal dc2 of the second additional delay circuit 104 is supplied to the clock input terminal CK of the flip-flop 105. .

  As a result, as shown in FIG. 2, the flip-flop 105 captures the level of the output signal dc1 of the first additional delay circuit 103 at the rising timing of the output signal dc2 of the second additional delay circuit 104 (comparison result). cr is output.

  Then, the output signal dc1, dc2 of the two delay lines 101 and 102 is changed by changing the output signal cr of the flip-flop 105 from the high level “H” to the low level “L” or from “L” to “H”. It is designed to grasp the phase difference.

  That is, the delay comparison circuit shown in FIG. 1 inputs the same clock CLK to the two delay lines 101 and 102. The timings of the rising edges of the output signals do1 and do2 of the delay lines 101 and 102 are compared by the flip-flop 105 using the buffers of the first and second additional delay circuits 103 and 104.

  By the way, conventionally, various delay comparison circuits for measuring and evaluating the delay time of the delay line to a short time have been proposed.

JP 2001-091587 A JP 2006-220631 A

  In the delay comparison circuit shown in FIG. 1 described above, the difference in delay time (phase difference) between the two delay lines 101 and 102 is detected by the number of buffers in the additional delay circuits 103 and 104.

  That is, in the delay comparison circuit shown in FIG. 1, only the delay difference between the two delay lines 101 and 102 can be compared with the delay time of one buffer in the additional delay circuits 103 and 104 as a unit.

  Note that the number of delay lines is not limited to two, but can be various as required.

  In recent years, the delay accuracy of the delay circuit and the delay comparison accuracy of the delay comparison circuit have been improved in response to the demand for higher speed (higher frequency) of clocks used in semiconductor integrated circuits and lower clock jitter. I need it.

  In view of the above-described problems, an object of the present application is to provide a delay comparison circuit and a delay comparison method that can compare delay differences (phase differences) in a plurality of delay lines with high accuracy.

According to an embodiment, there is provided a delay comparison circuit including a plurality of delay lines, a plurality of oscillator auxiliary circuits, a plurality of counters, a calculation circuit, and a comparison unit.

Each oscillator auxiliary circuit included in the plurality of delay lines converts each delay line into an oscillator, and each counter counts the oscillation output of each oscillator-generated delay line . The calculation unit calculates a reference count value based on each count value obtained by the plurality of counters , and the comparison unit compares each count value with the reference count value.

  The disclosed delay comparison circuit and delay comparison method have an effect of comparing phase differences in a plurality of delay lines with high accuracy.

It is a block diagram which shows an example of the conventional delay comparison circuit roughly. FIG. 2 is a timing chart for explaining the operation of the delay comparison circuit shown in FIG. 1. It is a block diagram which shows the delay comparison circuit of 1st Example. FIG. 4 is a block diagram illustrating an example of a delay line in the delay comparison circuit illustrated in FIG. 3. FIG. 4 is a timing chart for explaining the operation of the delay comparison circuit shown in FIG. 3. It is a figure which shows an example of the semiconductor integrated circuit to which the delay comparison circuit of 1st Example is applied. FIG. 7 is a diagram for explaining the operation of the semiconductor integrated circuit shown in FIG. 6. It is a figure for demonstrating the calculation operation | movement of a reference | standard count value. It is a block diagram which shows an example of a reference | standard count value calculation circuit. It is a block diagram which shows the other example of a reference | standard count value calculation circuit. It is a figure for demonstrating the processing operation in the case of using a center value as a reference | standard count value. It is a block diagram which shows the delay circuit of 2nd Example. FIG. 13 is a block diagram illustrating a main part in the delay circuit of FIG. 12. It is FIG. (1) for demonstrating operation | movement of the delay circuit of 2nd Example. FIG. 10 is a second diagram for explaining the operation of the delay circuit according to the second embodiment; It is a block diagram which shows an example of the semiconductor integrated circuit to which a delay circuit is applied.

  Hereinafter, embodiments of the delay comparison circuit, the delay comparison method, and the delay circuit will be described in detail with reference to the accompanying drawings.

  3 is a block diagram showing a delay comparison circuit of the first embodiment, FIG. 4 is a block diagram showing an example of a delay line in the delay comparison circuit shown in FIG. 3, and FIG. 5 is an operation of the delay comparison circuit shown in FIG. It is a timing diagram for demonstrating.

  In FIG. 3, reference numeral 1 is a first delay line, 2 is a second delay line, 3 is a first counter, 4 is a second counter, and 5 is a comparator. Reference numerals 6 and 7 indicate selectors, and 8 and 9 indicate inverters.

  As shown in FIG. 3, the delay comparison circuit of the first embodiment includes selectors 6 and 7, first and second delay lines 1 and 2, first and second counters 3 and 4, a comparison unit 5, and Inverters 8 and 9 are provided. Here, the comparison unit 5 includes a difference calculation circuit 51 and a difference allowance determination circuit 52.

  As shown in FIG. 4, the first delay line 1 selects a delay unit 11 having a plurality of delay units (DUs) that sequentially delay the clock CLK, and an output of any delay unit in the delay unit 11. And a selector 12 that outputs the delayed clock DO1.

  Here, a delay amount setting code DSC1 is input to the selector 12, and an output signal of a delay unit having a delay amount corresponding to the delay amount setting code DSC1 is selected and output. The second delay line 2 is substantially the same as the first delay line 1.

  As shown in FIG. 3, the selectors 6 and 7 receive the clock CLK and the output signals DO1 and DO2 of the delay lines 1 and 2 inverted through the inverters 8 and 9, respectively. Is to be selected.

  That is, during normal operation, the selectors 6 and 7 select the clock CLK by the selection signal SS and supply the clock CLK to the first and second delay lines 1 and 2, respectively, and the signals DO1 and DO2 obtained by delaying the clock CLK are Supplied to the system.

  On the other hand, during the delay time comparison operation, the selectors 6 and 7 select the output signals of the inverters 8 and 9 based on the selection signal SS and supply them to the first and second delay lines 1 and 2, respectively.

  Here, the circuit that feeds back the output signal DO1 of the first delay line 1 to its input via the inverter 8 and the selector 6 functions as an oscillator that oscillates at a first frequency corresponding to the delay time of the first delay line 1. .

  Similarly, a circuit that feeds back the output signal DO2 of the second delay line 2 to its input via the inverter 9 and the selector 7 functions as an oscillator that oscillates at a second frequency corresponding to the delay time of the second delay line 2. .

  That is, as shown in FIG. 3 and FIG. 5, the output signal DO1 of the first delay line 1 that oscillates at the first frequency is counted by the first counter 3 only during a fixed test period TP, and the first counter The count value CNT1 of 3 is supplied to the comparison unit 5.

  Similarly, the output signal DO2 of the second delay line 2 oscillating at the second frequency is counted by the second counter 4 only for a fixed test period TP, and the count value CNT2 of the second counter 4 is also compared with the comparison unit 5. To be supplied.

  Here, the difference between the first and second count values CNT1 and CNT2 increases as the period TP for counting the oscillation outputs DO1 and DO2 of the first and second delay lines 1 and 2 that are ring-oscillated is longer. Become.

  That is, even if the difference in delay time between the first and second delay lines 1 and 2 is small, they are converted into ring oscillators, and the oscillation outputs DO1 and DO2 are counted in the period TP and compared, thereby reducing the delay time. The difference can be amplified and detected according to the period TP.

  The count value CNT1 from the first counter 3 and the count value CNT2 from the second counter 4 are supplied to the difference detection circuit 51, and the difference detection circuit 51 outputs the difference value DCNT.

  The difference value DCNT from the difference detection circuit 51 is supplied to the difference allowance determination circuit 52, and whether or not the difference value DCNT is within a predetermined allowance is determined.

  As an example, when the count value CNT1 by the first counter 3 is “001110111” (55) and the count value CNT2 by the second counter 4 is “00110011” (51), it is determined that the allowable setting value is “00000100” (4). The result CR is consistent.

  That is, 55 (count value CNT1) −51 (count value CNT2) = 4 ≦ 4 (allowable set value), and therefore, the difference (CNT1−CNT2) is within the allowable set value. ")become.

  On the other hand, if the permissible setting is not set in the difference permissible determination circuit 52, it is determined that the count value CNT1 and the count value CNT2 are different from each other, and a determination result CR of mismatch (“L”) is output.

  As described above, according to the first embodiment, during the delay time comparison operation (test time), the delay lines 1 and 2 are caused to function as ring oscillators using the inverters 8 and 9 and the selectors 6 and 7, These oscillation frequencies are counted by counters 3 and 4.

  Then, the comparison unit 5 compares the count values CNT1 and CNT2 of the counters 3 and 4 to compare the delay time difference (phase difference) between the first delay line 1 and the second delay line 2 with high accuracy. Is possible.

  FIG. 6 is a diagram showing an example of a semiconductor integrated circuit to which the delay comparison circuit of the first embodiment is applied, and FIG. 7 is a diagram for explaining the operation of the semiconductor integrated circuit shown in FIG.

  As shown in FIG. 6, the delay comparison circuit of the first embodiment is not formed on a semiconductor integrated circuit (LSI: semiconductor chip), but for example, a first delay unit macro 10 and a second delay unit macro. 20 and the comparison part macro 50 can also be formed as different macros.

  The first delay unit macro 10 includes the first delay line 1, the first counter 3, and the like, the second delay unit macro 20 includes the second delay line 2, the second counter 4, and the like, and the comparison unit. The macro 50 includes the comparison unit 5.

  As described above, when the first delay unit macro 10, the second delay unit macro 20, and the comparison unit macro 50 are formed separately on the semiconductor chip, a transfer process (OSC) as shown in FIG. 7 is required.

  That is, as shown in FIG. 7, in the semiconductor integrated circuit shown in FIG. 6, first, a delay comparison test mode is set in operation OSA. That is, the selection signal SS is controlled, and the outputs of the inverters 8 and 9 are supplied to the first and second delay lines 1 and 2 to function as ring oscillators.

  Next, proceeding to operation OSB, the first and second counters 3 and 4 count the oscillating output signals (oscillator clocks) DO1 and DO2 of the first and second delay lines 1 and 2.

  Further, proceeding to operation OSC, the comparison unit of the comparison unit macro 50 in which the count values CNT1 and CNT2 counted by the first and second counters 3 and 4 are separated from the first delay unit macro 10 and the second delay unit macro 20. Transfer to 5.

  Then, the process proceeds to operation OSD, the transferred count values CNT1 and CNT2 are compared, and the determination result CR is output. Each operation may be a processing step.

  In the above-described embodiment, two delay lines (first and second delay lines 1 and 2) have been described. However, the number of delay lines can be variously changed as necessary.

  Next, calculation of a reference count value (reference count value) when there are three delay lines will be described.

FIG. 8 is a diagram for explaining the reference count value calculation operation.
As shown in FIG. 8, in the operation of calculating the reference count value when the number of delay lines is three, first, a delay comparison test mode is set in operation OTA. That is, the selection signal SS is controlled to cause the three delay lines to function as a ring oscillator.

  Next, proceeding to operation OTB, the output signals (oscillator clock) of the three oscillating delay lines are counted by the three counters (3a, 3b, 3c).

  Further, the operation proceeds to operation OTC, and a reference count value (CNTr) is calculated by a method described later.

  Then, the process proceeds to operation OTD, where the reference count value (CNTr) is compared with the count value (CNTa, CNTb, CNTc) of each counter (3a, 3b, 3c), and the determination result (CRa, CRb, CRc). Is output. Each operation may be a processing step.

  FIG. 9 is a block diagram showing an example of the reference count value calculation circuit, and shows an example in which the average of the count values of a plurality of (three) counters is used as the reference count value.

  As illustrated in FIG. 9, the reference count value calculation circuit example 31 includes an adder 311, a divider 312, and a counter 313.

  Here, the counters 3a, 3b, 3c correspond to the first counter 3 (second counter 4) of FIG. 3, and in FIG. 9, output signals of three delay lines (not shown) functioning as an oscillator are obtained. Each counts only for a certain test period.

  The adder 311 adds the count values CNTa, CNTb, and CNTc of the three counters 3a, 3b, and 3c (CNTa + CNTb + CNTc), and the divider 312 divides the output signal of the adder 311 by 3 to obtain an average value (CNTa + CNTb + CNTc). ) / 3 is output.

  The counter 313 holds the signal (CNTa + CNTb + CNTc) / 3 supplied from the divider 312 and supplies it as a reference count value CNTr to the comparison units 5a, 5b, 5c.

  The comparison units 5a, 5b, and 5c respectively compare the reference count value CNTr from the counter 313 with the count values CNTa, CNTb, and CNTc of the corresponding counters 3a, 3b, and 3c, respectively, and determine the determination results CRa, CRb, and CRc. Is output.

  FIG. 10 shows another example of the reference count value calculation circuit, and shows an example in which the center of the count values of a plurality (three) counters is used as the reference count value.

  That is, the reference count value calculation circuit 32 shown in FIG. 10 includes a center value extraction unit 321 and a counter 322 that extract center values from the count values CNTa, CNTb, and CNTc.

  FIG. 11 is a diagram for explaining the processing operation when the center value is used as the reference count value, and for explaining the processing operation of the center value extracting unit 321 in FIG.

  As shown in FIG. 11, in the center value extraction process, first, in operation OUA, the count values CNTa, CNTb, CNTc of the three counters 3a, 3b, 3c are received.

  Next, proceeding to operation OUB, CNTb-CNTa and CNTc-CNTa are determined.

  If it is determined in operation OUB that CNTb-CNTa> 0 and CNTc-CNTa <0, or CNTb-CNTa <0 and CNTc-CNTa> 0, the process proceeds to operation OUC and CNTa is set to the reference count value. Defined as CNTr.

  If it is determined in operation OUB that CNTb-CNTa> 0 and CNTc-CNTa> 0, the process proceeds to operation OUD to determine CNTc-CNTb.

  If it is determined in operation OUD that CNTc−CNTb> 0, the process proceeds to operation OUF and CNTb is defined as the reference count value CNTr. If it is determined in operation OUD that CNTc−CNTb <0, the process proceeds to operation OUG to define CNTc as the reference count value CNTr.

  If it is determined in operation OUB that CNTb-CNTa <0 and CNTc-CNTa <0, the process proceeds to operation OUE to determine CNTc-CNTb.

  If it is determined in operation OUE that CNTc−CNTb> 0, the process proceeds to operation OUH, where CNTc is defined as the reference count value CNTr. If the operation OUE determines that CNTc−CNTb <0, the process proceeds to operation OUI to define CNTb as the reference count value CNTr. Each operation may be a processing step.

  The central value extraction unit having the processing operation described with reference to FIG. 11 can be realized by a circuit as hardware, but can also be realized by a program as software.

  Needless to say, the number of delay lines is not limited to two or three, and may be a delay comparison circuit having a larger number of delay lines.

  FIG. 12 is a block diagram showing a delay circuit according to the second embodiment, and shows a delay circuit to which the delay comparison circuit described with reference to FIG. 3 is applied. FIG. 13 is a block diagram showing the main part of the delay circuit of FIG.

  As shown in FIG. 12, the delay circuit of the second embodiment includes first and second delay lines 1 ′ and 2 ′, first and second counters 3 ′ and 4 ′, a comparison unit 5 ′, and first and second delay lines 1 ′ and 2 ′. 1 and second oscillator auxiliary circuits 6 'and 7'.

  Here, the first oscillator auxiliary circuit 6 'corresponds to the selector 6 and the inverter 8 in FIG. 3, and the second oscillator auxiliary circuit 7' corresponds to the selector 7 and the inverter 9 in FIG.

  Although omitted in FIG. 12, for example, each selector of the first and second oscillator auxiliary circuits 6 ′ and 7 ′ is supplied with a selection signal SS, and the first and second delay lines 1 ′, The 2 'output signal is supplied to the system.

  Further, in the delay comparison circuit of the first embodiment, as described with reference to FIG. 9, the number of delay lines is not limited to the first and second, but three or more. May be.

  Furthermore, as described in the delay comparison circuit of the first embodiment, the comparison unit 5 ′ may include the difference calculation circuit 51 and the difference allowance determination circuit 52, and the reference count value is the value of each count value. The average value or the center value of each count value may be used.

  As shown in FIG. 12, the delay circuit of the second embodiment includes a test control circuit 80, first and second code comparison circuits 81 and 91, first and second adders 82 and 92, and first and second adders 82 and 92. Second delay setting circuits 83 and 93 are provided.

  Further, the delay circuit of the second embodiment also includes first and second error holding circuits 84 and 94 and first and second error DU relief decoders 85 and 95.

  The test control circuit 80 supplies the selection code SSC to the first and second code comparison circuits 81 and 91 and the first and second adders 82 and 92. Here, the test control circuit 80 includes a selection code increment circuit that increments the selection code SSC.

  The first and second code comparison circuits 81 and 91 compare the outputs of the first and second error holding circuits 84 and 94 with the selection code SSC, respectively, and firstly pass through the first and second adders 82 and 92, respectively. The second delay amount setting decoders 83 and 93 are controlled. As a result, the first and second delay lines 1 'and 2' output the delay clocks DO1 'and DO2'.

  Here, as shown in FIG. 13, the adder 82 (92) is controlled by the output of the code comparator 81 (91), and an adder that adds the output of the selector 21 to the selected code SSC. 22.

  The first and second error holding circuits 84 and 94 hold the determination results CR1 and CR2 from the comparison unit 5 ′, output them to the first and second code comparison circuits 81 and 91, and the first and second error holding circuits 84 and 94. The error DU is repaired (interlaced processing) via the DU repair decoders 85 and 95.

  As shown in FIG. 13, each of the first and second delay lines 1 ′ and 2 ′ includes a plurality of delay units DU (110, 111,...) And a plurality of selectors provided for each delay unit DU. It has units SU (120, 121,...).

  Each selector unit SU inputs the signal supplied to the corresponding delay unit DU as it is based on the signals from the first and second error DU relief decoders 85 and 95, or skips the corresponding delay unit to the next stage. Select whether to supply the delay unit.

  That is, for example, when the signal from the delay unit 110 at the previous stage is input to the corresponding delay unit 111 as it is, the selector unit 121 turns on the transfer gate 121a and turns off 121b.

  On the other hand, for example, when the selector unit 121 inputs the signal from the delay unit 110 at the previous stage to the delay unit 112 at the next stage by skipping the corresponding delay unit 111, the selector unit 121 turns on the transfer gate 121b and 122a and 122b. Turn off.

  In this manner, the error DU is remedied via the first and second error DU remedy decoders 85 and 95.

  The error DU is detected by setting, for example, a test mode and changing the delay amounts of the first and second delay lines 1 ′ and 2 ′ by the selectors 12 ′ and 22 ′ to be equal to each other. The count values CNT1 and CNT2 of 3 ′ and 4 ′ are compared by the comparison unit 5 ′.

  That is, when the number of delay units DU in the first and second delay lines 1 ′ and 2 ′ is changed equally, for example, if there is an error DU in one delay line, the first and second counters 3 ′, A large difference occurs between the count values CNT1 and CNT2 of 4 ′.

  In addition, in the first and second delay lines 1 ′ and 2 ′, when the number of delay units DU is sequentially increased, the delay time also increases linearly. However, the error DU is caused by the delay unit DU where the linearity is broken. Can be identified.

  As shown in FIG. 13, the selection code SSC and the output (error code) of the error holding circuit 84 (94) are input to the code comparator 81 (91). 1 ”is output.

  That is, when the error unit DU is skipped by the selector unit SU, the number of delay units DU that have decreased due to the skipping is increased.

14 and 15 are diagrams for explaining the operation of the delay circuit of the second embodiment.
As shown in FIG. 14, first, in operation OXA, a selection code SSC is set, and the operation proceeds to operation OXB. The selection code SSC has an initial value of “0” and is sequentially incremented (operation OXI).

  Next, in operation OXB, it is determined whether or not an error selection code exists. If an error selection code exists, the process proceeds to operation OXC. If no error selection code exists, the process proceeds to operation OXD.

  That is, when the error selection code is held in the error holding circuit 84 (94), it is determined in operation OXC whether the selection code SSC is larger than the error selection code held in the error holding circuit 84 (94). The

  If it is determined in operation OXC that the selection code SSC is not equal to or greater than the error selection code, that is, if the error DU is not included in the plurality of delay units that delay the input clock CLK, the operation OXD move on.

  In operation OXD, “0” is added to the selection code SSC, and the output of a predetermined delay unit DU according to the selection code SSC as it is by the selector 12 ′ (22 ′) via the delay amount setting decoder 83 (93). Select.

  On the other hand, in operation OXC, when it is determined that the selection code SSC is equal to or greater than the error selection code, that is, an error DU that has been subjected to the interlace process is included in a plurality of delay units that delay the input clock CLK. Proceed to operation OXE.

  In operation OXE, “1” is added to the selection code SSC, and the selection code SSC is added via the delay amount setting decoder 83 (93) by the selector 12 ′ (22 ′). The output of the predetermined delay unit DU is selected.

  Specifically, as shown in FIG. 15, for example, when the delay unit 111 is defective and the delay unit 111 is skipped as an error DU, a code Code− that selects the delay unit 111 of the error DU 1 is held in the error holding circuit 84.

  Then, when the selector 12 ′ originally selects the output of the delay unit 111 based on the selection code SSC, the selection code SSC (Code-1) is equal to or greater than the error selection code Code-1 (in this case, coincidence). ”Is added to the selection code SSC (Code-2).

  That is, the selector 12 'selects the output of the delay unit 112 by the code Code-2. Thereby, instead of the delay unit 111 of the skipped error DU, the delay clock DO1 'including the delay by the delay unit 112 is output from the selector 12'.

  Returning again to FIG. 14, in the operation OXF, as described in the first embodiment, the oscillator auxiliary circuit 6 ′ (7 ′) causes the oscillator clock DO1 ′ (DO2 ′) of the delay line 1 ′ (2 ′). ) Is counted by the counter 3 ′ (4 ′).

  Further, the operation proceeds to operation OXG, the count value CNT1 of the first counter 3 ′ and the count value CNT2 of the second counter 4 ′ are compared by the comparison unit 5 ′, and if it is determined that the count values CNT1 and CNT2 match, Proceed to OXI.

  In operation OXI, the selection code SSC is incremented, and the process returns to operation OXB to repeat the same processing.

  On the other hand, if it is determined in operation OXG that the count values CNT1 and CNT2 do not match, the operation proceeds to operation OXH, the error selection code is stored in the error holding circuit 84 (94), and the operation proceeds to operation OXI.

  Here, whether or not the count values CNT1 and CNT2 match in the operation OXG is, for example, whether the count value difference value (DCNT) is within a predetermined allowable value, as in the first embodiment described above. This is done considering whether or not. Each operation may be a processing step.

  As described above, according to the second embodiment, the selection code for selecting the delay unit DU is changed in order, and the oscillator clock of each delay line is counted and compared for each selection code.

  When the determination result is an error for a certain selection code, the selection code causing the error is held, and the delay unit DU causing the error is skipped. When the selection code shows a value greater than the error selection code, the delay amount setting code in the delay line is increased to match the number of stages of the delay unit DU, and the delay fault location is relieved.

  Note that the delay clock from the delay line in which the delay fault portion has been remedied is also used during normal operation.

FIG. 16 is a block diagram showing an example of a semiconductor integrated circuit to which a delay circuit is applied.
As illustrated in FIG. 16, the semiconductor integrated circuit 500 includes a logic circuit 501, an MCU (Micro Controller Unit), a PLL (Phase Locked Loop) 503, and a memory I / F (interface) 504.

  In some cases, the semiconductor integrated circuit 500 includes a functional block 505 such as a DSP (Digital Signal Processor), a memory 506, an I / F 507 such as a USB (Universal Serial Bus), and an input / output circuit 508.

  The delay circuit (delay comparison circuit) of the above-described embodiment is applied to, for example, the DLL 541 in the memory I / F 504 of the semiconductor integrated circuit 500 that performs high-speed data transfer between the DDR (Double Data Rate) -SDRAM 600.

  Of course, the delay circuit of the above-described embodiment can be widely applied not only to the DLL 541 in the memory I / F 504 of the semiconductor integrated circuit 500 as shown in FIG. 16 but also to various semiconductor integrated circuits. Absent.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
Multiple delay lines,
A plurality of oscillator auxiliary circuits for making each delay line into an oscillator,
A plurality of counters for counting the oscillation outputs of the respective delay lines that have been made into oscillators to obtain respective count values;
And a comparator for comparing each count value with a reference count value.

(Appendix 2)
In the delay comparison circuit according to attachment 1,
Each of the oscillator auxiliary circuits includes an inverting logic circuit that inverts an output signal of the corresponding delay line and feeds it back to the input of the delay line to form a ring oscillator.

(Appendix 3)
In the delay comparison circuit according to attachment 2,
Each of the oscillator auxiliary circuits inputs a clock to each delay line and supplies the output signal to the system during normal operation, and each delay line receives the output signal of the delay line via the inversion logic circuit. And a selector for switching between a delay time comparison operation for ring oscillation.

(Appendix 4)
In the delay comparison circuit according to any one of appendices 1 to 3,
The comparison unit includes a difference calculation circuit that calculates a difference between each count value and a reference count value, a difference allowance determination circuit that determines whether the calculated difference is within a predetermined allowable value, A delay comparison circuit comprising:

(Appendix 5)
In the delay comparison circuit according to any one of appendices 1 to 4,
The delay comparison circuit, wherein the reference count value is an average value of the count values.

(Appendix 6)
In the delay comparison circuit according to any one of appendices 1 to 4,
The delay comparison circuit, wherein the reference count value is a center value of the count values.

(Appendix 7)
A delay comparison method for comparing delay times between a plurality of delay lines,
Each delay line is made into a ring oscillator,
Count the oscillation output of each ring oscillator to obtain the count value,
A delay comparison method comprising comparing each count value with a reference count value.

(Appendix 8)
In the delay comparison method according to appendix 7,
The delay comparison method, wherein the reference count value is an average value of the count values.

(Appendix 9)
In the delay comparison method according to appendix 7,
The delay comparison method, wherein the reference count value is a center value of the count values.

(Appendix 10)
It has a delay comparison circuit given in any 1 paragraph of appendices 1-6,
Each delay line includes a plurality of delay units and a plurality of selector units provided for the delay units,
Each selector unit includes: a first transfer gate that directly inputs a signal supplied to the corresponding delay unit; and a second transfer gate that skips the corresponding delay unit and supplies the second transfer gate to the next delay unit. A delay circuit comprising:

(Appendix 11)
In the delay circuit described in appendix 10,
An error holding circuit for storing an error selection code of an error delay unit in the delay line;
A code comparator for determining whether the output of the error holding circuit is equal to or lower than a selected code;
A delay circuit comprising: an adder that adds a number corresponding to the error delay unit subjected to the interlace processing to the selected code in accordance with an output of the code comparator.

(Appendix 12)
A semiconductor integrated circuit comprising the delay comparison circuit according to any one of appendices 1 to 6, or the delay circuit according to appendix 10 or 11.

1, 1 'first delay line 2, 2' second delay line 3, 3 'first counter 3a to 3c counter 4, 4' second counter 5, 5 ', 5a to 5c comparison unit 6, 7 selector 6' 1st oscillator auxiliary circuit 7 '2nd oscillator auxiliary circuit 8,9 inverter 11,21 delay part 12,22 selector 31,32 reference count value calculation circuit 51 difference calculation circuit 52 difference permissible judgment circuit 80 test control circuit 81 first code Comparison circuit 82 First adder 83 First delay setting circuit 84 First error holding circuit 85 First error DU relief decoder 91 Second code comparison circuit 92 Second adder 93 Second delay setting circuit 94 Second error holding circuit 95 Second error DU relief decoder 500 Semiconductor integrated circuit 501 Logic circuit 502 MCU
503 PLL
504 Memory I / F (interface)
541 DLL
505 Function block 506 Memory 507 I / F
508 I / O circuit 600 DDR-SDRAM

Claims (12)

Multiple delay lines,
A plurality of oscillator auxiliary circuits that respectively convert each delay line included in the plurality of delay lines into an oscillator;
A plurality of counters for counting the oscillation outputs of the respective delay lines that have been made into oscillators to obtain respective count values;
A calculation circuit for calculating a reference count value based on each count value obtained by the plurality of counters;
A delay comparison circuit comprising: a comparison unit that compares each count value with the reference count value. Multiple delay lines,
A plurality of oscillator auxiliary circuits that respectively convert each delay line included in the plurality of delay lines into an oscillator;
A plurality of counters for counting the oscillation outputs of the respective delay lines that have been made into oscillators to obtain respective count values;
A delay comparison circuit comprising: a comparison unit that compares each count value with a reference count value defined based on each count value obtained by the plurality of counters . Each of the oscillator auxiliary circuits included in the plurality of oscillator auxiliary circuits is an inverting logic circuit that inverts an output signal of each delay line corresponding to each of the oscillator auxiliary circuits and feeds back to the input of the delay line to form a ring oscillator The delay comparison circuit according to claim 1, further comprising: Before SL Each oscillator auxiliary circuit comprises a normal operation for supplying an output signal to the system of the delay the delay line to input clock to the line, of the delay line via the inverting logic circuits to the respective delay lines 4. The delay comparison circuit according to claim 3, further comprising a selector that switches between a delay time comparison operation in which an output signal is input and a ring oscillator is formed. Before Symbol comparison unit, said a difference calculation circuit for calculating a difference between the reference count value and the count values, the allowable difference determining circuit for determining whether the calculated issued difference is within the tolerance predetermined The delay comparison circuit according to claim 1, wherein the delay comparison circuit includes: 6. The delay comparison circuit according to claim 1, wherein the reference count value is any one of the count values. 7. 6. The delay comparison circuit according to claim 1, wherein the reference count value is an average value of the count values. The delay comparison circuit according to claim 1, wherein the reference count value is a center value of the count values. A delay comparison method for comparing delay times between a plurality of delay lines,
Each delay line included in the plurality of delay lines is made into a ring oscillator,
Count the oscillation output of each delay line that has been made into the ring oscillator to obtain the count value,
A reference count value is calculated based on each count value obtained by counting the oscillation output,
Delay comparing method characterized by comparing the reference count value and the count values. A delay comparison circuit according to any one of claims 1 to 8 ,
Each of the delay lines includes a plurality of delay units, and a plurality of selector units provided for each delay unit included in the plurality of delay units ,
Each selector unit included in the plurality of selector units jumps over the first transfer gate that inputs the signal supplied to the delay unit corresponding to each selector unit as it is, and the delay unit corresponding to each selector unit. And a second transfer gate for supplying to the delay unit of the next stage. An error storage circuit for storing the error selection code error delay units before SL delay line,
A code comparator for determining whether an output of the error holding circuit is equal to or lower than a selected code;
11. The delay according to claim 10 , further comprising: an adder that adds a number corresponding to the error delay unit subjected to the interlace processing to the selected code in accordance with an output of the code comparator. circuit. Delay comparator circuit according to any one of claims 1 to 8, or a semiconductor integrated circuit and having a delay circuit according to claim 10 or claim 11.

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