JP3885119B2 - フィールドプログラマブルプロセッサデバイス - Google Patents

フィールドプログラマブルプロセッサデバイス Download PDF

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Publication number
JP3885119B2
JP3885119B2 JP53175598A JP53175598A JP3885119B2 JP 3885119 B2 JP3885119 B2 JP 3885119B2 JP 53175598 A JP53175598 A JP 53175598A JP 53175598 A JP53175598 A JP 53175598A JP 3885119 B2 JP3885119 B2 JP 3885119B2
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Japan
Prior art keywords
memory cells
switch
field programmable
programmable device
memory cell
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Expired - Fee Related
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JP53175598A
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English (en)
Japanese (ja)
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JP2001509336A5 (enExample
JP2001509336A (ja
Inventor
マーシャル，アラン
スタンスフィールド，アンソニー
ヴィルミン，ジャン
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Elixent Ltd
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Elixent Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Multi Processors (AREA)
JP53175598A 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサデバイス Expired - Fee Related JP3885119B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97300562.2 1997-01-29
EP97300562A EP0858167A1 (en) 1997-01-29 1997-01-29 Field programmable processor device
PCT/GB1998/000248 WO1998033276A1 (en) 1997-01-29 1998-01-28 Field programmable processor

Publications (3)

Publication Number Publication Date
JP2001509336A JP2001509336A (ja) 2001-07-10
JP2001509336A5 JP2001509336A5 (enExample) 2006-01-05
JP3885119B2 true JP3885119B2 (ja) 2007-02-21

Family

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Family Applications (1)

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JP53175598A Expired - Fee Related JP3885119B2 (ja) 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサデバイス

Country Status (5)

Country Link
US (2) US6262908B1 (enExample)
EP (2) EP0858167A1 (enExample)
JP (1) JP3885119B2 (enExample)
DE (1) DE69822796T2 (enExample)
WO (1) WO1998033276A1 (enExample)

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DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE59710317D1 (de) 1996-12-27 2003-07-24 Pact Inf Tech Gmbh VERFAHREN ZUM SELBSTÄNDIGEN DYNAMISCHEN UMLADEN VON DATENFLUSSPROZESSOREN (DFPs) SOWIE BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN (FPGAs, DPGAs, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
EP1228440B1 (de) 1999-06-10 2017-04-05 PACT XPP Technologies AG Sequenz-partitionierung auf zellstrukturen
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
DE50115584D1 (de) 2000-06-13 2010-09-16 Krass Maren Pipeline ct-protokolle und -kommunikation
US7383424B1 (en) 2000-06-15 2008-06-03 Hewlett-Packard Development Company, L.P. Computer architecture containing processor and decoupled coprocessor
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7581076B2 (en) * 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
EP2224330B1 (de) * 2001-06-20 2012-05-09 Krass, Maren Verfahren und gerät zum partitionieren von grossen rechnerprogrammen
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
EP1514193B1 (de) 2002-02-18 2008-07-23 PACT XPP Technologies AG Bussysteme und rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US6844757B2 (en) 2002-06-28 2005-01-18 Lattice Semiconductor Corp. Converting bits to vectors in a programmable logic device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
US6980390B2 (en) * 2003-02-05 2005-12-27 Quantum Corporation Magnetic media with embedded optical servo tracks
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
US7219325B1 (en) * 2003-11-21 2007-05-15 Xilinx, Inc. Exploiting unused configuration memory cells
US7461236B1 (en) * 2005-03-25 2008-12-02 Tilera Corporation Transferring data in a parallel processing environment
WO2007082730A1 (de) 2006-01-18 2007-07-26 Pact Xpp Technologies Ag Hardwaredefinitionsverfahren
US7928764B2 (en) * 2006-08-31 2011-04-19 Agate Logic (Beijing), Inc. Programmable interconnect network for logic array
US7994818B2 (en) * 2007-06-20 2011-08-09 Agate Logic (Beijing), Inc. Programmable interconnect network for logic array
JP5336398B2 (ja) * 2010-02-01 2013-11-06 ルネサスエレクトロニクス株式会社 半導体集積回路、半導体集積回路の構成変更方法
US9557154B2 (en) 2010-05-25 2017-01-31 The General Hospital Corporation Systems, devices, methods, apparatus and computer-accessible media for providing optical imaging of structures and compositions

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US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5204556A (en) 1991-05-06 1993-04-20 Lattice Semiconductor Corporation Programmable interconnect structure for logic blocks
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US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
US5498975A (en) * 1992-11-19 1996-03-12 Altera Corporation Implementation of redundancy on a programmable logic device
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US5453706A (en) * 1994-04-01 1995-09-26 Xilinx, Inc. Field programmable gate array providing contention free configuration and reconfiguration
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US5426379A (en) * 1994-07-29 1995-06-20 Xilinx, Inc. Field programmable gate array with built-in bitstream data expansion
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US5583450A (en) * 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
GB9611994D0 (en) 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor

Also Published As

Publication number Publication date
EP0956645A1 (en) 1999-11-17
US6262908B1 (en) 2001-07-17
DE69822796T2 (de) 2005-03-10
WO1998033276A1 (en) 1998-07-30
JP2001509336A (ja) 2001-07-10
US20010038298A1 (en) 2001-11-08
EP0956645B1 (en) 2004-03-31
DE69822796D1 (de) 2004-05-06
EP0858167A1 (en) 1998-08-12

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