JP3883598B2 - モジュール式プローブ構造体を備えた大形集積回路およびその試験方法 - Google Patents

モジュール式プローブ構造体を備えた大形集積回路およびその試験方法 Download PDF

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Publication number
JP3883598B2
JP3883598B2 JP31318295A JP31318295A JP3883598B2 JP 3883598 B2 JP3883598 B2 JP 3883598B2 JP 31318295 A JP31318295 A JP 31318295A JP 31318295 A JP31318295 A JP 31318295A JP 3883598 B2 JP3883598 B2 JP 3883598B2
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Japan
Prior art keywords
circuit
module
test
modules
test pad
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Expired - Fee Related
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JP31318295A
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English (en)
Japanese (ja)
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JPH08222612A (ja
Inventor
エル．ブーバ ロヒット
トラン バオ
エル．コナー ジェームズ
オーバーラウアー マイクル
エス．ポールセン トレイシー
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テキサス インスツルメンツ インコーポレイテツド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
    • G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
    • G02B26/0816—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements
    • G02B26/0833—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
    • G02B26/0841—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD the reflecting element being moved or deformed by electrostatic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
JP31318295A 1994-11-30 1995-11-30 モジュール式プローブ構造体を備えた大形集積回路およびその試験方法 Expired - Fee Related JP3883598B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US347021 1994-11-30
US08/347,021 US5648730A (en) 1994-11-30 1994-11-30 Large integrated circuit with modular probe structures

Publications (2)

Publication Number Publication Date
JPH08222612A JPH08222612A (ja) 1996-08-30
JP3883598B2 true JP3883598B2 (ja) 2007-02-21

Family

ID=23362000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31318295A Expired - Fee Related JP3883598B2 (ja) 1994-11-30 1995-11-30 モジュール式プローブ構造体を備えた大形集積回路およびその試験方法

Country Status (6)

Country Link
US (2) US5648730A (cg-RX-API-DMAC7.html)
EP (1) EP0715178B1 (cg-RX-API-DMAC7.html)
JP (1) JP3883598B2 (cg-RX-API-DMAC7.html)
KR (1) KR960019643A (cg-RX-API-DMAC7.html)
DE (1) DE69531657T2 (cg-RX-API-DMAC7.html)
TW (1) TW320756B (cg-RX-API-DMAC7.html)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619461A (en) 1995-07-28 1997-04-08 Micron Quantum Devices, Inc. Memory system having internal state monitoring circuit
US5965902A (en) 1995-09-19 1999-10-12 Micron Technology Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device
US5657284A (en) 1995-09-19 1997-08-12 Micron Technology, Inc. Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices
US5977763A (en) * 1996-02-27 1999-11-02 Micron Technology, Inc. Circuit and method for measuring and forcing an internal voltage of an integrated circuit
US6229296B1 (en) 1996-02-27 2001-05-08 Micron Technology, Inc. Circuit and method for measuring and forcing an internal voltage of an integrated circuit
US6946863B1 (en) 1998-02-27 2005-09-20 Micron Technology, Inc. Circuit and method for measuring and forcing an internal voltage of an integrated circuit
JPH11354594A (ja) * 1998-06-08 1999-12-24 Mitsubishi Electric Corp 半導体装置
US6163867A (en) * 1998-08-28 2000-12-19 Hewlett-Packard Company Input-output pad testing using bi-directional pads
EP1227502A1 (en) * 2001-01-25 2002-07-31 Alcatel Connection pad arrangements for electronic circuit comprising both functional logic and flash-EEPROM
US7026251B2 (en) * 2001-12-12 2006-04-11 Texas Instruments Incorporated Method of optimized stitching for digital micro-mirror device
US6831772B2 (en) * 2002-02-01 2004-12-14 Analog Devices, Inc. Optical mirror module
US6967348B2 (en) * 2002-06-20 2005-11-22 Micron Technology, Inc. Signal sharing circuit with microelectric die isolation features
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
DE102004059506B3 (de) * 2004-12-10 2006-08-17 X-Fab Semiconductor Foundries Ag Anordnung zum Test von eingebetteten Schaltungen mit Hilfe einer separaten Versorgungsspannung
DE102004059505B4 (de) 2004-12-10 2014-06-18 X-Fab Semiconductor Foundries Ag Anordnung zum Test von eingebetteten Schaltungen mit Hilfe von Testinseln

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4244048A (en) * 1978-12-29 1981-01-06 International Business Machines Corporation Chip and wafer configuration and testing method for large-scale-integrated circuits
JPS58115372A (ja) * 1981-12-29 1983-07-09 Fujitsu Ltd 半導体装置試験回路
JPS60115099A (ja) * 1983-11-25 1985-06-21 Fujitsu Ltd 半導体記憶装置
US5061049A (en) * 1984-08-31 1991-10-29 Texas Instruments Incorporated Spatial light modulator and method
US4687989A (en) * 1984-11-01 1987-08-18 Thomson Components-Mostek Corp. CMOS powerless rom code mask option select
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
US4710931A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
US4701921A (en) * 1985-10-23 1987-10-20 Texas Instruments Incorporated Modularized scan path for serially tested logic circuit
US5214655A (en) * 1986-09-26 1993-05-25 General Electric Company Integrated circuit packaging configuration for rapid customized design and unique test capability
US4970454A (en) * 1986-12-09 1990-11-13 Texas Instruments Incorporated Packaged semiconductor device with test circuits for determining fabrication parameters
US5008727A (en) * 1988-01-22 1991-04-16 Matsushita Electric Industrial Co., Ltd. Standard cell having test pad for probing and semiconductor integrated circuit device containing the standard cells
EP0332953B1 (en) 1988-03-16 1993-09-15 Texas Instruments Incorporated Spatial light modulator and method
US4956602A (en) * 1989-02-14 1990-09-11 Amber Engineering, Inc. Wafer scale testing of redundant integrated circuit dies
US5079544A (en) * 1989-02-27 1992-01-07 Texas Instruments Incorporated Standard independent digitized video system
US5051996A (en) * 1989-03-27 1991-09-24 The United States Of America As Represented By The United States Department Of Energy Built-in-test by signature inspection (bitsi)
US5107208A (en) * 1989-12-19 1992-04-21 North American Philips Corporation System for partitioning and testing submodule circuits of an integrated circuit
US5105369A (en) 1989-12-21 1992-04-14 Texas Instruments Incorporated Printing system exposure module alignment method and apparatus of manufacture
US5187712A (en) * 1990-02-26 1993-02-16 At&T Bell Laboratories Pseudo-exhaustive self-test technique
JP3381929B2 (ja) * 1990-12-27 2003-03-04 株式会社東芝 半導体装置
JP3179595B2 (ja) * 1992-11-12 2001-06-25 株式会社日立製作所 半導体集積回路装置およびその製造方法
US5705299A (en) 1992-12-16 1998-01-06 Texas Instruments Incorporated Large die photolithography

Also Published As

Publication number Publication date
US5648730A (en) 1997-07-15
EP0715178B1 (en) 2003-09-03
US5825194A (en) 1998-10-20
JPH08222612A (ja) 1996-08-30
TW320756B (cg-RX-API-DMAC7.html) 1997-11-21
EP0715178A2 (en) 1996-06-05
DE69531657T2 (de) 2004-07-29
DE69531657D1 (de) 2003-10-09
KR960019643A (ko) 1996-06-17
EP0715178A3 (en) 1998-01-28

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