JP3863951B2 - Bit line forming method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bit line forming method of a semiconductor device, and more particularly to a bit line forming method using a conductive layer as a planarizing layer.
[0002]
[Prior art]
The bit line is preferably formed to have a low resistance so that high-speed data access is possible. Therefore, the bit line is generally formed from a silicide structure.
When the lower layer of the bit line is not flattened, the outline of the resultant product formed in the previous stage appears on the bit line as it is. Accordingly, a plurality of recessed portions may be formed in the bit line according to the morphology of the resultant product.
[0003]
The conductive layer used as the bit line is formed only in a necessary region of the base film and must be removed in other regions. However, if there are a large number of recessed portions in the bit line, it is difficult to remove the conductive layer formed in this portion. Furthermore, when the bit line has a laminated structure, it is even more difficult to remove the conductive layer in the recessed portion. This is because silicide enters the polycrystalline silicon in the recessed portion and it is very difficult to remove it. In addition, if there is a concave portion, the photographic etching process is supported by the reflection effect of the concave surface.
[0004]
Therefore, in order to prevent this, a BPSG (Boro-Phospho-Silicate Glass) film is used in the planarization process that is usually performed before the doped polycrystalline silicon layer and the tungsten silicide layer are formed. This is because the fluidity increases when the slag is added, and the recessed portion is easily flattened. By doing so, the depth of the recessed portion becomes very shallow, and it becomes easy to pattern the silicide layer and the polycrystalline silicon layer.
[0005]
However, when heat is applied, the punch-through characteristics of the transistor are degraded, making it difficult to form a short channel.
As semiconductor devices are highly integrated and miniaturized, a method for planarization without applying heat has become necessary. As a non-thermal treatment method for planarization, there is an etch-back method in which a BPSG or USG (Undoped Silica Glass) film quality is formed thick, and then etching is performed while leaving a necessary amount.
[0006]
A conventional method for forming a bit line of a semiconductor device will be described in detail with reference to FIGS.
First, referring to FIG. 1, a gate electrode 12 is formed on a semiconductor substrate 10. Next, conductive impurities are ion-implanted over the entire surface of the semiconductor substrate 10 using the gate electrode 12 as a mask to form source / drain regions (S, D) in the semiconductor substrate 10 to form transistors. Next, an undoped oxide film 13 is formed on the entire surface of the semiconductor substrate 10 by chemical vapor deposition (hereinafter referred to as CVD). Next, a planarization layer 14 is formed on the entire surface of the resultant product. As the planarizing layer 14, a BPSG film is used.
[0007]
The oxide film 13 must be formed before the planarization layer 14 is formed because if the BPSG film is in direct contact with the semiconductor substrate, the characteristics of the transistor are adversely affected.
Immediately after the formation of the BPSG film, the entire surface of the BPSG film is not yet flattened, and therefore includes a recessed portion 16. At this time, when heat is applied to the resultant product, the BPSG film increases in fluidity and fills the recessed portion 16, and the entire surface of the resultant product is flattened. That is, as shown in FIG. 2, the depth of the recessed portion 16 becomes very shallow to the extent that it can be ignored.
[0008]
Referring to FIG. 3, a contact hole for forming a contact between the semiconductor substrate and the bit line is formed on the planarized BPSG film, and then the polycrystalline structure is formed on the entire surface of the resultant product while filling the contact hole. A bit line is formed by forming a silicon layer 18 and sequentially forming and patterning a tungsten silicide layer 20 on the entire surface thereof.
[0009]
As described above, the bit line forming method of the semiconductor device according to the prior art applies heat to the planarization layer in order to planarize the planarization layer. Therefore, when the channel length of the gate of the transistor formed on the semiconductor substrate is shortened, the punch-through characteristic of the transistor is deteriorated.
Although not mentioned in the above step, the BPSG film can be flattened by etching back instead of heating the flattening layer. However, in this case, there is an advantage that the transistor does not receive heat, but it is difficult to adjust the deposition and etch back uniformity. In addition, since it is impossible to determine the end point in the etch back process, time etching must be performed for a certain amount of etch back. However, in the actual process, the etching rate slightly changes according to the state of the equipment that changes every moment, and there is an inconvenience that this must be continuously checked and corrected.
[0010]
Excessive etch back also causes a short circuit between the polycrystalline silicon layer of the bit line and the subsequent layer, leading to defects in the device. On the other hand, when the etch back is insufficient, the etch back object is thick and it is difficult to form a contact. Thus, defects can be generated in the device. Thus, the etch back of the interlayer dielectric material also has a regulatory problem.
[0011]
[Problems to be solved by the invention]
The present invention has been devised to solve the above-described conventional problems, and has an object to provide a bit line forming method for a semiconductor device using a polycrystalline silicon layer as a planarizing layer.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a bit line forming method of a semiconductor device according to a first embodiment of the present invention includes a step of forming a transistor on a semiconductor substrate, and a first insulating film on the entire surface of the semiconductor substrate on which the transistor is formed. Forming a first conductive layer on the entire surface of the first insulating film, planarizing the entire surface of the first conductive layer until the surface of the first insulating film is exposed, and Forming a contact hole in the drain region of the transistor; forming a second conductive layer filling the contact hole over the entire surface of the first conductive layer; and forming a third conductive layer over the entire surface of the second conductive layer. Forming a bit line by patterning the third, second and first conductive layers.
[0013]
In order to achieve the above object, a bit line forming method of a semiconductor device according to a second embodiment of the present invention includes a step of forming a transistor on a semiconductor substrate, and a first insulating film on the entire surface of the resultant structure on which the transistor is formed. Forming a first conductive layer on the entire surface of the first insulating film, and planarizing the entire surface of the first conductive layer within a range where the surface of the first insulating film is not exposed. Removing a portion formed in the drain region of the transistor to pattern the first conductive layer; and etching the first insulating film formed in the drain region using the patterned first conductive layer as a mask. Forming a contact hole, forming a second conductive layer while filling the entire surface of the resultant product with a contact hole, and a third conductive layer on the entire surface of the second conductive layer. Comprising forming, and forming a bit line to the third, patterning the second and first conductive layers.
[0014]
The first insulating film is formed of a high temperature thermal oxide film (hereinafter referred to as HTO). The first and second conductive layers are formed of a polycrystalline silicon layer. The third conductive layer is formed of a tungsten silicide (WSi _x ) layer.
A polymer can also be used to make the diameter of the contact hole smaller. In addition, the diameter of the contact hole can be reduced by applying heat to the photosensitive film pattern to expand the edge of the pattern. Furthermore, the diameter of the contact hole can be made smaller by forming a spacer on the side wall of the photosensitive film pattern. In the first embodiment, the first conductive layer is preferably etched back until the surface of the first insulating film is exposed.
[0015]
According to the present invention, the tungsten silicider layer formed on the first conductive layer having a planarized surface is patterned, so that the photographic and etching processes are easily performed. In addition, the aspect ratio can be improved when the contact is formed.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
Referring to FIG. 4, the gate electrode 32 is formed on the semiconductor substrate 30. Next, conductive impurities are ion-implanted into the entire surface of the semiconductor substrate 30 using the gate electrode 32 as a mask. As a result, source and drain regions (S, D) are formed on the left and right semiconductor substrate 30 of the gate electrode 32, thereby forming a transistor. Subsequently, a first insulating film 34 is formed on the entire surface of the semiconductor substrate 30 on which the transistor is formed. The first insulating film 34 is formed of an HTO film.
[0017]
Next, as shown in FIG. 5, a first conductive layer 36 is formed thick on the entire surface of the first insulating film 34. The first conductive layer 36 is formed from a doped polysilicon layer.
FIG. 6 shows a step of etching back the entire surface of the first conductive layer 36. Here, the end point is the surface of the first insulating film 34. Accordingly, when the etch back is completed, the doped polysilicon layer forming the first conductive layer 36 is completely removed from the upper portion of the gate electrode 32. As a result, the surface of the first insulating film 34 is exposed, and a first conductive layer pattern 36a having the same flatness as the gate electrode 32 is formed therearound.
[0018]
Next, after applying a photosensitive film on the entire surface of the resultant product,
A photosensitive film pattern 37 is formed to expose the first conductive layer pattern 36a formed on the drain region between the gate electrodes 32 of the transistor. The photosensitive film pattern 37 is formed of a photoresist film. As shown in FIG. 7, the exposed portion of the first conductive layer pattern 36a is removed using the photosensitive film pattern 37 as an etching mask, and the first insulating film 34 formed thereunder is also removed. As a result, a contact hole 38 exposing the surface of the drain region (D) is formed in the semiconductor substrate 30. Next, the photosensitive film pattern 37 is removed.
[0019]
In order to further reduce the diameter of the contact hole 38, after forming the photosensitive film pattern 37, the edge of the photosensitive film pattern 37 may flow slightly by applying heat, and then etched. Alternatively, etching may be performed after a spacer (not shown) is formed on the sidewall of the photosensitive film pattern 37. Further, instead of using the photosensitive film pattern 37, a polymer can be used.
[0020]
In addition, since the interlayer insulating film is formed as a single layer and the contact hole is not deep, the aspect ratio of the contact hole, that is, the ratio of the depth to the diameter of the contact hole is good.
FIG. 8 shows the step of forming the second conductive layer 40 and the third conductive layer 42. Referring to this, a second conductive layer 40 for filling the contact hole 38 is formed on the entire surface of the resultant product. Subsequently, a third conductive layer 42 is formed on the entire surface of the second conductive layer 40 with a uniform thickness. The second conductive layer 40 is formed of a doped polysilicon layer similar to the first conductive layer 36a. The third conductive layer 42 is formed of a tungsten silicide layer.
[0021]
A photoresist pattern (not shown) that defines a region including the drain region (D) is formed on the third conductive layer 42. The third conductive layer, the second conductive layer, and the first conductive layer patterns 42, 40, and 36a are sequentially anisotropically etched using the photoresist pattern as an etching mask. Thereafter, when the photosensitive film pattern is removed, a bit line including the third conductive layer pattern 42a and the second conductive layer pattern 40a is formed as shown in FIG.
[0022]
As described above, the first embodiment of the present invention will be described in detail. The feature of the first embodiment is that the second and third conductive layers 40 and 42 are formed on the first conductive layer 36 flattened by etch back and then patterned. Therefore, the patterning process of this layer is further facilitated.
10 to 16 show a bit line forming method of a semiconductor device according to a second embodiment of the present invention step by step. As shown in FIGS. 10 and 11, the steps up to the step of forming the first conductive layer 56 are performed by the same process as in the first embodiment of the present invention. That is, after the gate electrode 52 is formed on the semiconductor substrate 50 and the source and drain regions (S, D) are formed, the first insulating film 54 and the first conductive layer 56 are sequentially formed on the entire surface. Then, after the first conductive layer 56 is formed, the first conductive layer 56 is removed from the first insulating film 54 within a range where the surface of the first insulating film 54 is not exposed, as shown in FIG. When etching back from the surface to a certain height, the thin first conductive layer pattern 56a is formed.
[0023]
FIG. 13 shows a step of removing the first conductive layer pattern 56 a formed in the drain region between the gate electrodes 52. Specifically, a photoresist film (not shown) is applied to the entire surface of the resultant product, and then patterned to expose the first conductive layer pattern 56a formed in the drain region between the gate electrodes 52. Form. Next, using the photosensitive film pattern 57 as an etching mask, the exposed portion of the first conductive layer pattern 56a is etched until the first insulating film 54 is exposed. As a result, a first conductive layer pattern 56b exposing the drain region (D) of the first insulating film 54 is formed.
[0024]
FIG. 14 shows the step of forming the contact hole 58. Specifically, after removing the photosensitive film pattern 57 from FIG. 13, the exposed portion of the first insulating film 54 is removed using the first conductive layer pattern 56b as an etching prevention mask. As a result, a contact hole 58 is formed on the drain region (D) of the semiconductor substrate 50.
[0025]
Next, as shown in FIG. 15, a second conductive layer 60 filling the contact hole 58 is formed on the entire surface of the resultant product, and a third conductive layer 62 is formed on the entire surface of the second conductive layer 60. . The second conductive layer 60 and the third conductive layer 62 are formed under the same conditions using the same material as in the first embodiment.
A photosensitive film pattern (not shown) that defines a region of the third conductive layer 62 including the contact hole 58 is formed on the third conductive layer 62. When the third conductive layer, the second conductive layer, and the first conductive layer patterns 62, 60, and 56b are anisotropically etched using the photoresist pattern as an etching mask, the first conductive layer is formed as shown in FIG. A bit line including the pattern 56c and the second and third conductive layer patterns 60a and 62a is formed.
[0026]
The bit line forming method of the semiconductor device according to the second embodiment of the present invention differs from the first embodiment in which the contact hole is formed at one time using the photosensitive film pattern as a mask in forming the contact hole as described above. First, the first conductive layer formed in a region where a contact hole is to be formed is removed using a photosensitive film pattern, and then the first insulating film pattern is removed using the first conductive layer pattern as an etching mask. It is.
[0027]
【The invention's effect】
In the present invention, good flatness can be obtained by using a conductive layer as a planarizing layer, and a tungsten silicide layer is formed thereon and subjected to a photographic and etching process. Therefore, the bit line patterning is simplified. Further, since heat is not received during the planarization process, the punch-through characteristics of the transistor can be improved. Since the interlayer oxide film is a single layer, it has a good aspect ratio when forming a contact.
[0028]
The present invention is not limited to the above-described embodiments, and it is obvious that many modifications can be made by those having ordinary knowledge in the art within the technical idea of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a conventional bit line forming method of a semiconductor device according to a conventional technique.
FIG. 2 is a diagram illustrating a conventional bit line formation method for a semiconductor device according to a conventional technique.
FIG. 3 is a diagram illustrating a conventional bit line formation method for a semiconductor device according to a conventional technique.
FIG. 4 is a diagram illustrating a bit line forming method of a semiconductor device according to a first embodiment of the present invention by steps;
FIG. 5 is a diagram illustrating a method of forming a bit line of a semiconductor device according to a first embodiment of the present invention, step by step.
FIG. 6 is a diagram illustrating a bit line forming method of a semiconductor device according to a first embodiment of the present invention in stages.
FIG. 7 is a diagram illustrating a bit line forming method of a semiconductor device according to a first embodiment of the present invention in stages.
FIG. 8 is a diagram illustrating a method of forming a bit line of a semiconductor device according to a first embodiment of the present invention, step by step.
FIG. 9 is a diagram illustrating a method of forming a bit line of a semiconductor device according to a first embodiment of the present invention step by step.
FIG. 10 is a diagram illustrating a bit line forming method of a semiconductor device according to a second embodiment of the present invention in stages.
FIG. 11 is a diagram illustrating a bit line forming method of a semiconductor device according to a second embodiment of the present invention in stages.
FIG. 12 is a diagram illustrating a bit line forming method of a semiconductor device according to a second embodiment of the present invention in stages.
FIG. 13 is a diagram illustrating a bit line forming method of a semiconductor device according to a second embodiment of the present invention in stages.
FIG. 14 is a view showing a bit line forming method of a semiconductor device according to a second embodiment of the present invention in stages.
FIG. 15 is a view illustrating a bit line forming method of a semiconductor device according to a second embodiment of the present invention in stages.
FIG. 16 is a view illustrating a bit line forming method of a semiconductor device according to a second embodiment of the present invention in stages.
[Explanation of symbols]
30 Semiconductor substrate 32 Gate electrode 34 First insulating film 36 First conductive layer 36a First conductive layer pattern 37 Photosensitive film pattern 38 Contact hole 40 Second conductive layer 40a Second conductive layer pattern 42 Third conductive layer 42a Third conductive layer Pattern 50 semiconductor substrate 52 gate electrode 54 first insulating film 56 first conductive layer 56a first conductive layer pattern 56b first conductive layer pattern 56c first conductive layer pattern 57 photosensitive film pattern 58 contact hole 60 second conductive layer 60a second Conductive layer 62 Third conductive layer 62a Third conductive layer

Claims (7)

(a) forming a transistor on a semiconductor substrate;
(b) forming a first insulating film on the entire surface of the semiconductor substrate on which the transistor is formed;
(c) forming a first conductive layer on the entire surface of the first insulating film;
(d) etching the first conductive layer to a predetermined depth to planarize the surface from the first conductive layer to the first insulating film or the surface of the first conductive layer ;
(e) forming a contact hole by sequentially removing the first conductive layer and the first insulating film on the drain region of the transistor;
(f) forming the resultant product second conductive layer while making the entire surface filled with the contact hole,
(g) forming a third conductive layer on the entire surface of the second conductive layer;
(h) patterning the third, second and first conductive layers to form a bit line connected to the drain region . The method of claim 1, wherein in the step (d), the planarization is performed until the first insulating film is exposed. The method of claim 1, wherein in the step (d), the planarization is performed within a range where the surface of the first insulating film is not exposed. The step (e) includes forming a photosensitive film pattern on the first conductive layer;
Bit lines forming a semiconductor device according to claim 1, characterized in that it comprises a step of etching the first conductive layer and said first insulating film formed on the drain region using the photoresist pattern Method. The step (e) includes forming a photosensitive film pattern on the first conductive layer;
Etching the first conductive layer formed on the drain region using the photosensitive film pattern and then removing the photosensitive film pattern;
The method of claim 1, further comprising: removing a first insulating film formed on the drain region using the first conductive layer as a mask. 5. The method of forming a bit line in a semiconductor device according to claim 4, wherein the diameter of the contact hole is further reduced by applying heat to the photosensitive film pattern to expand the edge of the pattern. 5. The method according to claim 4, wherein the diameter of the contact hole is further reduced by forming a spacer on the sidewall of the photosensitive film pattern.

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