JP3859066B2 - Semiconductor device and semiconductor circuit using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using an FET element, particularly a HEMT element, and a semiconductor circuit using the same.
[0002]
[Prior art]
First, the influence of the frequency dispersion of the HEMT element on the circuit and the frequency dispersion suppression method of the HEMT element proposed so far will be described. It is very important for circuit application that transconductance and drain conductance, which are main parameters of the FET element, can maintain stable values regardless of the signal frequency. When frequency dispersion is seen in the above parameters, that is, the value fluctuates depending on the signal frequency, various problems occur depending on the circuit type using the HEMT element. Further, the frequency dispersion characteristic also changes for each DC bias point of the HEMT element. This means that waveform distortion due to frequency dispersion characteristics occurs even when the HEMT element is operated with a large signal by CW.
[0003]
By the way, when a HEMT element is used in a high-speed digital circuit, (1) an increase in BER (bit error rate) due to cross-point movement depending on the signal mark rate (a high-level temporal ratio in the digital signal), (2 ) Waveform distortion (gate lag, drain lag) seen at the rise and fall of the signal. Further, when a HEMT element is used in a general analog circuit, there are problems in the form of (3) gain fluctuation, (4) increase in higher-order distortion, and the like. There are two causes of the frequency dispersion of the HEMT element, that is, the influence of trap order inside the device and the influence of holes generated by impact ionization in the drain region.
[0004]
As a first conventional example of the coping method, there is optimization of the channel layer composition (Eye Triple E Transaction of Electron Device, Vol. 38, No. 4, April, 1991, pages 862-870). When a trap exists in the vicinity of the channel region of the HEMT, frequency dispersion depending on the charge / discharge time constant of the trap is seen in the transconductance and the drain conductance. It has been reported that the trap density existing in the InGaAs channel layer used in InP-HEMT is minimized when the In composition is 60%, and at this time, frequency dispersion is most suppressed.
[0005]
As a second conventional example of the coping method, there is optimization of the recess area width (I Triple E Transaction of Electron Device, Vol. 45, No. 12, 1998, December, pages 2390-2399). When the voltage between the gate and the drain of the HEMT element increases, a high electric field domain is generated on the drain side of the gate and electrons are accelerated. As a result, excessive holes are generated inside the channel due to impact ionization. When this hole is not rapidly recombined and accumulated in the source region of the HEMT element, the pseudo-Fermi level of the hole shifts toward the valence band in the source-side recess region (which refers to the semiconductor portion in contact with the gate in the source region), Excess holes begin to move to the semiconductor surface in the recess region and accumulate on the semiconductor surface in the recess region. As a result, the channel potential increases and the electron concentration in the recess region increases. This means that the resistance of the recess region is lowered and the drain current is increased, which causes variations in transconductance and drain conductance. Since the movement of excess holes from the channel to the recess surface is accompanied by a time constant, the above-described fluctuations in transconductance and drain conductance have frequency dispersion.
[0006]
To prevent this, shorten the recess area and make it less susceptible to hole movement, and increase the doping amount to keep the electron concentration in the recess area high from the beginning to make the resistance change in the recess relatively small. Etc. have been shown to be effective.
[0007]
As a third conventional example of the coping method, there is a compensation circuit (Japanese Patent Laid-Open No. 5-114825). If only the small signal region is considered, the frequency dispersion of the drain conductance is always constant if the device structure and the DC bias condition are determined. Therefore, the influence of frequency dispersion can be compensated by providing an additional circuit having a frequency dispersion opposite to the frequency dispersion of the drain conductance of the HEMT element between the drain and source of the HEMT element. As the additional circuit, a circuit using a passive element including a resistor and an inductor is used. The effect of the transconductance can be reduced by providing a compensation circuit for each HEMT element.
[0008]
[Problems to be solved by the invention]
However, the conventional HEMT device frequency dispersion suppressing methods described above have the following problems. First, the channel composition optimization method is effective for InP-HEMT devices having a long channel gate with a gate length of about 0.7 μm, but a high gate length of 0.1 μm class used in high-speed optical communication or high-frequency amplifier circuits. In an InP-HEMT device, the effect of holes due to impact ionization is dominant, and a sufficient effect cannot be expected in a device actually used.
[0009]
In the method of optimizing the recess area width, even if the recess area is shortened to a position close to the limit of miniaturization of the exposure technique used for pattern formation, the influence of frequency dispersion is still seen. Even if the recess region width can be further reduced by improving the exposure technique, a certain recess region width is required to secure the reverse DC breakdown voltage between the gate and the source. The trade-off cannot be resolved. In addition, the doping concentration is set to a value close to the upper limit in a normal HEMT device, and it is technically difficult to significantly increase the electron concentration in the recess region compared to the conventional HEMT device.
[0010]
On the other hand, the method using the compensation circuit can be applied only when the signal is small and the signal frequency changes slowly. For example, in a circuit used for optical communication, an input signal is a large signal, and a broadband signal having various frequency components is input. In this case, it is practically impossible to remove the frequency dispersion with a simple compensation circuit. Further, even in a high-frequency amplifier, an input signal is often a large signal and accompanied by fluctuations in input amplitude, and there is a limit to applying a method using a compensation circuit.
[0011]
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device from which frequency dispersion of transconductance and drain conductance generated in a high-performance HEMT element having a gate length of 0.1 μm is removed, and to use the same. An object of the present invention is to provide a semiconductor circuit.
[0012]
[Means for Solving the Problems]
The invention according to claim 1 is a semiconductor device including first and second FETs, wherein the source electrode of the first FET and the drain electrode of the second FET are a common terminal, The channel layers of the first and second FETs are composed of the same layer, the common terminal is grounded, and the voltage applied to the source electrode of the second FET is the voltage of the common terminal. The semiconductor device is characterized by being set lower than the above.
[0013]
The invention according to claim 2 is the invention according to claim 1, wherein the voltage applied to the gate electrode of the second FET is equal to the voltage applied to the source electrode of the second FET and the second FET. The semiconductor device is characterized in that it is set lower than the sum of the threshold voltages.
[0014]
The invention according to claim 3 is the semiconductor device according to claim 1 or 2, wherein the DC voltage applied to the gate electrode of the first FET is set to a constant value.
[0015]
The invention according to claim 4 is a semiconductor circuit using the semiconductor device according to claim 1 or 2, wherein individual impedance matching circuits are connected to the gate electrode and the drain electrode of the first FET, respectively. It was set as the semiconductor circuit characterized by having.
[0016]
The invention according to claim 5 is a semiconductor circuit using the semiconductor device according to claim 2, wherein an anode electrode is connected to the second source electrode, and a cathode electrode is connected to the second gate electrode. A semiconductor circuit comprising a diode, wherein a voltage applied to a cathode electrode of the diode is set lower than a voltage of a source electrode of the second FET.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
In FIG. 1A, a 200 nm thick buffer layer 12 made of InAlAs is formed on an InP substrate 11, a 10 nm thick channel layer 13 made of InGaAs, and a 15 nm thick carrier supply layer 14 made of InAlAs. It is a cross section of InP-HEMT device 10 of an embodiment.
[0018]
A first HEMT element 21 that has a first gate electrode 16 and is used for a circuit, and a second HEMT element 22 that has a second gate electrode 18 and functions as an element that absorbs collisionally ionized holes are included in the HEMT. Connected directly at layer 20. Reference numeral 15 denotes a drain electrode, 17 denotes a first source electrode serving as a source electrode of the first HEMT element 21 and a drain electrode of the second HEMT element 22, and 19 denotes a second source electrode. The combination of the film type and the film thickness of the layers 11 to 14 can be any film type and film thickness as long as the HEMT layer 20 can be formed.
[0019]
FIG. 1B is a diagram showing the potential distribution of the channel layer 13 in the cross section of FIG. In the present embodiment, the potential of the second source electrode 19 of the second HEMT element 22 is always kept lower than the first source electrode 17 of the first HEMT element 21. Therefore, the potential of the valence band 36 is kept so as to increase monotonously from the first HEMT element 21 toward the second HEMT element 22. For this reason, the holes 35 generated by impact ionization in the region 34 of the first HEMT element 21 are not accumulated in the region 33 that is the source of the first HEMT element 21, but are the source of the second HEMT element 22. It reaches the region 31 or the region 32 and eventually recombines with electrons to disappear.
[0020]
Further, when it is desired to suppress an increase in power consumption due to the drain current flowing through the second HEMT element 22, the second gate electrode 18 needs to be maintained at a potential such that the drain current does not flow into the second HEMT element 22. . In the present embodiment, since the threshold voltage of the second HEMT element 22 is −0.4V, the voltage applied to the second gate electrode 18 is 0.4V higher than that of the second source electrode 19. Use a lower voltage. At this time, the conduction band 37 has a potential higher than the Fermi level 38 in the vicinity of the second gate electrode 18, and the electrons 39 are depleted in this portion, so that a little drain current flows through the second HEMT element 22. Absent. As a result, in the HEMT device 10 of the present embodiment, a current flows substantially only between the first source electrode 17 and the drain electrode 15 of the first HEMT device 21, and the second HEMT device 22 The circuit operation of the HEMT element 21 is not affected at all, and the power consumption of the circuit is not increased.
[0021]
In addition, since the first source electrode 17 of the first HEMT element 21 is used in a grounded state, it is terminated here in terms of high frequency. Therefore, as compared with the case where an additional circuit having a frequency dispersion opposite to the frequency dispersion of the drain conductance of the HEMT element described in the prior art is provided, there is an advantage that no extra circuit is required to be inserted into the signal path. As a result, it is possible to suppress the frequency dispersion of the first HEMT element 21 without causing unintentional signal attenuation or extra phase rotation due to the influence of the additional circuit.
[0022]
[Second Embodiment]
FIG. 2 is a circuit diagram of a differential amplifier circuit using the HEMT element 10 shown in FIG. 1 as a constant current source HEMT element 10A. 41 and 42 are load resistors, 43 and 44 are differentially connected FETs, 45 and 46 are input terminals, and 47 and 48 are output terminals. Since it is for a constant current source, the first gate electrode 16 and the first source electrode 17 of the HEMT element 10A are grounded. When the current value is variable, a voltage other than the ground voltage can be applied to the gate electrode 16. Further, the VG terminal 49 connected to the second gate electrode 18 of the HEMT element 10A and the VS terminal 50 connected to the second source electrode 19 are drawn to the outside so that a control voltage can be applied.
[0023]
Here, in order to obtain the improvement effect of suppressing the frequency dispersion according to the present embodiment, it is necessary to apply a bias voltage to the VG terminal 49 and the VS terminal 50. First, a voltage lower than the voltage of the source electrode 17 is applied to the VS terminal 50 within a range where there is no problem with the withstand voltage of the FET. Further, when it is desired to suppress power consumption, the threshold value of the above InP-HEMT is −0.4V, and therefore the VG terminal 49 needs to be set to a voltage lower than the VS terminal 50 by 0.4V or more.
[0024]
In FIG. 2, the power supply voltage is VDD, the resistance values of the load resistors 41 and 42 are R, the current flowing through the constant current source HEMT element 10A is Id, the input signal applied to the input terminals 45 and 46 is sufficiently large, and the output amplitude is large. Considering the case of saturation, the output amplitude of the output terminals 47 and 48 is “R × Id”, and the center voltage of the output signal is “VDD−0.5 × R × Id”. Therefore, if frequency dispersion exists in the constant current source HEMT element 10A, Id changes depending on the frequency of the signals input to the input terminals 45 and 46 and the mark ratio (a high-level temporal ratio in the digital signal). This shows that the output amplitude and the center voltage of the output signal fluctuate. However, in the present embodiment, since Id is stabilized by the frequency dispersion suppressing effect, the above fluctuation in the output signal is not seen.
[0025]
The same improvement effect can be obtained even if the constant current source HEMT element 10A shown in FIG. 2 is replaced with the constant current source HEMT element 10B shown in FIG. In FIG. 3, the source electrode 17 of the first HEMT element 21 having the gate electrode 16 is grounded via the capacitor 51 together with the gate electrode 16. In this case, the drain current also flows through the second HEMT element 22 having the gate terminal 18, so that the power consumption of the entire circuit increases. However, the bias circuit to be connected to the VG terminal 49 and the VS terminal 50 is not required, and the circuit is simplified. Is possible.
[0026]
[Third Embodiment]
FIG. 4 shows a case where the HEMT device of the first embodiment is used in a high frequency power amplifier circuit as a third embodiment. Here, the InP-HEMT element 10 described in FIG. 1 is used as the high-frequency power amplification HEMT element 10C constituting the one-source-grounded amplifier. The output side of the input matching circuit 61 is connected to the gate electrode 16 of the HEMT element 10C for high frequency power amplification, and the input side of the output matching circuit 62 is connected to the drain electrode 15. By setting both the VG terminal 49 and the VS terminal 50 to the same voltage as in the second embodiment, a high frequency power amplifier with little gain fluctuation and distortion can be obtained. In the present embodiment, the circuit similar to that shown in FIG. 3 can be simplified.
[0027]
[Fourth Embodiment]
In the circuits of the second and third embodiments shown in FIG. 2 and FIG. 4, it is necessary to apply control voltages to the two locations of the VG terminal 49 and the VS terminal 50, which complicates the external control circuit. In order to improve this point, in this embodiment, as shown in FIG. 5 (a), the level shift diode 71 has its anode as the source electrode 19 of the HEMT element 10A (or 10C) and its cathode as the HEMT element 10A. A diode 71 connected to the gate electrode 18 (or 10C) may be used, and the VC terminal 52 may be connected to the cathode of the diode 71. Further, as shown in FIG. 5B, the VC terminal 52 may be connected to the cathode 71 of the diode 71 via a resistor 72. In this way, only one control terminal can be provided as the VC terminal 52. Two or more diodes 71 may be connected in series when the threshold voltage of the HEMT element is low.
[0028]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, the frequency dispersion of the HEMT element can be suppressed, and at this time, an increase in power consumption can also be suppressed. As a result, in a semiconductor circuit such as a high-speed digital circuit using this semiconductor device, the waveform distortion seen at the time of cross-point movement and signal rise / fall depending on the signal mark rate is suppressed. In the case of a semiconductor circuit using this semiconductor device for a general analog circuit, it is possible to suppress fluctuations in gain and increase in higher-order distortion.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view of a HEMT element that is a semiconductor device of a first embodiment, and FIG. 1B is an explanatory view showing an energy band along a channel layer of FIG.
FIG. 2 is a circuit diagram of a differential amplifier circuit according to a second embodiment.
FIG. 3 is a circuit diagram showing a modification of the differential amplifier circuit of FIG. 2;
FIG. 4 is a circuit diagram of a differential amplifier circuit according to a third embodiment.
5A and 5B are circuit diagrams of a fourth embodiment showing a modification of the bias circuit of the differential amplifier circuit of FIG. 2 and the high-frequency power amplifier circuit of FIG.
[Explanation of symbols]
10: InP-HEMT element 11: substrate (InP), 12: buffer layer (InAlAs), 13: channel layer (InGaAs), 14: carrier supply layer (InAlAs), 15: drain electrode, 16: first gate electrode , 17: first source electrode, 18: second gate electrode, 19: second source electrode, 20: HEMT layer, 21: first HEMT element, 22: second HEMT elements 31 to 34: region 35: Hall, 36: Valence band, 37: Conduction band, 38: Fermi level, 39: Electron 41, 42: Load resistance, 43, 44: FET, 45, 46: Input terminal, 47, 48: Output terminal 49: VG terminal, 50: VS terminal, 51: capacitor, 52: VC terminal 10A, 10B: HEMT element for constant current source, 10C: HEMT element for high frequency power amplification 61: On The matching circuit, 62: output matching circuit,
71: Diode, 72: Resistance

Claims (5)

A semiconductor device comprising a first FET and a second FET, wherein the source electrode of the first FET and the drain electrode of the second FET are common terminals,
The channel layers of the first and second FETs are composed of the same layer, the common terminal is grounded, and the voltage applied to the source electrode of the second FET is the voltage of the common terminal. A semiconductor device characterized by being set lower than the above. The voltage applied to the gate electrode of the second FET is set lower than the sum of the voltage applied to the source electrode of the second FET and the threshold voltage of the second FET. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein a DC voltage applied to the gate electrode of the first FET is set to a constant value. 3. A semiconductor circuit using the semiconductor device according to claim 1, wherein individual impedance matching circuits are connected to the gate electrode and the drain electrode of the first FET, respectively. 3. A semiconductor circuit using the semiconductor device according to claim 2, comprising a diode having an anode electrode connected to the second source electrode and a cathode electrode connected to the second gate electrode, and a cathode of the diode A semiconductor circuit, wherein a voltage applied to an electrode is set lower than a voltage of a source electrode of the second FET.

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