JPH11205055A - Variable gain differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand a gain changeable range by reducing he distortion in the case of using a FET for an amplifying element. SOLUTION: Between the source of a first amplifying FET 13 and the source of second amplifying FET 18, the mutual sources connected at a source connecting part 20A, and each gate is provided with first and second gain control FET 23A and FET 23B connected to a gain control terminal 22 respectively via second and third resistors 21A and 21B regulating a gain control voltage. In addition, at a resistance connecting part 20B mutually connected with the part 20A, it is provided with first and second gain stabilizing resistors 24A and 24B mutually connected in series and connected in parallel with FET 23A and 23B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain differential amplifier circuit used for a mobile communication device such as a portable telephone and a simple portable telephone, and a transceiver such as a TV, a CATV and a satellite broadcast.

[0002]

2. Description of the Related Art In recent years, digital broadband communication for the purpose of increasing capacity has been introduced as a communication method. Generally, a differential amplifier circuit is used as an amplifier circuit for amplifying an IF signal or an RF signal in digital communication. However, as the frequency band becomes wider, it is necessary to further reduce the distortion of the amplifier circuit, and an ultra-low distortion differential amplifier circuit or a variable gain ultra-low distortion differential amplifier circuit is indispensable. Therefore, in order to realize these digital broadband communications, a Schottky gate field effect transistor (MESFET) made of gallium arsenide (GaAs) having low current consumption and excellent high frequency characteristics and low distortion characteristics is used. Semiconductor amplifying circuits using the same are widely used.

Hereinafter, a conventional variable gain differential amplifier circuit will be described with reference to the drawings.

FIG. 6 shows a circuit configuration of a conventional variable gain differential amplifier circuit using an EFT as an amplifier. As shown in FIG. 6, a first amplifier receives a first RF signal from a first input terminal 101 at a gate, amplifies the first RF signal, and outputs the amplified first RF signal to a first output terminal 102 from a drain. For FE
T103, a first current source FET 105 having a drain connected to the source of the first amplifying FET 103, a source grounded via a first resistor 104 for self-bias, and a gate grounded; The second RF signal from the input terminal 106 is received by the gate, the second RF signal is amplified and output from the drain to the second output terminal 107, and the second RF signal paired with the first amplification FET 103 Amplification FET
And a second current source FET 109 whose drain is connected to the source of the second amplification FET 108, whose source is grounded via the first resistor 104, and whose gate is grounded.
And

The source of the first amplification FET 103 and the second
Between the source of the amplifying FET 108 and the second resistor 110A and the third
A gain control dual-gate FET 112 connected to the gain control terminal 111 via the resistor 110B, and a gain stabilizing fourth resistor 113 connected in parallel with the gain control dual-gate FET 112. , The gate of the first amplification FET 103 and the second amplification FET 1
08 is a gate for generating a gate bias, respectively.
Is connected to the gate bias application terminal 116 via the resistor 114 and the sixth resistor 115.

A desired amplified signal is output between the first output terminal 102 and the second output terminal 107 by connecting the first output terminal 102 and the second output terminal 107 to a power supply via a resistor or an inductor serving as a load.

Hereinafter, the operation of the variable gain differential amplifier circuit configured as described above will be described.

The first RF signal input to the first input terminal 101 is input to the gate of the first amplifying FET 103 and input to the second input terminal 106 to form a pair with the first RF signal. The second RF signal is supplied to the second amplification FET 10
8 is input to the gate. First current source FET 105
The second current source FET 109 and the second current source FET 109 have their gates grounded and their source potentials become positive due to the resistance component of the first resistor 104. , A predetermined operating current flows, and the in-phase components of the first RF signal and the second RF signal are suppressed, so that only the out-of-phase components of the input signal are amplified and output.

The gain of the differential amplifier circuit to which the input signal is differentially input is determined by the combined value of the resistance components of the gain control dual gate FET 112 and the fourth resistor 113 connected in parallel with each other. The combined value becomes the source resistance of the first amplification FET 103 and the second amplification FET 108 in the differential amplifier circuit, and the gain is controlled. That is, the dual gate FET 11 for gain control
By performing voltage control on the two gates of the two, the resistance value of the gain control dual gate FET 112 is externally controlled so that the gain of the differential amplifier circuit can be changed.

Here, a dual gate FET for gain control
Although 112 can be regarded as a gate voltage control type resistor, when the input signal level increases and the voltage applied between the source and drain of the gain control dual gate FET 112 increases, the FET becomes a non-linear element with respect to the operating voltage. Therefore, the distortion characteristic deteriorates at a change point where the channel resistance changes abruptly. Therefore, in order to prevent the deterioration of the distortion characteristic, the fourth resistor 113 is connected to the gain control dual gate FE.
The distortion characteristics are improved by connecting in parallel with T112 and dispersing the increasing voltage between the source and the drain by the dual gate.

[0011]

However, since the gates of the gain control dual-gate FETs 112 are close to each other, there is a problem that the high-frequency resistance decreases due to the parasitic capacitance between the two gates and the gain control characteristics deteriorate. is there.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to increase the range in which the gain can be changed by reducing distortion in a variable gain differential amplifier circuit using an FET as an amplifying element. And

[0013]

A variable gain differential amplifier circuit according to the present invention has a gate in which a first R signal is input from a first input terminal.
A first amplifying FET for receiving the F signal, amplifying the first RF signal and outputting the amplified signal to a drain, and a gate for receiving a second RF signal from a second input terminal; A second amplifying FET for amplifying and outputting to a drain, a gate for receiving a gain control signal, and a drain for the first amplifying FE.
A first gain control FET connected to the source of T, a gate receiving a gain control signal, and a drain connected to the second amplification F
A second gain control FET connected to the source of ET;
A first gain stabilizing resistor and a second gain stabilizing resistor connected in series at a resistor connection portion between a source of the first amplifying FET and a source of the second amplifying FET; The source of the first gain control FET and the source of the second gain control FET are connected to each other, and are also connected to the resistor connection.

According to the variable gain differential amplifier circuit of the present invention,
Two independent F control FETs connected between the sources of the first and second differential amplification FETs forming a pair.
Since the ET is used, the first and second gain control FEs
The parasitic capacitance between the gates of T is reduced. Furthermore, since the common source of the first and second gain control FETs is also electrically connected to the resistor connection of the gain stabilizing resistor, the DC level is stable when the gain control FET has a high resistance. I do.

In the variable gain differential amplifier circuit according to the present invention, a first input attenuating FET having a drain connected to a first input terminal via a first DC cut-off capacitor, and a drain connected to a second DC attenuator. A second input attenuating FET connected to the second input terminal via a blocking capacitor, wherein a source of the first input attenuating FET and a source of the second input attenuating FET are connected to each other; And the first input attenuation FE
T source and drain and second input attenuating FET
It is preferable that a gain control signal is input to each of the source and the drain. With this configuration, the gain control signal is input to the gates of the first and second gain control FETs and to the sources and drains of the first and second input attenuation FETs. Thereby, when the control voltage of the gain control signal is smaller than the first predetermined value (for example, the upper limit value), the gate bias of the first and second gain control FETs decreases and the channel resistance increases. ,
Since the resistance between the sources of the first and second differential amplification FETs is reduced, the gain of the amplifier circuit is reduced. On the other hand, when the control voltage of the gain control signal is higher than a second predetermined value (for example, a lower limit), the first and second input attenuation FETs
Since the gate bias is fixed and the source and drain biases decrease, the gate-source voltage increases as a result, the channel resistance decreases, the impedance between the differential inputs decreases, and the input signal attenuates. .

In the variable gain differential amplifier circuit according to the present invention, a drain is connected to the source of the first amplifying FET and the source is grounded, and the drain is connected to the first current source FET and the drain is connected to the second amplifying FET. A second current source FET connected to the source of the first current source and having the source grounded, wherein the gate of the first current source FET and the gate of the second current source FET are grounded via respective capacitors. It is preferred that

In the variable gain differential amplifier circuit according to the present invention,
It is preferable that the capacitor insulating film in the capacitor is made of a high dielectric substance.

[0018]

(First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of a variable gain differential amplifier circuit according to a first embodiment of the present invention. In FIG. 1, a variable gain differential amplifier circuit includes a gain control differential amplifier 1 that amplifies first and second RF signals differentially input to each other.
An input signal attenuator 2 for attenuating first and second RF signals differentially input to each other; and a bias generator for generating predetermined bias voltages for the gain control differential amplifier 1 and the input signal attenuator 2 And 3.

As shown in FIG. 1, the gain control differential amplifier 1
Receives the first RF signal from the first input terminal 11 at the gate, amplifies the first RF signal, and outputs the first
A first amplifying FET 13 that outputs to an output terminal 12 of
A first current source FET whose drain is connected to the source of the first amplification FET 13, whose source is grounded via a first resistor 14 for self-bias, and whose gate is grounded
15 and the second RF signal from the second input terminal 16 are received at the gate, and the second RF signal is amplified and output from the drain to the second output terminal 17.
And a second amplifying FET 18 paired with the second
Is connected to the source of the amplifying FET 18 and the source is the first.
Grounded via a resistor 14 of
And a current source FET 19.

Between the source of the first amplifying FET 13 and the source of the second amplifying FET 18, the respective sources are connected at a source connecting portion 20A, and each gate is connected to the FE.
A first gain control FET 23A and a second gain control F connected to the gain control terminal 22 via a second resistor 21A and a third resistor 21B for stabilizing the operation of T, respectively.
The ET 23B and a first gain stabilizing resistor 24A and a first gain stabilizing resistor 24A which are connected in series at a resistor connecting portion 20B connected to the source connecting portion 20A and connected in parallel with the first and second gain controlling FETs 23A and 23B. And two gain stabilizing resistors 24B.

The gate of the first amplifying FET 13 is connected to the bias generator 3 via a first bias resistor 25, and the gate of the second amplifying FET 18 is biased via a second bias resistor 26. It is connected to the generation unit 3. The drain of the first amplification FET 13 is the first
, And the drain of the second amplifying FET 18 is connected to the power supply terminal 29 via the second load inductor 28.

Next, the input signal attenuator 2 has its sources connected to each other and one gate connected to the third bias resistor 31A.
And the other gate is connected to the fourth bias resistor 31
B connected to the bias generation unit 3
Input attenuation FET 32A and second input attenuation FET 3
2B.

The first input attenuating FET 32A has a drain connected to the first input terminal 11 via a first DC blocking capacitor 33A, and a drain connected via a fifth bias resistor 34A. The sources are respectively connected to the gain control terminals 22 via the sixth bias resistors 34B. On the other hand, the drain of the second input attenuation FET 32B is connected to the second input terminal 16 via the second DC blocking capacitor 33B, and the drain is connected to the gain control via the seventh bias resistor 34C. Connected to terminal 22.

Next, the bias generation section 3 is connected in series, one end is connected to the power supply terminal 29, and the other end is grounded. A resistor 41B, a third bias generating resistor 42A and a fourth bias generating resistor 42B for dividing the resistor, one end of which is connected to the power supply terminal 29 and the other end of which is grounded; The common connection of the generation resistor 41A and the second bias generation resistor 41B is connected to the first bias resistor 25 and the second bias resistor 26 of the gain control differential amplifying section 1, and the third bias The common connection of the resistor 42A and the fourth bias generating resistor 42B is connected to the third bias resistor 31A and the fourth bias resistor 31B of the input signal attenuator 2.

Hereinafter, the operation of the variable gain differential amplifier circuit configured as described above will be described.

First, the operation of the gain control differential amplifier 1 will be described. Gain control The gain control of the differential amplifier 1
This is performed by changing the resistance value between the sources of the amplifying FET 13 and the second amplifying FET 18, and a first gain control FE in which the respective sources are connected between the sources.
By connecting T23A and the second gain control FET 23B in series, the first and second gain control FETs are connected.
23A and 23B are variable resistors.

Assuming that the threshold values of the first gain control FET 23A and the second gain control FET 23B are -1.0 V, the voltage value of each drain becomes about 2.0 V and is applied to the gain control terminal 22. If the control voltage exceeds the upper limit value of 2 V, the first and second gain control FETs 23
Since the channels A and 23B are open and have low resistance, the gain of the amplifier circuit is increased. On the other hand, when the control voltage is lower than 2 V, each channel of the first and second gain control FETs 23A and 23B has high resistance, and the resistance value between the sources of the first and second amplification FETs 13 and 18 increases. Therefore, the gain is reduced.

Further, by using two FETs, a first gain control FET 23A and a second gain control FET 23B, as variable resistors, when the signal voltage level is high, the first and second gain control FETs 23A and 23B are used. The voltage level applied between each source and drain of the FETs 23A and 23B is one F
Distortion is reduced by halving each in comparison with the case of using ET.

When a dual gate FET is used as a gain control FET as in the conventional example, it is difficult to make the shape of the drain and source asymmetric with respect to the gate for optimizing high frequency characteristics. In the present invention,
Since two single FETs are connected in series to the gain control FET and used, the single FET has an asymmetric shape of the drain and source, similarly to the amplification or current source FET. , So that the high frequency characteristics can be optimized,
As a result, desired performance can be easily obtained even when the gain control differential amplifier 1 is integrated.

Also, a control voltage from the gain control terminal 22;
That is, the first and second gain control FETs 23A, 23A
3B, when the respective channels of the first and second gain control FETs 23A and 23B enter a pinch-off state in which they are sufficiently closed, the first and second gain control FETs 23A , 23B become several tens MΩ, and the resistance value for changing the gain of the gain control differential amplifier 1 is, for example, a first gain stabilizing resistor 24A and a second gain stabilizing resistor 24K each having a resistance value of 5 KΩ. This is defined by the resistance 24B.

In this embodiment, the source connection 20A of the sources of the first and second gain control FETs 23A and 23B is connected to the first and second gain stabilizing resistors 24A and 24A.
B, since it is electrically connected to the resistance connection portion 20B.
When the first and second gain control FETs 23A and 23B are in a high-resistance state, the first and second gain control FETs 2
Since the source potentials of 3A and 23B can be fixed, the operation of these FETs 23A and 23B can be stabilized.

The first and second gain control FETs 2
When the source potentials of 3A and 23B are not fixed,
As described above, since the resistance value of the channel has increased to several tens of MΩ, the source potential greatly changes due to external noise or a minute current that is a leak current of the FET. Gain control FET 23A,
The operation of 23B becomes unstable and the distortion characteristics of the amplified signal deteriorate.

This will be described with reference to FIG. FIG.
Is a common source of the first and second gain control FETs 23A and 23B and the first and second gain stabilizing resistors 24A and 24B.
The results of simulating the change in the distortion amount of the third harmonic distortion (IM3) with respect to the gain control voltage when connected to the 4B resistance connection unit 20B and when not connected are shown. In FIG. 2, a curve 5 shows the output power value in the gain control differential amplifying section 1, and a curve 6 connects a common source of the gain control FETs 23A and 23B to the resistance connection section 20B of the gain stabilizing resistors 24A and 24B. I in case
The curve 7 shows the amount of distortion of the gain control FET 23.
A and 23B are shared by the gain stabilizing resistors 24A and 2B.
The distortion amount of IM3 when not connected to the 4B resistance connection unit 20B is shown. As shown in the curve 6, the gain control F
A common source of ET23A and 23B is connected to a gain stabilizing resistor 2
It can be seen that when connected to the 4A and 24B resistance connection portions 20B, the distortion amount of the IM3 is reduced by about 20 dB particularly in a region where the gain control voltage is 1.5 V or less, that is, in a region where the gain is relatively small.

Next, the operation of the input signal attenuator 2 will be described.

The input impedance of a differential amplifier circuit using an FET such as a MESFET as an amplifying element is large, and a resistance is applied between both input terminals of the first input terminal 11 and the second input terminal 16 (= differential input). , The input signal is attenuated by the damping resistor, and as a result, the gain can be reduced.

The present invention utilizes this basic principle, and includes a first input attenuating FET 32A and a second input attenuating FE.
T32B is used as a damping resistor, and the resistance value of the damping resistor is the fifth bias resistor 34A and the sixth bias resistor.
And the control voltage applied to the gain control terminal 22 connected via the bias resistor 34B and the seventh bias resistor 34C.

That is, if each threshold voltage of the first and second input attenuating FETs 32A and 32B is -1.0V, and each gate bias inputted from the bias generator 3 is 0.8V, the gain is The control voltage applied to the control terminal 22 is gradually increased from the low level side of the control voltage to approach 1.5 V, and each channel of the first and second input attenuation FETs 32A and 32B starts to open. ,
As each channel resistance decreases, the impedance between the differential inputs decreases. This causes a loss in the differential input signal, so that even if the signal level of the input RF signal is relatively high, the gain control differential amplifier 1
To lower the input level of the input signal
Distortion which is likely to occur at the time of large input can be reduced. At this time, the first and second input attenuation FETs 32A, 32
2B is the first and second DC blocking capacitors 33A and 33B.
As a result, the DC component of the input signal is removed, so that a stable operation can be performed.

Further, the control voltage is reduced to 1.5 V or less, and the first and second input attenuation FETs 32A, 32
Even when B has a high resistance, as shown in FIG.
The drain and source of the input attenuating FET 32A
And the source and drain of the second input attenuating FET 32B are connected to the sixth and seventh bias resistors 34B and 34C, respectively, so that the first and second bias resistors 34A and 34C are connected to the first and second bias resistors 34A and 34C. FET for input attenuation
The operations of 32A and 32B are stabilized.

The first and second input attenuation FEs
Since T32A and 32B are formed by connecting two single FETs in series, when the voltage level of the input signal is high, the voltage is applied between each source-drain of the first and second input attenuation FETs 32A and 32B. Voltage level is one FE
Since each is halved compared to the case of using T, distortion due to excessive voltage is reduced, and the shape of the source and the drain is asymmetric with respect to the gate similarly to the amplifying FET and the current source FET. As a result, the electrical characteristics can be optimized, so that even when the input signal attenuator 2 is integrated, a predetermined performance can be obtained easily and reliably.

The output characteristics of the variable gain differential amplifier circuit according to the present embodiment when the input signal attenuator 2 is not provided and when it is provided will be described with reference to graphs. Explain the nature. FIG. 3 shows a simulation result of output characteristics of output power when the input signal attenuator 2 is not provided in the variable gain differential amplifier circuit, and FIG. 4 shows a case where the input signal attenuator 2 is provided in the variable gain differential amplifier circuit. 4 shows simulation results of output characteristics of the output power of FIG. In FIG. 3, the output curve 8A shows the output power when the gain is maximum, that is, when the control voltage is minimized, and the output curve 8B shows the output power when the gain is minimum, that is, when the control voltage is maximized. As shown in FIG. 3, when the gain is gradually reduced, the output power does not increase monotonously in a region where the input power is relatively large. This is because a voltage change larger than the control voltage occurs between the drain and the source of the first and second gain control FETs 23A and 23B in the gain control differential amplifier 1 shown in FIG. 1 due to an excessive input signal. As a result, the control voltage fluctuates.

On the other hand, in FIG. 4, the output curve 9A shows the output power when the gain is maximum, ie, when the control voltage is minimized, and the output curve 9B shows the output power when the gain is minimum, ie, when the control voltage is maximized. 4 shows the output power, and as shown in FIG. 4, even in a region where the input power is relatively large, the output power monotonically increases, and it can be seen that the output characteristics are improved. This is because, as shown in FIG. 1, the first and second input attenuation FETs 32A and 32
Since a control voltage is applied to each drain of B, when the voltage exceeds a predetermined voltage value, the first and second input attenuation F
This is because the channel resistance of each of the ETs 32A and 32B decreases, and the signal level of the differential input signal attenuates for the reason described above.

As described above, according to the present embodiment, in the gain control differential amplifying section 1, the gain control FET as the variable resistor is configured by using two single FETs, and the common source is connected to the gain source. Since these two FEs are connected to the resistance connection portion 20B of the stabilizing resistors 24A and 24B.
A stable operation can be performed even when T has a high resistance.
Further, in the input signal attenuating unit 2, when an excessive input signal is input, the signal level is suppressed, so that distortion can be reduced.

Therefore, since the gain control differential amplifier 1 and the input signal attenuator 2 are controlled by the control voltage input from one gain control terminal 22, the start voltage of each control is applied to the bias generator 3 , And good gain control can be reliably performed over the entire control region.

In this embodiment, the FET has M
Although the ESFET is used, the present invention is not limited to this, and a MOSFET may be used.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 5 shows a circuit configuration of a variable gain differential amplifier circuit according to a second embodiment of the present invention. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. This embodiment and the first
The difference from this embodiment is the method of setting the operation bias for the first current source FET 15 and the second current source FET 19. As shown in FIG. 5, the first current source FE
In T15, the source is directly grounded, the gate is connected to the first capacitor 51 having a capacitor insulating film made of a high dielectric material such as BST, and the second current source FET 19 has the source directly grounded and the gate Are connected to a second capacitor 52 having a capacitor insulating film made of a high dielectric substance.

The gate of the first current source FET 15 is connected through a fourth self-biasing resistor 53, and the gate of the second current source FET 19 is connected to the fifth self bias source.
Are connected to a current source control terminal 55 via the resistor 54 of FIG.

According to the present embodiment, since the first and second current source FETs 15 and 19 have their sources directly grounded, the parasitic inductance component up to the ground (ground) is reduced, and Since the gates of the first and second current source FETs 15 and 19 are grounded via the capacitors 51 and 52, even if the variable gain differential amplifier circuit is operated in a higher frequency region, the high frequency characteristics deteriorate. Can be suppressed.

The first capacitor 51 and the second capacitor 52
Since both have a capacitive insulating film made of a high dielectric film, the external dimensions of the capacitive element on the substrate can be made smaller than in the case where a commonly used capacitive insulating film such as silicon oxide is used. Gain control differential amplifier 1 shown in
When integrating the first and second capacitors 51 and 5
2 is not an area penalty.

[0051]

According to the variable gain differential amplifier circuit of the present invention, since the first and second gain control FETs are single FETs, the parasitic capacitance between the gates is reduced, and the electrical connection between the source and the drain is reduced. Since the characteristics can be optimized independently,
There is no deterioration in high frequency characteristics. Further, since the common source of the first and second gain control FETs is also connected to the resistor connection of the gain stabilizing resistor, the gain control F
Since the DC level is stabilized when ET has high resistance, the gain control characteristic can be changed over a wide range while maintaining low distortion.

Further, first and second gain control FETs
Since two single FETs are used, the shape of each source and drain can have an asymmetric shape so that electrical characteristics can be optimized. It is easier to obtain.

In the variable gain differential amplifier circuit according to the present invention, the first input attenuating FET having the drain connected to the first input terminal via the first DC blocking capacitor, and the drain being connected to the second DC attenuator. A second input attenuating FET connected to the second input terminal via a blocking capacitor, wherein a source of the first input attenuating FET and a source of the second input attenuating FET are connected to each other; And the first input attenuation FE
T source and drain and second input attenuating FET
When a gain control signal is input to the source and the drain of the first FET, the gain control signal is input to the gates of the first and second gain control FETs and the first and second input attenuation FETs Are input to the source and drain.

As a result, when the voltage value of the gain control signal is reduced from the upper limit of the control region, the channel resistance of the first and second gain control FETs increases and the gain decreases, while the gain control signal decreases. Is increased from the lower limit of the control region, the channel resistances of the first and second input attenuating FETs decrease, and the impedance between the differential inputs decreases, and the input signal attenuates. Distortion at the time of input can be reduced.

Further, first and second input attenuation FETs
Since two single FETs are used, the shape of each source and drain can have an asymmetric shape so that electrical characteristics can be optimized. It is easier to obtain.

In the variable gain differential amplifier circuit of the present invention, a first current source FET whose drain is connected to the source of the first amplifying FET and whose source is grounded, and a drain whose second drain is the second amplifying FET are provided. A second current source FET connected to the source of the first current source and having the source grounded, wherein the gate of the first current source FET and the gate of the second current source FET are grounded via respective capacitors. In addition to reducing the parasitic inductance component up to the ground,
Since the respective gates of the first and second current source FETs are grounded via the respective capacitors, deterioration of high frequency characteristics can be suppressed even when operating in a higher frequency region.

In the variable gain differential amplifier circuit of the present invention,
When the capacitor insulating film of the capacitor is made of a high dielectric material, the external dimensions of the element can be made smaller than in the case where a capacitor insulating film such as silicon oxide is used, so that high integration is facilitated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a variable gain differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing simulation results of output operations when the common connection point of the gain control FETs is fixed and not fixed in the variable gain differential amplifier circuit according to the first embodiment of the present invention. is there.

FIG. 3 is a graph illustrating a simulation result of an output operation when an input signal attenuator is not provided in the variable gain differential amplifier circuit according to the first embodiment of the present invention.

FIG. 4 is a graph showing a simulation result of an output operation of the variable gain differential amplifier circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a variable gain differential amplifier circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a conventional variable gain differential amplifier circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 gain control differential amplifier 2 input signal attenuator 3 bias generator 11 first input terminal 12 first output terminal 13 first amplifying FET 14 first resistor 15 first current source FET 16 th 2 input terminal 17 2nd output terminal 18 2nd amplification FET 19 2nd current source FET 20A source connection 20B resistance connection 21A second resistance 21B third resistance 22 gain control terminal 23A first 23B Second gain control FET 24A First gain stabilization resistor 24B Second gain stabilization resistor 25 First bias resistor 26 Second bias resistor 27 First load inductor 28 Second Load inductor 29 power supply terminal 31A third bias resistor 31B fourth bias resistor 32A first input attenuating FET 32B second input attenuating FE 33A First DC blocking capacitor 33B Second DC blocking capacitor 34A Fifth bias resistor 34B Sixth bias resistor 34C Seventh bias resistor 41A First bias generating resistor 41B Second bias generating resistor 42A Third bias generation resistor 42B Fourth bias generation resistor 51 First capacitor 52 Second capacitor 53 Fourth resistor 54 Fifth resistor 55 Current source control terminal

Claims (4)

[Claims] 1. A first R input from a first input terminal to a gate.
A first amplifying FET for receiving the F signal, amplifying the first RF signal and outputting the amplified signal to a drain, and a gate for receiving a second RF signal from a second input terminal;
A second amplifying FET for amplifying the second RF signal and outputting the amplified signal to a drain; a first gain control receiving a gain control signal at a gate and having a drain connected to a source of the first amplifying FET For FE
T, the gate receives the gain control signal, and the drain is the second
A second gain control FET connected to the source of the amplifying FET, the source of the first amplifying FET, and the second amplifying F
A first gain stabilizing resistor and a second gain stabilizing resistor connected in series with each other at a resistance connection portion between the source of the first gain control FET and the source of the first gain control FET; 2. The variable gain differential amplifier circuit according to claim 2, wherein the sources of the gain control FETs are connected to each other and also connected to the resistor connection part. 2. A first input attenuation F whose drain is connected to the first input terminal via a first DC blocking capacitor.
ET; and a second input attenuating FET having a drain connected to the second input terminal via a second DC blocking capacitor, and a source of the first input attenuating FET and the second input attenuating FET. The source and the drain of the first input attenuating FET and the source and the drain of the second input attenuating FET are connected to each other with the gain control. 2. The variable gain differential amplifier circuit according to claim 1, wherein signals are respectively input. 3. A first current source FET having a drain connected to the source of the first amplifying FET and a source grounded, and a drain connected to the source of the second amplifying FET. And a second current source FET whose source is grounded. The gate of the first current source FET and the gate of the second current source FET are each grounded via a capacitor. The variable gain differential amplifier circuit according to claim 1 or 2, wherein: 4. The variable gain differential amplifier circuit according to claim 3, wherein the capacitor insulating film in the capacitor is made of a high dielectric.