JPH11346131A - High frequency gain variable amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To have a circuit operate with low current consumption, to reduce the deterioration of input/output reflection characteristic when the gain is variable and to secure stable operation, even in the case of expanding a variable gain width. SOLUTION: A first FET 1 on the side of an input terminal T1 and a second FET 2 on the side of an output terminal T2 are connected to serially share the power source current of a power source terminal T3 , when a ground potential is viewed from the terminal T3 , and to operate by a low current. In addition, a third FET 3 and a resistor 29 provided with a variable resisting function are arranged between the first and second FETs 1 and 2, and a capacitor 32 for grounding by a high frequency is connected between the source/ground potential of this second FET 2. Thus, the deterioration of output reflecting characteristic at gain variation is suppressed. In addition, a fourth FET 4 with the function of a signal attenuator is together provided with bias resistors 33 to 35, to improve the linearity of the inclination of total gain variable characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency gain variable amplifier circuit, and more particularly to a configuration of an amplifier circuit having a variable gain function for signals such as ultrashort waves to quasi-microwaves.

[0002]

2. Description of the Related Art Conventionally, an amplifier circuit for variably controlling the gain of a high-frequency signal has been used in a communication device or the like that handles signals from ultrashort waves to quasi-microwaves. There are the following. In FIG. 8, a first field-effect transistor (hereinafter referred to as F
ET) 1 is connected via an input matching circuit 6, and an output terminal T2 for outputting an amplified high-frequency signal has an influence on deterioration of the output reflection characteristic of the first FET 1 in a subsequent stage when the gain is variable. In order to prevent this, the second F
ET2 is connected via the input matching circuit 7.

In order to ensure the operation of the first FET 1, a resistive element (hereinafter referred to as a resistor) is provided at a position shown in the drawing.
9, 10 and a capacitance element (hereinafter referred to as a capacitance) 11, and the other FET 2 are provided with resistors 12, 13 and a capacitance 14. The capacitances 11 and 14 are the source electrodes (hereinafter referred to as sources) of the respective FETs 1 and 2. ) Is grounded at high frequency. A capacitor 15 is connected between the drain of the first FET 1 (hereinafter referred to as a drain) and the gate electrode (hereinafter referred to as a gate) of the second FET 2 for DC cut and impedance matching.

The first FE having the dual structure described above
A terminal T3 for providing a gain control voltage via the resistor 16 is arranged at the second gate of T1, and the gain of the signal output from the second FET 2 is controlled based on the gain control voltage. Further, the first FET 1 and the second FE
An inductor 1 is connected between the drain of T2 and the power supply terminal T4.
8 and 19 are arranged, and these inductors 18, 19
Thereby, the high-frequency isolation between the drains of the FETs 1 and 2 is increased. The power terminal T4 is grounded at a high frequency via the capacitor 20.

According to the variable gain amplifying circuit having such a configuration, a stable operation in a predetermined gain range can be realized without deteriorating the deterioration of the output reflection characteristic of the first FET 1 by the second FET 2. can do. That is, the second
When the FET2 is not used, when the gain is changed by applying a gain control voltage to the second gate electrode of the first FET1, the output reflection characteristic of the first FET1 greatly changes. This affects the filters and amplifiers connected to the subsequent stage, causing deterioration of the characteristics of the communication device system and the like and unstable operation.

[0006]

However, in the conventional circuit shown in FIG. 8, the added second FET is used.
2 requires a new current to operate, and there is a problem that a low current consumption operation cannot be realized.

Further, even when the second FET 2 is arranged, the deterioration of the output reflection characteristic cannot be sufficiently suppressed when the amplification gain is changed, and when the amplifier is operated in a wide band, the input reflection at a specific frequency is not performed. There is also a disadvantage that characteristics are deteriorated. Furthermore, if the circuit configuration is made to widen the variable range of the gain, there is a problem that it is difficult to secure a stable operation in consideration of the linearity of the slope of the overall gain variable characteristic.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to be able to operate with low current consumption, to reduce deterioration of input / output reflection characteristics even when the gain is changed, and It is an object of the present invention to provide a high-frequency gain variable amplifier circuit structure capable of ensuring stable operation even when the variable gain width is widened.

[0009]

In order to achieve the above object, according to the present invention, a first transistor for inputting a high-frequency signal to a gate electrode and a second transistor for outputting the high-frequency signal from a drain electrode are provided. Transistor and the first
An inductor element or a resistance element connected between the drain electrode of the second transistor and the source electrode of the second transistor for increasing high-frequency isolation between the electrodes; and a source electrode of the second transistor. Wherein the first and second transistors are configured to share a current from a power supply in series, wherein the first and second transistors are configured to share a current from a power supply in series. As a variable resistance element for changing the gain obtained by the first and second transistors without changing the high-frequency output impedance of the transistor, the variable resistor is arranged between the third transistor and the drain / source electrode of the third transistor. A resistor connected in series with the inductor or resistor between the first and second transistors; Characterized in that the connection was. According to a second aspect of the present invention, there is provided a fourth transistor connected between a drain electrode of the first transistor and a gate electrode of the second transistor and operating as a signal attenuator, wherein the first and second transistors are provided. The variable gain control voltage applied to the gate electrode of the third transistor for varying the gain obtained from the transistor is also connected to the gate electrode of the fourth transistor, and the drain electrode of the fourth transistor is connected to the drain electrode of the fourth transistor. Between the power supply, between the drain electrode of the fourth transistor and the ground potential, and between the source electrode of the fourth transistor and the power supply or the ground potential, the third transistor taking into account the variable gain characteristic of the third transistor. Bias for correcting the linearity of the slope of the overall gain variable characteristic with respect to the variable gain control voltage of the signal attenuation characteristic by the transistor No. 4 Characterized in that connecting the anti element.

[0010] The invention according to claim 3 is characterized in that the bias resistance element disposed on the source electrode side of the fourth transistor also serves as a bias resistance of a gate electrode of the second transistor. I do. Claim 4
In the invention described above, a resistance element and a capacitance element are connected in series between respective drain and gate electrodes of the first transistor and the second transistor, and the first transistor and the second transistor are configured as a broadband amplifier. An inductor element is connected between the input terminal and the gate electrode of the first transistor for correcting an input reflection characteristic at a specific frequency when viewed from the input terminal. According to a fifth aspect of the present invention, the variable gain amplifying circuit having the above configuration is formed as an integrated circuit.

According to the configuration of the first aspect, the first and second transistors share the power supply current in series instead of in parallel as in the prior art, so that they can be operated with low current. Further, the variable gain control is performed by the third transistor and the resistance element having the variable resistance function,
In addition, since the source of the second transistor is grounded at a high frequency by the capacitive element, it is possible to favorably suppress the deterioration of output reflectivity when the gain is changed.

According to the second aspect of the present invention, the fourth transistor functions as a signal attenuator, so that the variable gain width can be increased, and the total gain can be increased by appropriately selecting the value of the bias resistance element. The linearity of the slope of the variable characteristic can be improved. According to the configuration of the third aspect, the bias resistance element on the source electrode side of the fourth transistor and the bias resistance element on the gate electrode of the second transistor are shared, so that the number of resistance elements is reduced and
The DC-cut capacitance element disposed between these transistors is not required.

According to the fourth aspect of the present invention, a wide-band gain variable amplifier circuit is used. In this case, the input reflection characteristic at a specific frequency is corrected. Can be kept small. According to the configuration of the fifth aspect, the number of terminals can be reduced as compared with the case where the integrated circuit is not formed.

[0014]

FIG. 1 shows the configuration of a high-frequency variable gain amplifier circuit according to a first embodiment of the present invention.
, A first FET having a dual structure is provided between an input terminal T1 of a high-frequency signal and an output terminal T2 of the high-frequency signal.
1. A second FET 2 for improving the output reflection characteristic and a third FET 3 having a variable resistance function (details will be described later) are arranged. These FETs 1 to 3 are arranged in series with the power supply. . That is, the power supply terminal T4 and the ground (GND)
As shown, the drain electrode of the second FET 2 (hereinafter referred to as the drain) → the source electrode (hereinafter referred to as the source) → the drain of the third FET 3 → the source → the drain of the first FET 1 (DC cut by the capacitor 38) → The source is connected in that order. As a result, these FETs 1 to 3 directly share the power supply current.

The first FET 1 is a self-biased amplifier. The source of the first FET 1 is self-biased by a resistor 10, and the gate electrode (hereinafter, gate) is biased to the ground potential by a resistor 9. The high-frequency impedance of the source of the first FET 1 is reduced by the capacitor 11, so that the impedance between the source and the ground potential does not affect the high-frequency. Then, the second gate of this FET1 is short-circuited to its source. Further, a resistor 22 and a capacitor 23 are connected in series between the drain and the gate electrode of the first FET 1, thereby forming a negative feedback and operating the FET 1 as a broadband amplifier.

The second FET 2 is an amplifier of a fixed bias system. The gate of the second FET 2 is biased by a resistor 24 and a resistor 25 to a voltage obtained by dividing a power supply voltage.
Also at T2, a negative feedback is constituted by the resistor 26 and the capacitor 27 arranged in series between the drain and gate electrodes, and the device operates as a broadband amplifier.

An inductor 18 (in place of this inductor, a resistor is disposed between the source of the second FET 2 and the drain of the first FET 1) to increase high-frequency isolation between the two. The inductor 18 and the second FE
The third FET 3 and the resistor 29 (this is the third
(Disposed between the drain and source electrodes of the FET 3). A variable gain control voltage terminal T3 is arranged at the gate of the third FET 3 via a resistor 30. According to this variable resistance function, the gain of the first FET 1 can be changed by changing the voltage applied to the drain of the first FET 1 by utilizing the voltage drop generated here.

The source electrode of the second FET 2 is grounded to GND at a high frequency by a capacitor 32. If the DC voltage at the source electrode does not change when the gain is varied, the characteristics of the amplifier do not change significantly. In addition, the deterioration of the output reflection characteristic of the second FET 2 when the gain is changed becomes small.

Further, the first FET 1 and the second FE
During T2, a fourth FET 4 is connected,
It operates as a high-frequency attenuator between the stages of the broadband amplifier composed of 1 and 2. That is, this fourth FE
A voltage obtained by dividing the power supply voltage by the resistors 33 and 34 is set as the bias voltage of the drain of T4.
The bias voltage of the source of ET4 is pulled up to the power supply voltage by the resistor 35. The gate of the fourth FET 4 is connected via the resistor 36 to the above-described control voltage terminal T3.

The fourth FET 4 as the high-frequency attenuator
Is the drain of the FET 4 when the attenuation characteristic is minimum.
The source becomes conductive, and at this time, the fourth FE
The resistor 33 and the resistor 35 are connected to the drain and the source of T4.
, And a bias obtained by dividing the power supply voltage by the resistor 34. Then, the fourth FE is determined by these resistance values.
By applying different biases to the drain and source of T4, the slope of the attenuation characteristic is adjusted, and the variable gain control of the signal attenuation characteristic by the fourth FET 4 including the variable gain characteristic of the third FET 3 is performed. The linearity of the slope of the overall gain variable characteristic with respect to the voltage can be improved.

As shown in the figure, the second FE
Between the gate of T2 and the source of the fourth FET 4, D
A capacitor 37 for C (direct current) cut is arranged, and a capacitor 38 for DC cut is also provided between the drain of the fourth FET 4 and the drain of the first FET 1.
Further, an inductor 40 for improving the input reflection characteristic is connected between the input terminal T1 and the gate of the first FET 1 via a capacitor 39. Thus, it is possible to improve the input reflection characteristics at a specific frequency in an amplifier that varies the gain over a wide band.

According to the configuration of the first example, as described above, since the first to third FETs 3 share the power supply current in series, they can be operated with a low current. . A third FET 3 having a variable resistance function is provided between the source of the second FET 2 and the inductor 18.
And the resistor 29, the first FE as in the prior art is provided.
Instead of applying a control voltage to the second gate of T1,
The variable gain function can be performed by the variable resistance function between the FET1 and the second FET2.

That is, the variable gain control voltage Vc applied to the terminal T 3 is supplied to the third FET 3 via the resistor 30.
, And the control voltage Vc is applied to the second F
As the source voltage is higher than the source voltage Vs of ET2, the resistance value of the variable resistance portion decreases, and the gain of the first FET 1 increases. On the other hand, the variable gain control voltage Vc is equal to the second F
As the source voltage is lower than the source voltage Vs of ET2, the resistance value of the variable resistance portion increases, and the gain of the first FET 1 decreases. In such a variable gain control, since the source of the second FET 2 is grounded at a high frequency by the capacitor 32, the voltage of the source electrode does not change.
Deterioration of output reflection characteristics is reduced.

FIG. 4 shows changes in the source voltage of the second FET 2 and the drain voltage and the source voltage of the first FET 1 when the gain is changed. This graph shows that GaAs (gallium arsenide) MES (Metal) having a pinch-off voltage of -1 V is used as the first to third FETs 1 to 3.
Semiconductor) field-effect transistors, the power supply voltage (V _DD ) is 3 V, and the variable gain control voltage (Vc) is varied from 0 to 3 V. As shown in FIG. 4, the source voltage of the second FET 2 is:
Even if the gain changes, there is almost no change, and the second FE
It is understood that there is no change in the DC bias of each electrode of T2, and the deterioration of the output reflection characteristics is small.

FIG. 5 shows the first to fourth FETs 1 to 4 in the high-frequency gain variable circuit of the first example of the above embodiment.
In the same manner as above, GaAsM having a pinch-off voltage of -1 V
The fourth FET when the power supply voltage is 3 V and the variable gain control voltage (Vc) is changed from 0 to 3 V using an ESFET
4, the characteristics of the drain voltage and the source voltage are shown.

As shown, the fourth F of the first example is shown.
The drain voltage and the source voltage of ET4 are such that the control voltage is 1 V
It is set so that different voltages are applied when it becomes lower than this, whereby the slope of the overall gain variable characteristic can be maintained almost linearly. The linearity of the inclination will be described later in comparison with other embodiments.

FIG. 2 shows the configuration of a second example of the embodiment. In this high-frequency gain variable amplifier circuit, the first
As in the example, the first terminal is provided between the input terminal T1 and the output terminal T2.
FET1, the second FET2, and the third FET3 are connected so that the power supply current is shared in series with the ground potential viewed from the power supply terminal T4, and the first FET1 and the second FET2 are connected.
Between them, a fourth FET 4 is connected, and this is operated as a high-frequency attenuator between the stages of the broadband amplifier (consisting of the first and second FETs 1 and 2).

In the second example, the fourth FE
The bias voltage at the drain of T4 is pulled up to the power supply voltage by the resistor 33 in the figure, and the bias voltage at the source of the fourth FET 4 is set to a voltage obtained by dividing the power supply voltage by the resistors 24 and 25 in the figure. The resistors 24 and 25, which are the bias resistors of the gate of the second FET, are connected to the fourth FE.
Also used as a bias resistor for T4.

That is, since the drain and the source of the fourth FET 4 show the same characteristics, the fourth FET 4 of the first example
It is possible to arrange the drain-side resistors 33 and 34 on the source side and the source-side resistor 35 on the drain side. Therefore, in the second example, the resistors 33 and 34 of the first example
4 and 25, and the resistor 35 is replaced by the resistor 33, so that the bias resistance of the gate of the second FET 2 and the fourth
, The bias resistance of the source of the FET 4 can be shared. According to the second example, the number of resistive elements can be reduced, and the capacitor 37 serving as a DC cut is not required, so that the number of components can be reduced.

FIG. 3 shows a configuration of a third example of the embodiment. In the third example, the first FET described above is also used.
The first to fourth FETs 4 and the connection configuration attached thereto are as follows:
It is the same as the first example. In the third example, a power supply voltage is connected to the drain and the source of the fourth FET by the resistor 42.
To the voltage divided by the resistor 43 and the resistor 44 and the resistor 4
The set voltage is supplied via the terminal 5.

According to the third example, the first FET 1 to the third FET 3 can be connected in series to one power supply line to operate at a low current.
By providing the variable resistance function of T3 and the resistor 29 and the capacitor 32 for high-frequency grounding, there is an advantage that deterioration of output reflection characteristics can be kept small.

FIG. 6 shows the frequency variable gain characteristics of the first, second, and third examples (solid line in the first example, dotted line in the second example, and chain line in the third example). Represents). FIG. 6 shows the characteristics for a frequency of 1.5 GHz. As can be understood from FIG.
The gain can be varied in the range of dB or more.
In the circuits of the first and second examples, the linearity of the slope of the variable gain characteristic is improved as compared with the circuit of the third example.

That is, in the first and second examples, the fourth FET
By adjusting the values of the bias resistors 24, 25, and 33 to 35 of each electrode of No. 4, the linearity of the slope of the total gain variable characteristic considering the variable gain characteristic given by the third FET 3 is improved. On the other hand, in the case of this third example,
Since the drain and the source of the fourth FET 4 always have the same voltage, the linearity of the slope of the total gain variable characteristic with respect to the variable gain control voltage in the state where the signal attenuation characteristic of the fourth FET 4 is given is not compensated. It is.

Furthermore, in the high-frequency gain variable circuits of the first to third examples of the above embodiment, as described above, the input terminal T
An inductor 40 is provided between the first FET 1 and the first FET 1. When the inductor 40 is configured to operate at a narrow band frequency by using the inductor 40 and operates at a narrow band frequency, a specific frequency at the time of variable gain is used. Input reflection characteristics can be improved.

FIG. 7 shows the circuit of the first example.
The input VSWR (voltage standing wave ratio) characteristic (solid line) and the output VSWR characteristic (dotted line) when the variable gain control is performed with the variable gain control voltage for a specific frequency of 0 MHz, The input VSWR characteristics (dashed line) when is excluded are shown. According to FIG. 7, it can be seen that the characteristics of the first example of the solid line are better than the characteristics in the case where the inductor 40 is not included in the chain line.

Further, it is preferable that the circuits in each of the above examples be integrated circuits, whereby the number of terminals can be reduced. In other words, considering the case where the integrated circuit is not formed in the conventional FIG. 8, a power supply terminal for the inductor 18 is required.
When this and the GND terminal are added, six terminals must be provided. On the other hand, in the present invention, as shown in each figure, the input / output terminals T1, T2, the gain control voltage terminal T3,
There are five power supply terminals T4 plus GND terminals, which reduces the number of terminals.

[0037]

As described above, according to the first aspect of the present invention, the ground potential of the first transistor on the input side and the second transistor on the output side of the high-frequency gain variable amplifying circuit are viewed from the power supply terminal. Since the power supply current is shared in series, operation at a low current becomes possible, which can contribute to power saving. Further, a third transistor and a resistance element for varying the gain are arranged between the first and second transistors arranged in series, and a capacitor for high-frequency grounding is provided between the source and the ground potential of the second transistor. Since the elements are connected, the FET2 can change the gain of the first transistor without changing the high-frequency output impedance of the second transistor, thereby suppressing deterioration of output reflectivity when the gain is changed. Become.

According to the second and third aspects of the present invention, a fourth transistor is provided between the signal lines of the first and second transistors in order to increase the variable gain range of the amplifier circuit. Since the function of the high-frequency signal attenuator is added and the bias resistance element is provided, a high-frequency gain variable amplifier in which the third transistor and the fourth transistor are linked by one gain variable control voltage is configured. Also, the fourth
By adjusting the signal attenuation characteristic of the fourth transistor with the bias voltage, the slope of the total gain variable characteristic with respect to the variable gain control voltage of the signal attenuation characteristic of the fourth transistor is added in consideration of the variable gain characteristic provided by the third transistor. Can be improved.

Further, according to the third aspect of the present invention, the bias resistance on the gate side of the second transistor and the bias resistance on the source side of the fourth transistor are shared, so that the bias resistance and the DC cutoff can be reduced. There is an advantage that a capacitor is not required and the number of circuit elements can be reduced.

According to the fourth aspect of the present invention, the first and the second
In the case where a negative feedback circuit is added to the transistor (1) to form a variable gain amplifier circuit of a wide band, an inductor is arranged between the gate and the input terminal of the first transistor, and the input reflection characteristic at a specific frequency within a predetermined band is improved. Because it was good,
It is possible to improve the deterioration of the input reflection characteristics when the gain is changed.

According to the fifth aspect of the present invention, there is an advantage that an amplifier circuit that operates stably with a small number of terminals can be obtained by using the amplifiers of the first to fourth aspects as an integrated circuit.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a high-frequency gain variable amplifier circuit according to a first example of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a high-frequency variable gain amplifier circuit according to a second example of the embodiment;

FIG. 3 is a diagram illustrating a configuration of a high-frequency variable gain amplifier circuit according to a third example of the embodiment;

FIG. 4 is a graph showing characteristics of a source electrode voltage and a drain electrode voltage of a first FET and a source electrode voltage of a second FET when a variable gain control voltage is changed in the circuit of the first example.

FIG. 5 is a graph showing characteristics of a drain electrode voltage and a source electrode voltage of a fourth FET when a variable gain control voltage is changed in the circuit of the first example.

FIG. 6 is a graph showing gain characteristics when the variable gain control voltage is changed in the circuits of the first, second, and third examples (the first example is represented by a solid line, the second example is represented by a dotted line, and the third example is represented by a chain line). FIG.

FIG. 7 shows the input VSWR characteristic (solid line) and the output VSWR characteristic (dotted line) when the variable gain control voltage is changed in the circuit of the first example, and the input VSWR characteristic when the inductor element is removed from the first example circuit ( (Dashed line).

FIG. 8 is a diagram illustrating a configuration of a conventional high-frequency gain variable amplifier circuit.

[Explanation of symbols]

T1 ... input terminal, T2 ... output terminal, T3 ... variable gain control voltage terminal, T4 ... power supply terminal, 1 ... first FET, 2 ... second FET, 3 ... third F
ET, 4 ... fourth FET, 6 ... input matching circuit,
7 ... output matching circuit, 9, 10, 13, 16, 22,
24, 25, 26, 29, 30, 33 to 36, 42 to 4
5 ... resistance element, 11, 14, 20, 21, 23, 2
7, 32, 37 to 39 ... capacitive element, 18, 19, 4
0 ... Inductor element.

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[Procedure amendment]

[Submission date] July 22, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

Claims (5)

[Claims] A first electrode for inputting a high-frequency signal to a gate electrode;
, A second transistor that outputs the high-frequency signal from the drain electrode, and a high-frequency signal between the drain electrode of the first transistor and the source electrode of the second transistor. An inductor element or a resistance element for increasing isolation; and a capacitance element for reducing a high-frequency impedance at a source electrode of the second transistor, wherein the first and second transistors are connected to a power source. A third transistor and a variable resistor that change the gain obtained by the first and second transistors without changing the high-frequency output impedance of the second transistor are configured to share a current in series. The resistance element disposed between the drain and source electrodes of the third transistor is connected to the first and second transistors. A high-frequency variable gain amplifier circuit connected in series to the inductor element or the resistance element between the transistors. A fourth transistor connected between a drain electrode of the first transistor and a gate electrode of the second transistor and operating as a signal attenuator; A variable gain control voltage applied to the gate electrode of the third transistor for varying the gain obtained is also connected to the gate electrode of the fourth transistor, between the drain electrode of the fourth transistor and the power supply. The fourth transistor, which takes into account the variable gain characteristics of the third transistor, between the drain electrode of the fourth transistor and the ground potential, and between the source electrode of the fourth transistor and the power supply or the ground potential. Resistive element for correcting the linearity of the slope of the overall gain variable characteristic with respect to the variable control voltage of the signal attenuation characteristic due to noise RF variable gain amplifier circuit according to the first aspect, characterized in that connected. 3. The device according to claim 1, wherein the bias resistance element disposed on the source electrode side of the fourth transistor also serves as a bias resistance of a gate electrode of the second transistor. 3. The variable high-frequency gain amplifier circuit according to 2. 4. A resistor and a capacitor are connected in series between respective drain and gate electrodes of the first transistor and the second transistor, and the first transistor and the second transistor are configured as a broadband amplifier. 2. The method according to claim 1, wherein an inductor element for correcting an input reflection characteristic at a specific frequency when viewed from the input terminal is connected between the input terminal and a gate electrode of the first transistor. 4. The high-frequency gain variable amplifier circuit according to any one of claims 3 to 3. 5. The high-frequency variable gain amplifier circuit according to claim 1, wherein the variable gain amplifier circuit having the above configuration is formed as an integrated circuit.