JPH0758870B2 - Low feedback amplifier - Google Patents
Low feedback amplifierInfo
- Publication number
- JPH0758870B2 JPH0758870B2 JP60239738A JP23973885A JPH0758870B2 JP H0758870 B2 JPH0758870 B2 JP H0758870B2 JP 60239738 A JP60239738 A JP 60239738A JP 23973885 A JP23973885 A JP 23973885A JP H0758870 B2 JPH0758870 B2 JP H0758870B2
- Authority
- JP
- Japan
- Prior art keywords
- feedback
- transistor
- peaking
- amplifier
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Amplifiers (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、マイクロ波増幅器に関し、特に、抵抗帰還形
増幅器に関する。Description: FIELD OF THE INVENTION The present invention relates to microwave amplifiers, and more particularly to resistive feedback amplifiers.
従来の技術 従来、この種の増幅器は、数10MHzから数GHzの広い周波
数にわたり、良好な入力定在波比及び平坦な利得特性が
得られるために広い応用が考えられている。従来の抵抗
帰還増幅器は、第２図に示す構成（電子通信学会マイク
ロ波研究会資料MW82−31）が採られていた。2. Description of the Related Art Conventionally, this kind of amplifier has been widely applied because a good input standing wave ratio and a flat gain characteristic can be obtained over a wide frequency range of several tens of MHz to several GHz. The conventional resistance feedback amplifier has the configuration shown in Fig. 2 (Material MW82-31, Microwave Research Group of the Institute of Electronics and Communication Engineers).
電界効果トランジスタ（以後FETと記す）21、11の入力
容量に起因する負荷インピーダンスの低下による高周波
数域での利得低下を補償するためにピーキング用線路イ
ンダクタ25,26が設けられている。このピーキングイン
ダクタ25、26は次段のFET11の入力容量CGSと直列共振を
する周波数が存在し、この周波数で利得が高くなるピー
キング効果が得られる。帰還抵抗22,23により入力イン
ピーダンス整合及び出力インピーダンス整合を計ると共
に、広い周波数にわたり平坦な利得特性が得られてい
る。Peaking line inductors 25 and 26 are provided in order to compensate for a gain decrease in a high frequency range due to a decrease in load impedance caused by an input capacitance of field effect transistors (hereinafter referred to as FETs) 21 and 11. The peaking inductors 25 and 26 have a frequency at which they resonate in series with the input capacitance C GS of the FET 11 in the next stage, and the peaking effect that the gain becomes high is obtained at this frequency. Input impedance matching and output impedance matching are measured by the feedback resistors 22 and 23, and a flat gain characteristic is obtained over a wide frequency range.
発明が解決しようとする問題点 上述した従来の帰還増幅器は、ピーキングインダクタに
より高周波における利得低下を補償している。この時、
利得が最大となる周波数は、寄生容量等の寄生素子の影
響を無視するならば、ピーキングインダクタ25と２段目
のFET11の入力容量CGSとの直列共振周波数となる。この
周波数において２段目のFET11の入力端における電圧利
得は最大になるものの、初段FET21の負荷抵抗30の接続
点41におけるインピーダンスが低下し、電圧利得も低下
するために、入力端への帰還量が同時に低下し、入力イ
ンピーダンスが劣化する欠点がある。Problems to be Solved by the Invention In the above-described conventional feedback amplifier, the peaking inductor compensates for the decrease in gain at high frequencies. At this time,
The frequency at which the gain becomes maximum is the series resonance frequency of the peaking inductor 25 and the input capacitance C GS of the second-stage FET 11 if the influence of parasitic elements such as parasitic capacitance is ignored. Although the voltage gain at the input end of the second-stage FET 11 is maximum at this frequency, the impedance at the connection point 41 of the load resistor 30 of the first-stage FET 21 decreases, and the voltage gain also decreases, so the amount of feedback to the input end is increased. At the same time, the input impedance deteriorates.
また、入力インピーダンスが劣化するために、入力反射
による利得低下を生じピーキングによる広帯域化が十分
に達成されない欠点を持つていた。Further, since the input impedance is deteriorated, the gain is lowered due to the input reflection, and the banding due to peaking cannot be sufficiently achieved.
本発明は従来の上記事情に鑑みてなされたものであり、
従つて本発明の目的は、従来の技術に内在する上記欠点
を解消することを可能とした新規な抵抗帰還増幅器を提
供することにある。The present invention has been made in view of the above circumstances,
Therefore, it is an object of the present invention to provide a novel resistance feedback amplifier which can solve the above-mentioned drawbacks inherent in the conventional technique.
問題点を解決するための手段 上記目的を達成する為に、本発明に係る抵抗帰還増幅器
は、縦続接続される２個以上のトランジスタと、該各ト
ランジスタにより増幅された信号をトランジスタ入力に
帰還する抵抗を含む帰還回路と、利得の高周波特性を補
償するピーキングインダクタを持つ段回路とを少なくと
も有して構成され、前記ピーキングインダクタと後段ト
ランジスタとの接続点と前段トランジスタの入力端間に
前記帰還回路を設けたことを特徴とする。Means for Solving the Problems In order to achieve the above object, a resistance feedback amplifier according to the present invention feeds back two or more transistors connected in cascade and a signal amplified by each transistor to a transistor input. The feedback circuit includes at least a feedback circuit including a resistor and a stage circuit having a peaking inductor for compensating the high frequency characteristic of gain, and the feedback circuit is provided between a connection point of the peaking inductor and the rear stage transistor and an input end of the front stage transistor. Is provided.
実施例 次に、本発明をその好ましい一実施例について図面を参
照して具体的に説明する。Embodiment Next, the present invention will be described in detail with reference to the drawings for a preferred embodiment thereof.
第１図は本発明の一実施例を示す等価回路である。第１
図において、本発明の一実施例は、初段FET21の出力端1
3にDCカツト用キヤパシタ27を接続し、このキヤパシタ2
7と次段FET11との間にピーキングインダクタ25を接続
し、このピーキングインダクタ25と次段FET11との接続
点12と前段FET21のゲート電極間に、帰還抵抗22とDCカ
ツトキヤパシタ28を接続した２段増幅器である。負荷抵
抗30,31は、さらに高い周波数（数GHz以上）において
は、インダクタンスで置き換えることも可能である。FIG. 1 is an equivalent circuit showing an embodiment of the present invention. First
In the figure, one embodiment of the present invention shows the output terminal 1 of the first-stage FET 21.
Capacitor 27 for DC cut is connected to 3 and this capacitor 2
A peaking inductor 25 is connected between 7 and the next-stage FET 11, and a feedback resistor 22 and a DC cut capacitor 28 are connected between the connection point 12 between this peaking inductor 25 and the next-stage FET 11 and the gate electrode of the previous-stage FET 21. It is an amplifier. The load resistors 30 and 31 can be replaced with inductances at higher frequencies (several GHz or more).
また、帰還回路に挿入されているDCカツト用キヤパシタ
は、前段FET21と後段FET11を同じ直流バイアス条件下で
使用する場合には不用である。Further, the DC cut capacitor inserted in the feedback circuit is unnecessary when the front-stage FET 21 and the rear-stage FET 11 are used under the same DC bias condition.
本実施例の増幅器は、帰還回路がピーキングインダクタ
25と後段FET11との接続点12に接続されている。この接
続点12の電位は、ピーキングインダクタ25と後段FET11
の入力キヤパシタンスCGSが形成するタンク回路の中間
点にあるために、前段FET21の出力端13の電位に比べ、
このタンク回路の共振周波数付近までは高く保たれてい
る。従つて、従来例の増幅器では、ピーキングインダク
タ25と後段FETの入力キヤパシタンスCGSの共振周波数付
近では、非常に小さな帰還量しか得られなかつたのに対
し、本実施例の増幅器では、この共振周波数以上まで十
分な帰還量が得られる。In the amplifier of this embodiment, the feedback circuit has a peaking inductor.
It is connected to the connection point 12 between the second stage FET 11 and 25. The potential of this connection point 12 is the peaking inductor 25 and the post-stage FET 11
Since it is at the midpoint of the tank circuit formed by the input capacitance C GS of
It is kept high up to near the resonance frequency of this tank circuit. Therefore, in the amplifier of the conventional example, only a very small amount of feedback was obtained in the vicinity of the resonance frequency of the peaking inductor 25 and the input capacitance C GS of the post-stage FET. Up to the above, a sufficient amount of feedback can be obtained.
従つて、本実施例では、ピーキング周波数においても良
好な入力インピーダンスが保持され、その結果、さらに
高い周波数まで平坦な利得特性が得られる。Therefore, in this embodiment, a good input impedance is maintained even at the peaking frequency, and as a result, a flat gain characteristic is obtained up to a higher frequency.
本発明の抵抗帰還増幅器をGaAs基板上に形成することに
より、10MHzから4GHzにわたり15dB以上の平坦な利得特
性と入出力定在波比が1.5以下の良好なモノリシツク増
幅器を形成することが出来る。By forming the resistance feedback amplifier of the present invention on a GaAs substrate, it is possible to form a good monolithic amplifier having a flat gain characteristic of 15 dB or more from 10 MHz to 4 GHz and an input / output standing wave ratio of 1.5 or less.
また、本発明が、３段あるいはそれ以上の多段増幅器に
も適用し得ることは言うまでもない。Further, it goes without saying that the present invention can be applied to a multistage amplifier having three stages or more.
発明の効果 以上説明したように、本発明によれば、抵抗帰還増幅器
の帰還回路を前段FETのゲート電極と、ピーキングイン
ダクタ25と後段FETとの接続点12間に設けることによ
り、高周波数においても良好な入力インピーダンスを持
ち、その結果、従来例に比べ高い周波数まで平坦な利得
特性を得ることが出来る効果が得られる。As described above, according to the present invention, by providing the feedback circuit of the resistance feedback amplifier between the gate electrode of the front-stage FET and the connection point 12 between the peaking inductor 25 and the rear-stage FET, even at high frequencies. It has a good input impedance, and as a result, an effect that a flat gain characteristic can be obtained up to a higher frequency than the conventional example can be obtained.
第１図は本発明の一実施例を示す回路構成図である。 21……前段FET、11……後段FET、22……帰還抵抗、25…
…ピーキングインダクタ 第２図は従来例を示す回路図である。 23……帰還抵抗、24,26……ピーキングインダクタFIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. 21 …… front stage FET, 11 …… rear stage FET, 22 …… feedback resistor, 25…
... Peaking inductor Fig. 2 is a circuit diagram showing a conventional example. 23 …… Feedback resistor, 24,26 …… Peaking inductor
Claims (1)
と、該各トランジスタにより増幅された信号をトランジ
スタ入力に帰還する抵抗を含む帰還回路と、利得の高周
波特性を補償するピーキングインダクタを持つ段間回路
とを少なくとも有し、前記ピーキングインダクタと後段
トランジスタとの接続点と前段トランジスタの入力端間
に前記帰還回路を設けたことを特徴とする抵抗帰還形増
幅器。1. A stage having two or more transistors connected in cascade, a feedback circuit including a resistor for returning a signal amplified by each transistor to a transistor input, and a peaking inductor for compensating a high frequency characteristic of gain. A resistance feedback amplifier, comprising at least a circuit, and wherein the feedback circuit is provided between a connection point of the peaking inductor and the rear transistor and an input terminal of the front transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60239738A JPH0758870B2 (en) | 1985-10-26 | 1985-10-26 | Low feedback amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60239738A JPH0758870B2 (en) | 1985-10-26 | 1985-10-26 | Low feedback amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62100006A JPS62100006A (en) | 1987-05-09 |
| JPH0758870B2 true JPH0758870B2 (en) | 1995-06-21 |
Family
ID=17049194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60239738A Expired - Lifetime JPH0758870B2 (en) | 1985-10-26 | 1985-10-26 | Low feedback amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758870B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001298329A (en) * | 2000-03-21 | 2001-10-26 | Internatl Business Mach Corp <Ibm> | Radio frequency amplifier |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3793069B2 (en) | 2001-10-30 | 2006-07-05 | 三菱電機株式会社 | Semiconductor device |
| JP2008236354A (en) | 2007-03-20 | 2008-10-02 | Fujitsu Ltd | Amplifier |
| JP2009239816A (en) * | 2008-03-28 | 2009-10-15 | Icom Inc | Amplifier |
| JP5001980B2 (en) * | 2009-06-18 | 2012-08-15 | サイトウ共聴特殊機器株式会社 | Antenna booster unit for terrestrial digital TV |
| JP7238269B2 (en) * | 2018-05-11 | 2023-03-14 | オムロン株式会社 | signal processing circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6082823U (en) * | 1983-11-12 | 1985-06-08 | アルプス電気株式会社 | high frequency circuit |
-
1985
- 1985-10-26 JP JP60239738A patent/JPH0758870B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001298329A (en) * | 2000-03-21 | 2001-10-26 | Internatl Business Mach Corp <Ibm> | Radio frequency amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62100006A (en) | 1987-05-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |