JP3302643B2 - Distortion compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distortion compensating circuit for compensating for amplitude non-linearity and phase non-linearity of a high frequency amplifier to obtain a linear characteristic.

[0002]

2. Description of the Related Art Generally, in a low frequency amplifier, negative feedback is applied to improve the nonlinearity of the amplifier. However, in a high frequency amplifier, negative feedback is applied due to phase rotation in a feedback path. It is difficult. Therefore, the nonlinearity is improved by providing a distortion compensation circuit having input / output characteristics that cancels the nonlinearity of the high-frequency amplifier on the input side or the output side of the high-frequency amplifier.

FIG. 13 is a block diagram showing an ultra-high frequency amplifier provided with a distortion compensation circuit disclosed in Japanese Patent Application Laid-Open No. 55-16527. In the figure, 101 is a dual gate F
ET, 102 is the source of the dual gate FET 101,
103 is an input matching circuit, 104 is a dual gate FET
Reference numeral 101 denotes a first gate, 105 denotes an output matching circuit, 106 denotes a drain of the dual gate FET 101, 107 denotes a second gate of the dual gate FET 101, 108 denotes a reactance circuit, 109 denotes an input terminal, 110 denotes a directional coupling circuit, and 111 denotes a dual circuit. A gate FET amplifier circuit, 112 a detection circuit, 113 an FET amplifier circuit as a main amplifier,
14 is an output terminal. Here, dual gate FET
The amplification circuit 111 forms a distortion compensation circuit.

Next, the operation will be described. The microwave signal subjected to the amplitude modulation is input to an input terminal 109, is divided into two by a directional coupler 110, and one part is a detection circuit 1
12, the envelope detection amplification is performed by the reactance circuit 10
8 is applied to the second gate 107 of the dual gate FET 101. On the other hand, most of the microwave signal passes through the input
It is applied to the first gate 104 of the ET 101.

The voltage applied to the second gate 107 of the dual gate FET 101 causes the dual gate FET
101 is applied to the first gate 104 and the drain 106
By controlling the gain and passing phase characteristics of the microwave signal output from the
13 to compensate for the gain and pass phase characteristics. That is, F
When the input of the ET amplifier circuit 113 increases, the gain decreases due to the electrical parameters of the amplifying element, and the phase advances.
The dual-gate FET amplification circuit 111 compensates for characteristics by increasing the gain and delaying the phase as the input increases.

The output of the dual-gate FET 101 is input from the drain 106 of the dual-gate FET 101 to the FET amplification circuit 113 via the output matching circuit 105. The output terminal 11 of the FET amplifier circuit 113
4 obtains a distortion-compensated output signal. in this way,
This distortion compensation circuit has an advantage that distortion compensation can be performed without power loss since the distortion compensation circuit itself has a gain.

[0007]

Since the conventional distortion compensating circuit is configured as described above, there is a problem that the operation of the distortion compensating circuit itself may be unstable because the distortion compensating circuit itself has a gain. Was. In addition, there is a problem that a variation in a detection voltage may occur due to a variation in a detection element of the detection circuit 112, and the distortion compensation amount may be different.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a small-sized distortion compensating circuit suitable for monolithic operation without requiring a directional coupler or a detecting circuit. I do.

[0009]

A distortion compensating circuit according to the present invention connects a first gate of a dual gate FET to a signal path, connects a drain of the dual gate FET to ground, and connects a first gate of the dual gate FET to a ground. A predetermined DC voltage is applied to the first gate and the second gate.

In the distortion compensating circuit according to the present invention, the drain of the dual-gate FET is connected to the signal path, the first gate of the dual-gate FET is connected to the ground, and the drain and the second gate of the dual-gate FET are connected to the predetermined gate. Is applied.

In the distortion compensating circuit according to the present invention, a matching circuit for adjusting impedance is connected to a signal path.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing a distortion compensation circuit according to the first embodiment. In the figure, 1 is a dual gate F
ET, 2 are resistors for applying a bias from the DC power supply 4 to the first gate G1 of the dual-gate FET 1, 3a and 3b are capacitors for blocking DC, 5 is a DC power supply for biasing the second gate G2 of the dual-gate FET 1, 8 Is an input terminal of the distortion compensation circuit, and 9 is an output terminal of the distortion compensation circuit. The source S of the dual-gate FET 1 is open and the drain D is grounded. As described above, the distortion compensation circuit according to the first embodiment includes the dual gate FET 1
Are connected between the signal path from the input terminal 8 to the output terminal 9 and the ground.

FIG. 2 is a diagram showing an equivalent circuit of the distortion compensation circuit shown in FIG. FIGS. 2A and 2B are views showing the structure of the dual gate FET 1. FIG. In FIG. 2, R ₁ is the resistance of the first gate G1 junction of dual gate FET1, R ₂ is the resistance of the lower second gate, Cj is the capacitance of the first gate junction of dual gate FET1. Others are the same as FIG.

Here, the resistor R is connected to the dual gate FET 1
The resistance is defined by the resistance R ₁ of the first gate junction, the resistance R ₂ below the second gate, the resistance ₂ of FIG. 1, and the capacitance Cj of the first gate G1 junction of the dual gate FET1. The resistance R ₁ at the first gate junction of the dual gate FET ₁ is R ₁ [OHM], and the resistance R ₂ under the second gate is R ₂
[OHM], the resistance 2 in FIG. 1 is Rb [OHM] and the capacitance Cj at the junction of the first gate G1 of the dual gate FET1.
Is defined as jX [OHM], the resistance R is defined as follows.

(Equation 1) That is, the dual and the resistance R ₁ of the first gate lower gate FET1 increases the resistance R increases, the resistance R the resistance R ₂ of the second gate lower increases increases.

FIG. 3 shows the equivalent circuit of FIG.
FIG. 7 is a diagram showing calculation results of gain and pass phase characteristics with respect to changes in the phase shift. In FIG. 2, as the resistance R ₁ increases, the attenuation of the signal path decreases, and the reactance component decreases relative to the resistance R _{1. As} shown in FIG. The gain is increased and the phase is delayed.

In FIG. 1, when the input power of the distortion compensation circuit increases, the first gate G of the dual gate FET 1 is increased.
1. The voltage between the drain D decreases, and as a result, the resistance under the first gate G1 of the dual gate FET1 increases. That is, when the input power increases, R ₁ in FIG.
As a result, R increases. Therefore, when the input of the distortion compensating circuit increases, the gain and the passing phase characteristic as shown in FIG.

FIG. 4 is a diagram showing gain and passing phase characteristics with respect to input power of the distortion compensation circuit. As shown in FIG. 4, a characteristic is obtained in which the gain increases and the phase lags as the input power increases.

FIG. 5 is a diagram showing gain and passing phase characteristics with respect to input power when the DC voltage of the DC power supply 4 is used as a parameter. In Figure 1, the higher the DC voltage of the DC power supply 4, the resistance R ₁ of Figure 2 is reduced, the resistance R
Becomes smaller. Here, when the input power increases, the resistance R
However, at this time, a slight change in the resistance R greatly changes the gain and phase. Conversely, when the DC voltage of the DC power supply 4 is reduced, the resistance R ₁ increases and the resistance R increases. Therefore, even if the input power increases and the resistance R increases, the gain, The phase change is small.
Therefore, characteristics as shown in FIG. 5 are obtained, and by changing the bias of the first gate G1 of the dual-gate FET 1, the gain and passing phase characteristics of this distortion compensation circuit can be adjusted.

FIG. 6 is a diagram showing gain and passing phase characteristics with respect to input power when the DC voltage of the DC power supply 5 is used as a parameter. In FIG. 1, when the DC voltage of the DC power supply 5 is increased (close to 0 V), the resistance ₂ in FIG. 2 decreases, and the resistance R decreases. Here, as the input power increases, the resistance R increases. At this time, a slight change in the resistance R greatly changes the gain and phase. Also,
Conversely, when the DC voltage of the DC power supply 4 is reduced (increased in the negative direction), the resistance R ₂ increases and the resistance R increases. Therefore, even if the input power increases and the resistance R increases, the resistance R increases.
The change in gain and phase is small with respect to the change in. Therefore, the characteristics as shown in FIG.
By changing the bias of the second gate G2, the gain and passing phase characteristics of the distortion compensating circuit can be adjusted.

As described above, the distortion compensation circuit having the configuration of FIG.
It has the characteristic that the gain increases and the phase lags as the input power increases. This makes it possible to improve the linearity of the amplitude and phase characteristics by combining with an amplifier having a characteristic in which the gain decreases and the phase advances in response to an increase in the input power.

As described above, according to the first embodiment, the dual gate FET is connected between the signal path and the ground, and a predetermined bias is applied to each of the first gate and the second gate of the dual gate FET. As a result, it is possible to obtain a stable operation, improve the linearity of the amplitude and phase characteristics, and obtain a distortion compensation circuit which is small and suitable for monolithic operation.

Embodiment 2 FIG. FIG. 7 is a configuration diagram showing a distortion compensation circuit according to the second embodiment. In the figure, 11 is a dual gate FET, 14 is a dual gate FET 1
1 is a DC power supply for biasing the drain D, and the other components are the same as those in FIG. 1 of the first embodiment. Embodiment 2
The distortion compensating circuit of FIG. 1 also has the dual gate FET 11 connected between the signal path and the ground, but differs from FIG. 1 in the connection method of the dual gate FET 11 and that the DC power supply 14 is a negative power supply.

Next, the operation will be described. The equivalent circuit of the distortion compensation circuit of FIG. 7 is also the same as the equivalent circuit of FIG. 2 in the first embodiment, and the gain and the passing phase characteristic with respect to the change of the resistance R in the equivalent circuit are also the same as those of FIG.
Therefore, the gain and the passing phase characteristic with respect to the input power of the distortion compensation circuit in FIG. 7 are the same as those in FIG. 4 in the first embodiment.

FIG. 8 is a diagram showing gain and passing phase characteristics with respect to input power when the DC voltage of the DC power supply 14 is used as a parameter. This characteristic is different from FIG. 5 of the first embodiment in that the DC voltage as a parameter is negative, but the characteristic is the same. When the DC voltage of the DC power supply 5 is used as a parameter, gain and passing phase characteristics with respect to input power are the same as those in FIG. 6 of the first embodiment.

As described above, the distortion compensation circuit having the configuration shown in FIG. 7 also has the same distortion compensation characteristics as the distortion compensation circuit having the configuration shown in FIG. 1, and has a characteristic that the gain increases and the phase lags as the input power increases. . This makes it possible to improve the linearity of the amplitude and phase characteristics by combining with an amplifier having a characteristic in which the gain decreases and the phase advances in response to an increase in the input power.

As described above, according to the second embodiment, the dual gate FET is connected between the signal path and the ground, and a predetermined bias is applied to the drain and the second gate of the dual gate FET. It is possible to obtain a stable operation, improve the linearity of the amplitude-phase characteristic, and obtain a small-sized distortion compensation circuit suitable for monolithic operation.

Further, since all the power supplies may be negative DC voltages, the effect that the power supply circuit can be simplified can be obtained.

Embodiment 3 FIG. 9 is a configuration diagram showing a distortion compensation circuit according to the third embodiment. The distortion compensation circuit of FIG. 9 is obtained by adding a matching circuit 6 for adjusting the input impedance and a matching circuit 7 for adjusting the output impedance to FIG. 1 of the first embodiment. FIG. 10 is a block diagram showing a distortion compensation circuit as a specific example of FIG. 9, and in the figure, reference numeral 10 denotes a resistor for adjusting the output impedance.

Next, the operation will be described. FIG. 11 (a)
FIG. 3 is a diagram showing characteristics of an input reflection coefficient with respect to a frequency. The input reflection coefficient is adjusted by connecting a resistor 10 and adjusting an output impedance. The input reflection coefficient changes depending on the frequency because the impedance between the drain and the first gate of the dual-gate FET 1 has frequency dependency.

FIG. 11B is a diagram showing the characteristics of the output reflection coefficient with respect to the frequency. The output reflection coefficient is similarly adjusted by connecting the resistor 10 and adjusting the output impedance.

FIG. 11C is a diagram showing the characteristic of the gain with respect to the frequency. The gain is adjusted by connecting the resistor 10 and adjusting the output impedance.

FIG. 12 is a diagram showing gain and passing phase characteristics with respect to input power of the distortion compensation circuit having the configuration of FIG. As shown in the drawing, similar to the first and second embodiments, gain and pass phase characteristics can be obtained with respect to an increase in input power, and by connecting a resistor 10 and adjusting the output impedance, gain, The pass phase characteristic is adjusted. This makes it possible to adjust the characteristics in accordance with the gain and passing phase characteristics of the circuits used in combination.

In this embodiment, a resistor for adjusting the impedance is connected to the output terminal 9;
A resistor for adjusting the impedance may be connected to both the input terminal 8 and the output terminal 9. Further, not only a resistor but also a capacitor or an inductor may be connected.

Furthermore, in this embodiment, the first embodiment
Although the resistor 10 for adjusting the impedance is added to the distortion compensation circuit shown in FIG. 1 of FIG. 1, a resistor 10 for adjusting the impedance may be added to the distortion compensation circuit of FIG.

As described above, the impedance can be adjusted to an appropriate impedance by the matching circuit for adjusting the impedance, and the reflection characteristic, the gain, and the passing phase characteristic of the distortion compensation circuits of the first and second embodiments can be adjusted. Becomes possible. As a result, the non-linearity of the amplitude and phase characteristics of the amplifier used in combination can be further improved.

As described above, according to the third embodiment, the dual gate FET is connected between the signal path and the ground, and the first gate or the drain and the second gate of the dual gate FET have the predetermined bias, respectively. And a matching circuit that adjusts the input and output impedances to provide stable operation, improve the linearity of the amplitude and phase characteristics, and obtain a small-sized distortion compensation circuit suitable for monolithic integration. In this case, the characteristics can be adjusted in accordance with the gain and pass phase characteristics of the amplifier used.

[0037]

As described above, according to the present invention, the dual gate FET is connected between the signal path and the ground, and a predetermined bias is applied to each of the first gate and the second gate of the dual gate FET. It operates stably, improves the linearity of the amplitude and phase characteristics, and has the effect of obtaining a small-sized distortion compensation circuit suitable for monolithic operation.

According to the present invention, a dual gate FET
Is connected between the signal path and the ground, and the dual gate FE
By applying a predetermined bias to each of the drain and the second gate of T, it is possible to operate stably, improve the linearity of the amplitude and phase characteristics, and obtain a small-sized distortion compensation circuit suitable for monolithic implementation. effective.

According to the present invention, the provision of the matching circuit for adjusting the impedance has the effect that the characteristics can be adjusted in accordance with the gain and pass phase characteristics of the amplifier used in combination.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a distortion compensation circuit according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the distortion compensation circuit according to the first and second embodiments of the present invention.

FIG. 3 is a diagram showing calculation results of gain and pass phase characteristics with respect to a change in resistance R of the equivalent circuits according to the first and second embodiments of the present invention.

FIG. 4 is a diagram showing gain and passing phase characteristics with respect to input power of the distortion compensation circuits according to the first and second embodiments of the present invention.

FIG. 5 is a diagram showing gain and passing phase characteristics with respect to input power when the DC voltage of the DC power supply according to the first embodiment of the present invention is used as a parameter.

FIG. 6 is a diagram showing gain and passing phase characteristics with respect to input power when the DC voltage of the DC power supply according to the first and second embodiments of the present invention is used as a parameter.

FIG. 7 is a configuration diagram showing a distortion compensation circuit according to a second embodiment of the present invention.

FIG. 8 is a diagram showing gain and passing phase characteristics with respect to input power when a DC voltage of a DC power supply according to Embodiment 2 of the present invention is used as a parameter.

FIG. 9 is a configuration diagram showing a distortion compensation circuit according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram showing a distortion compensation circuit according to Embodiment 3 of the present invention.

FIG. 11 is a diagram showing characteristics of an input reflection coefficient, an output reflection coefficient, and a gain with respect to a frequency according to the third embodiment of the present invention.

FIG. 12 is a diagram showing gain and passing phase characteristics with respect to input power of a distortion compensation circuit according to Embodiment 3 of the present invention.

FIG. 13 is a configuration diagram showing a conventional distortion compensation circuit.

[Explanation of symbols]

 1,11 Dual gate FET, 6,7 Matching circuit.

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Nao Takagi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (56) References JP-A-55-16527 (JP, A) JP-A-6 −69731 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03F 1/32

Claims (3)

(57) [Claims] A first gate connected to a signal path; a drain connected to a ground of the dual gate FET; a first gate connected to the first gate of the dual gate FET;
A distortion compensation circuit, wherein a predetermined DC voltage is applied to a gate and a second gate. 2. A method for connecting a signal path to a drain of a dual-gate FET, connecting a first gate of the dual-gate FET to ground, and applying a predetermined DC voltage to a drain and a second gate of the dual-gate FET. A distortion compensation circuit characterized by the following. 3. The signal path according to claim 1, wherein a matching circuit for adjusting impedance is connected to the signal path.
The distortion compensation circuit as described.