JP3393514B2 - Monolithically integrated low phase distortion power amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low phase distortion power amplifier for amplifying a modulated wave of a band-limited digital signal with low phase distortion and high efficiency in a wireless communication device such as a mobile phone.

[0002]

2. Description of the Related Art Multivalued P used in mobile phones and the like
In the wireless communication device of the SK modulation digital system, it is required that the transmission power amplifier has high output, high efficiency, and low distortion. Low distortion of a wireless communication device can be easily realized by class A operation of an amplifier. However, in the class A operation, the conversion efficiency from the DC input to the microwave output is poor. Therefore,
AB for battery-powered mobile phones that require high efficiency
The class movement is the mainstream.

However, it is known that in the class AB operation FET amplifier, the output phase greatly changes with respect to the input power. When the multilevel PSK modulated wave is amplified by such an amplifier, the output signal spectrum is widened, and the adjacent channel is disturbed. Therefore, as shown in FIG. 11, a configuration is conceivable in which a predistortion type phase distortion compensation circuit 32 is connected in front of the power amplifier 31 using an FET, and a phase in the opposite direction is generated there to cancel the phase distortion. (Ogura, "Simplified Linearizer Using Si-Bipolar Transistor", 1993 IEICE Spring Conference, No.C-73).

The phase distortion compensating circuit 32 comprises a level adjusting attenuator 33 and an anti-phase distortion generator 34 using Si bipolar transistors. The power amplifier 31 using the FET has a characteristic that the passing phase advances as the input power increases. On the other hand, the anti-phase distortion generator 34 using the Si bipolar transistor has a characteristic that the passing phase is delayed as the input power increases, and the phase distortion opposite to the phase distortion generated in the power amplifier 31 using the FET is input in advance. By giving and injecting the signal, unnecessary phase distortion is canceled. However, since such a phase distortion compensating circuit 32 uses Si bipolar transistors, it is monolithic with the power amplifier 31 using FETs.
C conversion was difficult.

FIG. 12 shows the structure of a conventional power amplifier which is designed to reduce distortion (Japanese Patent Laid-Open No. 5-152877). In the figure, 41 is an input terminal, 42 is an output terminal, 43 is a source-grounded FET, 44 is an input matching circuit, 45 is an output matching circuit, 46 is a FET gate bias terminal, and 47 is an FET.
Is a drain bias terminal, and 48 is a non-linear resistance.

In this configuration, the phase advances due to the increase in drain conductance Gd due to the decrease in gain of the FET amplifier,
The focus is on the phase delay due to the increase of the drain-gate conductance Gdg. That is, by inserting the non-linear resistor 48, which changes according to the terminal voltage so as to cancel the phase change, between the drain and the gate,
It is configured to reduce the phase change of the FET amplifier. However, in such a power amplifier, the nonlinear resistance 4
Since a special control element such as 8 is used, the optimum G
It was difficult to adjust the dg to create it, and a special peripheral circuit was needed to actively control it.

[0007]

In the conventional power amplifier, if it is used in class A operation to suppress the phase distortion, the power efficiency becomes poor. Further, if a conventional phase distortion compensating circuit is added to compensate for phase distortion during class AB operation, it is difficult to form a monolithic IC, which increases the device cost. Further, even in the configuration using the non-linear resistance, the negative feedback is applied between the drain and the gate, so that the gain becomes small, and high output and high efficiency cannot be expected.

The present invention enables the FE without using any special additional circuit.
An object of the present invention is to provide a low phase distortion power amplifier which has a small phase change with respect to the input power of the T amplifier, has high power efficiency, can be easily made into a monolithic IC, and is low in cost.

[0009]

The low phase distortion power amplifier of the present invention comprises a grounded-gate FET (source grounded FET) that functions as an amplifier and a source-grounded FET (gate that functions as an anti-phase distortion generator having an amplifying function). (Grounded FET).

[0010]

In the present invention, a source-grounded FET having an amplifying function is provided.
The phase lead (phase lag) in the anti-phase distortion generator using (gate grounded FET) and the gate grounded FET (source grounded F
By combining with the phase delay (phase lead) in the amplifier using ET), the phase distortion of the entire power amplifier can be canceled.

[0011]

1 shows the basic configuration of a low phase distortion power amplifier according to the present invention (claim 1). In the figure, 11 is an input terminal, 12 is an output terminal, 13 is an anti-phase distortion generator using a source-grounded FET, 14 is an amplifier using a gate-grounded FET, and an anti-phase distortion generator using a source-grounded FET. 1
An amplifier 14 using 3 and a grounded-gate FET is connected in cascade.

The antiphase distortion generator 13 is connected to the gate ground F
A configuration may be adopted in which ET is used and the amplifier 14 is a source-grounded FET (claim 3). Alternatively, the connection between the anti-phase distortion generator 13 and the amplifier 14 may be reversed (claims 2 and 4).

The operation principle of this configuration will be described below with reference to FIGS. FIG. 2 shows input / output characteristics of the source-grounded FET amplifier and the gate-grounded FET amplifier during class AB operation. The arrow indicates the 1 dB gain compression point. Generally, in a source-grounded FET amplifier, the gain decreases as the input power increases, and the output phase changes in a direction in which it advances. On the other hand, in the gate-grounded FET amplifier, the gain decreases as the input power increases, and the output phase changes in a delaying direction.

Here, the factors that the phase distortion is reversed between the source-grounded FET amplifier and the gate-grounded FET amplifier will be analytically described. FIG. 3 shows a non-linear FET equivalent circuit. Gdg, Cgs, Ggs, and Gd can be considered as the non-linear element.
Therefore, using only one of these four nonlinear elements as a parameter, the phase change of S ₂₁ at the frequency f = 1.9 GHz was examined by the analysis method using harmonic balance. As the initial value parameter, a small signal S parameter of an FET having a gate width of 960 μm was measured and fitted. FIG. 4 shows the result. (1), (2), (3), and (4) are phase changes when Gd, Gdg, Cgs, and Ggs are parameters, respectively. In the case of the source ground and the gate ground, the lead and lag of the phase are reversed only when Gd is used as a parameter. When a large signal region, that is, a saturation region is reached, a breakdown current flows between the gate and the drain, and a forward leakage current flows at the Jottky junction of the gate, so that the phase advances due to an increase in Gdg and Ggs. On the other hand, in the initial stage where the low gain phase change begins to occur, the increase of Gd and Cgs particularly affects the phase characteristics.

Next, the phase change due to the increase of Gd and Cgs will be described using the simplified equivalent circuit shown in FIG. FIG. 5 (1) is an equivalent circuit of the source-grounded FET. In order to simplify the small signal analysis, the Gdg, Cdg, and Ggs that affect only the large signal are omitted. Here, the input / output impedance is Z ₀ .

[0016]

[Equation 1]

When this is transformed,

[0018]

[Equation 2]

It becomes Also, its phase is

[0020]

[Equation 3]

[0021] here,

[0022]

[Equation 4]

Putting it aside,

[0024]

[Equation 5]

The following holds. Therefore, in the case of the source-grounded FET, it is understood that the phase advances as Gd increases and the phase delays as Cgs increases.

Next, the grounded-gate FET will be described. FIG. 5 (2) is an equivalent circuit of the grounded-gate FET. Further, in order to simplify the analysis, Cds, which is connected in series between the input and the output and has a small capacitance value and is considered to have little influence on the phase change, is omitted.

[0027]

[Equation 6]

By transforming this,

[0029]

[Equation 7]

It becomes Also, its phase is

[0031]

[Equation 8]

It becomes here,

[0033]

[Equation 9]

Putting it aside,

[0035]

[Equation 10]

Is satisfied. Therefore, in the case of the gate-grounded FET, it can be seen that the phase is delayed with an increase in Gd and the phase is delayed with an increase in Cgs.

From the above, Gd is a source grounded FET
It can be understood that the leading and lagging phases of the gate-grounded FET are the main causes of reversal. FIG. 6 shows phase characteristics of the source-grounded FET and the gate-grounded FET with respect to the gate voltage Vgs. The bias point is changed from 1/2 to 1/10 of the saturation current value Idss, and the phase at the 1 dB gain compression point is compared.
In the source-grounded FET, the phase change is small near Idss / 4, and the phase advances greatly near Idss / 10. On the other hand, in the gate-grounded FET, the phase is delayed in the vicinity of Idss / 4, and the phase change becomes small in the vicinity of Idss / 10.
Therefore, the phase distortion can be reduced by setting the operating point in the source-grounded FET near Idss / 4 and in the gate-grounded FET near Idss / 10. That is, in order to improve the phase characteristics by itself, the operating point should be
Set near Idss / 4 and set the operating point for the grounded FET
Set it near Idss / 10.

As described above, since the phase changes of the source-grounded FET and the gate-grounded FET have mutually opposite characteristics, if the source-grounded FET and the gate-grounded FET are connected in cascade and the operating point is appropriately set, the result shown in FIG. As shown, the mutual phase distortions can be compensated. Note that FIG. 7 shows the phase change-input power characteristics of the configuration in which the source-grounded FET is arranged in the front stage and the gate-grounded FET is arranged in the rear stage, and ΔP represents the deviation of the phase change due to the gain of the source-grounded FET in the front stage. .

Therefore, as shown in FIG. 1, by combining the anti-phase distortion generator 13 using the source-grounded FET and the amplifier 14 using the gate-grounded FET, the operating point of each stage is optimized. The phase distortion can be compensated for in the entire power amplifier. In this configuration, both FETs having an amplifying action are combined, so that power efficiency is high and a monolithic IC can be easily formed. Even if the source-grounded FET and the gate-grounded FET have a multi-stage structure of three or more stages, a low phase distortion power amplifier can be similarly realized.

FIG. 8 shows the configuration of an embodiment of the low phase distortion power amplifier of the present invention. The present embodiment is a cascode type FET
It is applied to an amplifier. In the figure, in the cascode type FET amplifier, the drain terminal of the source-grounded FET 21 in the preceding stage and the source terminal of the gate-grounded FET 22 in the subsequent stage are cascode-connected. The gate terminal (Vg) of the source-grounded FET 21 and the gate terminal (V
c) and a bias circuit for supplying power to the drain terminal (Vd). The input signal is the source grounded FET21 in the previous stage.
Input to the gate terminal of the
The output signal is taken out from the drain terminal of. The source-grounded FET 21 in the front stage and the gate-grounded FET 22 in the rear stage function as an antiphase distortion generator and an amplifier, respectively, as described above, and can compensate each other's phase distortion.

Here, the output phase at the 1 dB gain compression point when the gate voltage (Vg) of the source grounded FET 21 in the front stage and the gate voltage (Vc) of the gate grounded FET 22 in the rear stage of the cascode type FET amplifier is changed. It shows in FIG.
It can be seen that the phase becomes smaller when the gate voltage of each FET is set in the negative direction. Changing the gate voltages Vg, Vc is equivalent to changing the voltage distribution between the two, and high output and high efficiency are achieved when the applied voltage in the preceding stage is smaller than the applied voltage in the succeeding stage.

Next, FIG. 10 shows a comparative example between the case where the bias point where the phase change is minimized in the cascode type FET amplifier is set and the case where the bias point where the power efficiency is maximized is set. It can be seen that if the bias point at which the phase change is minimized is set in order to improve the phase distortion, the efficiency becomes higher in the range where the specified value of the adjacent channel leakage power is actually satisfied. Here, the gate widths used for the source-grounded FET and the gate-grounded FET do not have to be the same, and the sizes may be changed in the front and rear stages.

This circuit configuration can be applied not only to the power amplifier operating in the saturation region but also to an amplitude limiting circuit in which a large phase change poses a problem.

[0044]

As described above, in the low phase distortion power amplifier of the present invention, by combining the source-grounded FET and the gate-grounded FET, the phase distortion of the entire amplifier is canceled to realize the low phase distortion. You can As a result, the spread of the spectrum at the output terminal can be reduced when amplifying the multilevel PSK modulated wave, and the influence on the adjacent channel can be reduced.

Further, since each FET can be manufactured on the same substrate, it is extremely easy to make the entire power amplifier into a monolithic IC, and the cost can be reduced.
Further, by suppressing the phase distortion, the back-off of the amplifier can be reduced and the operation can be performed in the vicinity of the saturation region, so that the power efficiency during use can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a low phase distortion power amplifier of the present invention.

FIG. 2 is a diagram showing input / output characteristics of a source-grounded FET amplifier and a gate-grounded FET amplifier.

FIG. 3 is a diagram showing an equivalent circuit of a non-linear FET.

FIG. 4 is a diagram showing a phase change when each non-linear element of the non-linear FET equivalent circuit is individually changed.

FIG. 5 is a diagram showing an equivalent circuit of a source-grounded FET and a gate-grounded FET.

FIG. 6 is a diagram showing phase characteristics of a source-grounded FET and a gate-grounded FET with respect to a gate voltage Vgs.

FIG. 7: Source-grounded FET in front stage, Gate-grounded FET in rear stage
The figure which shows the phase change of a structure-input electric power characteristic.

FIG. 8 is a diagram showing a configuration of an embodiment of a low phase distortion power amplifier of the present invention.

FIG. 9 is a diagram showing a phase change with respect to a gate voltage Vg.

FIG. 10 is a diagram showing a comparison result of input / output characteristics when the bias point is changed.

FIG. 11 is a diagram showing a configuration of a conventional power amplifier designed to reduce distortion.

FIG. 12 is a diagram showing a configuration of a conventional power amplifier designed to reduce distortion.

[Explanation of symbols]

11 input terminals 12 output terminals 13 Anti-phase distortion generator using source-grounded FET 14 Gate-grounded FET amplifier 21 Source grounded FET 22 Gate grounded FET 31 power amplifier 32 Phase distortion compensation circuit 33 Level adjustment attenuator 34 Anti-phase distortion generator 41 Input terminal 42 output terminals 43 FET 44 input matching circuit 45 Output matching circuit 46 Gate bias terminal 47 Drain bias terminal 48 Non-linear resistance

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-60-157305 (JP, A) JP-A-5-235646 (JP, A) JP-B-55-47485 (JP, B1) (58) Field (Int.Cl. ⁷ , DB name) H03F 1/00-3/72

Claims (5)

(57) [Claims] 1. A low-phase-distortion power amplifier in which an anti-phase distortion generator using a source-grounded FET is connected in front of an amplifier using a gate-grounded FET that performs class AB operation, in the amplifier and the anti-phase distortion generator. Is a monolith on the same substrate
Chicly integrated, the source-grounded FET and the gate-grounded FET are
Output phase-input power characteristic at 1 dB gain compression point
Output phase change depends on bias point
The nonlinear conductance that changes in the direction
Between the amplifier and the amplifier , the amplifier has an approximate power efficiency at the 1 dB gain compression point.
Bias point of the gate-grounded FET so that it becomes maximum
Within the range of 1/2 to 1/10 of the saturated drain current
The antiphase distortion generator controls the nonlinear conductance.
The change in the output phase at the 1 dB gain compression point is
The bias point of the source-grounded FET is set so that it becomes zero.
Set in advance within 1/4 to 1/10 of the saturated drain current.
Monolithic integrated low phase distortion power amplifier which is characterized in that it is a constant. 2. A low-phase-distortion power amplifier in which an anti-phase distortion generator using a source-grounded FET is connected to a stage subsequent to an amplifier using a gate-grounded FET that performs class AB operation, the amplifier and the anti-phase distortion generator. Is a monolith on the same substrate
Chicly integrated, the source-grounded FET and the gate-grounded FET are
Output phase-input power characteristic at 1 dB gain compression point
Output phase change depends on bias point
The nonlinear conductance that changes in the direction
Between the amplifier and the amplifier , the amplifier has an approximate power efficiency at the 1 dB gain compression point.
Bias point of the gate-grounded FET so that it becomes maximum
Within the range of 1/2 to 1/10 of the saturated drain current
The antiphase distortion generator controls the nonlinear conductance.
The change in the output phase at the 1 dB gain compression point is
The bias point of the source-grounded FET is set so that it becomes zero.
Set in advance within 1/4 to 1/10 of the saturated drain current.
Monolithic integrated low phase distortion power amplifier which is characterized in that it is a constant. 3. A low-phase-distortion power amplifier in which an anti-phase distortion generator using a gate-grounded FET is connected in front of an amplifier using a source-grounded FET that performs class AB operation, in the amplifier and the anti-phase distortion generator. Is a monolith on the same substrate
Chicly integrated, the source-grounded FET and the gate-grounded FET are
Output phase-input power characteristic at 1 dB gain compression point
Output phase change depends on bias point
The nonlinear conductance that changes in the direction
Between the amplifier and the amplifier , the amplifier has an approximate power efficiency at the 1 dB gain compression point.
Bias point of the source-grounded FET so that it becomes maximum
Within 1/4 to 1/10 of the saturation drain current
The antiphase distortion generator controls the nonlinear conductance.
The change in the output phase at the 1 dB gain compression point is
The bias point of the grounded FET is set so that it becomes zero.
Set in advance within the range of 1/2 to 1/10 of the saturated drain current.
Monolithic integrated low phase distortion power amplifier which is characterized in that it is a constant. 4. A low phase distortion power amplifier in which an antiphase distortion generator using a gate grounded FET is connected to a stage subsequent to an amplifier using a source grounded FET that performs class AB operation, the amplifier and the antiphase distortion generator. Is a monolith on the same substrate
Chicly integrated, the source-grounded FET and the gate-grounded FET are
Output phase-input power characteristic at 1 dB gain compression point
Output phase change depends on bias point
The nonlinear conductance that changes in the direction
Between the amplifier and the amplifier , the amplifier has an approximate power efficiency at the 1 dB gain compression point.
Bias point of the source-grounded FET so that it becomes maximum
Within 1/4 to 1/10 of the saturation drain current
The antiphase distortion generator controls the nonlinear conductance.
The change in the output phase at the 1 dB gain compression point is
The bias point of the grounded FET is set so that it becomes zero.
Set in advance within the range of 1/2 to 1/10 of the saturated drain current.
Monolithic integrated low phase distortion power amplifier which is characterized in that it is a constant. 5. The monolith according to claim 1 or 4.
Thick integrated low phase In the distortion power amplifier, The source-grounded FET and the gate-grounded FET are
Scord connected, By controlling the non-linear conductance, the 1 dB gain
The power efficiency at the compression point is almost maximum and the change in output phase is
By-pass of the cascode-connected FET so that it becomes zero
As point is within 1/4 to 1/10 of the saturated drain current
Monolithic integration characterized by presetting in
Low phase distortion power amplifier.