JPH08321726A - Amplifier circuit - Google Patents

Abstract

PURPOSE: To provide an MMIC amplifier circuit in which the loss of a matching circuit is reduced and the noise characteristic is improved. CONSTITUTION: A 1st spiral inductor L1 is connected to a gate terminal of a FET 10 and a 2nd capacitor C1 is connected to the other terminal of the 1st spiral inductor L1. An input signal is given via the 2nd capacitor C1. A connection point between the 1st spiral inductor L1 and the 2nd capacitor C2 connects to ground via the 2nd spiral inductor L2. A 1st capacitor C5 is connected between a gate terminal of the FET 10 and ground, and impedance matching with a line is taken by a matching circuit comprising the 1st capacitor C5 and the 1st spiral inductor L1. Since the inductance of the 2nd spiral inductor L2 is selected higher than the impedance matching, a loss in the 2nd spiral inductor L2 is reduced and the noise characteristic of the amplifier circuit is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic microwave IC (hereinafter referred to as MMIC). In particular, MMIC that uses lumped constants to match external signals
Regarding

[0002]

2. Description of the Related Art Conventionally, with regard to microwave band ICs,
A predetermined matching circuit is added to active elements such as FETs. An MMIC having such a configuration is described in, for example, Japanese Patent Publication No. 4-57124.

A variable loss matching variable matching circuit that obtains a low loss variable reactance is disclosed in Japanese Patent Laid-Open No. 5-251964. A delay equalizer capable of reducing loss due to mismatch is disclosed in Japanese Patent Laid-Open No. 46-46309.

[0004]

Normally, in an amplifier that pursues low noise characteristics, an input matching circuit is configured so as to satisfy the input impedance condition with the lowest noise derived from the characteristics of active elements. Then, the input signal is supplied to the input terminal of the active element via the input matching circuit.
For example, FIG. 7 shows a circuit diagram of a conventional amplifier circuit including such a matching circuit. At this time, as a matter of course, the impedance of the input matching circuit in this circuit is designed to have an optimum value for matching. Therefore, each lumped constant cannot take a free value.

By the way, ideally, it is necessary to reduce the loss of this input matching circuit as much as possible. This is because if there is a loss in the part of the input matching circuit, the signal is attenuated before reaching the active element, which causes deterioration of noise characteristics. In the circuit configuration of the above-mentioned prior art, the circuit configuration considering the loss due to the matching circuit is not made (as described above, it is not possible because the constant of the circuit is fixed),
There is a drawback in that the loss of the matching circuit is large when the MMIC (monolithic microwave IC) amplifier is constructed, and as a result, the noise of the amplifier becomes large.

It is known that most of the loss of the matching circuit is the loss of the spiral inductor on the MMIC (monolithic microwave IC).

Therefore, reducing the loss of the spiral inductor contributes to reducing the loss of the matching circuit. Since the loss of the spiral inductor changes depending on its inductance value, if the inductance value can be set to a value that minimizes the loss of the spiral inductor, the loss of the matching circuit can be made extremely small.

However, in the circuit configuration of the conventional amplifier described above, the inductance value of the spiral inductance is automatically determined by the original purpose of the matching circuit, which is to perform impedance matching. Therefore, it has been impossible to select the value of the spiral inductor so that the loss thereof is minimized.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an amplifier circuit in which the loss of the matching circuit is reduced and the noise characteristic is improved.

[0010]

A feature of the means according to the present invention is that it employs a circuit configuration in which the value of the spiral inductor can be set to a value that reduces the loss of the spiral inductor.

In order to solve the above problems, the first aspect of the present invention is to provide an active element, a first inductor having one end connected to an input terminal of the active element, an input terminal of the active element, and a ground. A first capacitor connected between the second capacitor and a second capacitor connected between the other end of the first inductor and an input terminal for inputting an input signal to be amplified, An amplifier circuit including: a second inductor connected between the other end of the first inductor and the ground.

A second aspect of the present invention is the amplifier circuit of the first aspect of the present invention, in which the second inductor is not directly connected to ground but is connected to ground through a third capacitor. It is an amplifier circuit characterized by being performed.

[0013]

According to the first aspect of the present invention, the first capacitor,
Impedance matching is performed by the first inductor. Therefore, it is possible to sufficiently increase the inductance value of the second inductor.

Further, according to the second aspect of the present invention, since the second inductor is installed through the third capacitor, it is possible to set a bias value other than 0 volt on the input terminal of the active element. Is.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an amplifier according to the preferred embodiment of the present invention. The circuit shown in FIG. 1 is a 1.5 GHz band low noise amplifier circuit, and its configuration will be described below.

Field effect transistor (hereinafter referred to as FET) 10
A first spiral inductor L1 is connected to the gate terminal of the FET 10. Further, a first capacitor C5 is further provided between the gate terminal of the FET 10 and the ground.
Is connected.

Further, the first spiral inductor L
A second capacitor C1 is connected to the other end of 1. The other end of the second capacitor C1 is connected to an input terminal, and an input signal in the 1.5 GHz band is input via this input terminal.

Further, the first spiral inductor L
The second spiral inductor L2 is connected between the connection point between the first capacitor C1 and the second capacitor C1 and the ground.

As described above, the matching circuit of the amplifier shown in FIG. 1 corresponds to claim 1 of the present invention.
It is also preferable that the second spiral inductor L2 is not directly grounded, but is grounded via the third capacitor C3 as shown in FIG. This figure 2
The configuration shown in (1) corresponds to claim 2.

Further, FIG. 1 shows that the drain terminal of the FET 10 is connected to the third spiral inductor L3 and the fourth capacitor C2. Also,
A fifth part is provided between the third spiral inductor L3 and the ground.
Capacitor C4 is connected. The output side matching circuit including the third spiral inductor L3 and the fourth capacitor C2 is configured in this way, but these inductance values and capacitance values do not significantly affect noise characteristics. . In the present invention, these configurations are not essential components.

The operation of this embodiment will be described below in comparison with a conventional circuit. First, in this embodiment, the FET 10 has a gate length of 0.7.
A HEMT (high electron mobility transistor) having a μm and a gate width of 600 μm is used. Further, as the values of the respective lumped constants, C1 = 10 pF, L1 = 9 nH, C2 = 1.
5 pF, L2 = 50 nH, C3 = 10 pF, L3 = 15
nH, L4 = 3.5 nH, C4 = 10 pF, C5 = 0.
It uses 45 pF.

In the conventional circuit, the value of the inductance of L2 in FIG. 7 is set to a predetermined finite value in order to match the input of the FET with the matching circuit on the input side. However, the loss of the spiral inductor at that value is often not the lowest value.

Here, the concept of the loss of the spiral inductor will be described with reference to FIG. As shown in FIG. 3, one of the inductors is grounded and the other is used as an input / output terminal to input an RF input. The ratio of the decrease of the output (reflected) power with respect to the input power is the loss of the inductor. That is, if the output power is equal to the input power in the circuit as shown in FIG. 3, the loss is 0 dB, and if the output power is half the input power, the loss is -3 dB. In this embodiment and the present invention, only the loss of the second spiral inductor L2 is considered and the loss of the first spiral inductor L1 is not improved.

According to an experiment conducted by the inventor of the present application, the relationship between the inductance value of the spiral inductor and its loss (1.5 GHz) has been found to be as shown in the graph of FIG. 4, for example. In the graph shown in FIG. 4, the horizontal axis represents the inductance value (nH) and the vertical axis represents the loss (d
B) is represented. As shown in the graph of FIG. 4, in the region where the inductance value is 4 nH or more, it can be seen that the loss decreases as the inductance value becomes larger (FIG. 1 shows the case where the frequency is around 1.5 GHz. Even if the maximum loss is different, the same tendency is shown).

The spiral inductor has a series resistance inside, and its internal series resistance value increases in proportion to the length of the line of the inductor. Further, the inductance value of the spiral inductor has a large number of turns, and the larger the line length, the larger the inductance value. Therefore, the larger the inductance value, the larger the internal resistance value.

Due to such characteristics of the spiral inductor, first, when the inductance value becomes small,
Since the resistance decreases, the loss gradually decreases. If the inductance value is 0, the resistance value is also 0, and the loss is also 0. Therefore, as shown in FIG. 4, the graph draws a curve that converges so that the loss becomes 0 when the inductance value is 0.

On the other hand, when the inductance value increases and approaches infinity, the impedance value also increases, and the current flowing inside approaches 0. The inductor loss is the power consumption due to the internal resistance (power consumption = (1 /
2) × (current ^ 2) × (internal resistance)). Therefore, as the inductance value approaches infinity, the power consumption decreases, and the inductor loss also approaches 0.

After all, when the inductance value is 0 or close to infinity, the loss of the inductor also becomes small, and when the internal resistance value and the current value are appropriately large, the loss becomes the largest. Therefore, as shown in the graph of FIG. 4, the inductor loss has a maximum value at an appropriate inductance value.

According to the graph of FIG. 4, in the region where the inductance value is 4 nH or more, the loss decreases as the inductance value increases (1.5 in FIG. 4).
Although it is in the vicinity of GHz, the same tendency is shown only when the maximum values of loss are different even in different frequency bands).

Therefore, if the value of the second spiral inductor can be made infinite to 0, the loss of the matching circuit can be remarkably reduced.

The characteristic of this embodiment is that the FET
The first spiral inductance L1 is connected to the input terminal of 10.
Is to insert the first capacitor C5 (in parallel). By inserting the first capacitor C5 here (FIG. 1), it is possible to set the inductance value of the second spiral inductor L2 to be as large as possible, and as a result, to set the loss of the spiral inductor to be small. Becomes

Hereinafter, it will be described using a Smith chart that the inductance value of the second spiral inductor L2 can be made infinite. First, the inductance values in the input matching circuit in the circuit of this embodiment and the conventional circuit will be compared.

The input impedance of the FET 10 near 1.5 GHz can be represented, for example, by a point a in the Smith chart shown in FIG.

The matching circuit according to this embodiment has an input VSWR.
In order to achieve both a reduction in (voltage standing wave ratio) and a reduction in noise figure, a series feedback circuit configuration is used in which an inductor is connected to the source of the FET 10 (similar to a conventional matching circuit).
Therefore, the point a is located inside the Smith chart as compared with S11 of the normal FET 10. According to the conventional matching path, the series impedance L1 moves the constant resistance circle from the point a to the point b, and the parallel inductance L2 moves the low conductance circle to match the characteristic impedance of 50 ohms from the point a. This is done by moving from point b to point c. Further series capacitor C
Move from point c to point o by 1 (here, point a to b
The inductance value to the point is L1p, and the inductance value from the point b to the point c is L2p).

In this way, in the conventional matching circuit, impedance matching is performed by moving from point a to b → c → o.

On the other hand, in the circuit of this embodiment, first, the first capacitor C5 moves from the point a to the point d on the constant conductance circle, and the first spiral inductor L1 moves the constant resistance circle from the point d to the point o. Move to (where
The inductance value of the first spiral inductor required to move from the point d to the point o is L1n).

As described above, in the conventional circuit, there is always a matching path from the point b to the point c due to the second spiral inductance L2 (inductance value L2p) except in the special case where the point a is in the constant resistance circle of 50 ohms. This is necessary, which means that the inductance value L2p has to be some predetermined finite value.

On the other hand, in this embodiment, the first capacitor C5 is added between the input terminal of the FET 10 and the ground terminal, so that the matching path from the point a to the point d is 50 ohms. The impedance can be set on the constant resistance circle for the time being. As a result, only the first spiral inductor L1 can move from the point d to the point o.

As described above, in the matching circuit according to this embodiment, impedance matching can be performed without using the second spiral inductor L2.

Therefore, in this embodiment, the second spiral inductor L2 having an almost infinite inductance value is used. That is, if the second spiral inductance having a sufficiently large inductance value is used, the operations of the first spiral inductance L1 and the first capacitor C5 are not affected.

In the case of the circuit shown in FIG. 2 (corresponding to claim 2), the second spiral inductor L2 having an almost infinite inductance value and the second capacitor having a sufficiently large capacitance. C1 and are used. As a result, the point o on the Smith chart in which the impedance matching is performed is caused by the second spiral inductor L2 (or the second capacitor C1 in the case of the circuit shown in FIG. 2) having a sufficiently large value. Without moving (changing), the matching condition is still satisfied.

Of course, the second spiral inductor L
The matching condition is already satisfied without connecting the second and second capacitors C1. However, the DC bias to be applied to the gate of the FET 10 is always necessary, and since the application is performed via the second spiral inductor L2, the second spiral inductor L2 has a necessary configuration.

Further, even when the DC bias is set to 0V, the circuit shown in FIG. 1 (corresponding to claim 1) is adopted, and the DC bias is applied through the second spiral inductor L2. The configuration of the second capacitor C1 is also necessary to remove the DC component that may be superimposed on the input signal.

Although not shown in FIG. 1, the FET
In order to make the DC voltage of the source terminal of 10 higher than the DC voltage of the gate terminal, it is possible to insert a resistor and a capacitor in parallel between the inductor L4 and the ground. The same applies to FIG.

In the present embodiment, the second spiral inductor L2 employs a finite value of 50 nH instead of the infinite value as described above. This is because, as is clear from the graph of the noise figure reduction effect shown in FIG. 6, the improvement of the noise figure is saturated even if the inductance value is set to a certain value or more. Since the size of the spiral inductor having an infinite inductance value becomes large, a value of 50 nH which can achieve a sufficient improvement in the noise figure is adopted in this embodiment.

As described above, the spiral inductor having an inductance value close to infinity (50 nH in this embodiment) has a small loss as shown in FIG. 4, and therefore the loss of the entire matching circuit can be reduced. Become. As a result, the circuit having this configuration can realize an amplifier having excellent noise characteristics. FIG. 6 shows how the noise figure reduction in the embodiment is actually compared with the conventional circuit. 6 (a) (b)
The horizontal axis represents the shunt inductor diameter (μm) of the spiral inductor, and the vertical axis represents the noise figure (dB) of the MMIC.
Represents In addition, what is shown in parentheses on the horizontal axis is a number representing an inductance value (nH). In FIG. 6 (a),
The inductance value and MM of the second spiral inductor in the case of the conventional circuit configuration and the circuit configuration according to the present embodiment
A graph representing the noise figure of the IC is shown. Figure 6
In addition to (a), (b) shows a plot of changes in noise figure when the inductance value of the second spiral inductor is changed.

As described above, according to this embodiment, the inductance value of the second spiral inductor L2 can be increased as compared with the conventional one, and the loss of the input matching circuit for that purpose can be reduced, thereby reducing the noise of about 0.3 dB. It will be understood that there is an index reduction effect. In addition, although an example using a spiral inductor is shown in the present embodiment, the inductance value of the inductor corresponding to the second spiral inductor in the present embodiment is sufficiently large even when other types of inductors are used. By doing so, the same operation and effect as those of the present embodiment can be achieved.

Although the MMIC has a feature that it can be constructed in a small area, increasing the inductance of the spiral inductor as in this embodiment cancels the feature of miniaturizing the amplifier MMIC. is not. The reason is that an infinite inductance value can be obtained with a finite size due to the effect of the parasitic capacitance of the spiral inductor, and the loss does not increase so much even if the wiring cross-sectional area of the spiral inductor is slightly reduced. This is because an inductor with a smaller area and a smaller loss can be realized as compared with a spiral inductor having a large width (wiring cross-sectional area) and a small inductance value.

[0050]

As described above, according to the first aspect of the present invention, since the inductance value of the second inductor can be set to be sufficiently large, the loss of the matching circuit can be reduced. As a result, an amplifier circuit with improved noise characteristics can be provided.

Further, according to the second aspect of the present invention, since the bias voltage applied to the input terminal of the active element can be freely set, a circuit structure having a high degree of freedom according to the characteristics of the active element can be realized. . As a result, an amplifier circuit having a wide range of applications can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an amplifier circuit according to an embodiment.

FIG. 2 is a circuit diagram of another amplifier circuit according to the present embodiment.

FIG. 3 is an explanatory diagram illustrating a loss of the spiral inductor.

FIG. 4 is a graph showing the relationship between the inductance value and the loss of the spiral inductor.

FIG. 5 is a Smith chart showing a state of impedance matching in the present embodiment.

FIG. 6 is a graph showing a comparison of noise figures of the amplifier circuit according to the present embodiment and a conventional amplifier circuit.

FIG. 7 is a circuit diagram of a conventional MMIC amplifier circuit.

[Explanation of symbols]

10 FET, L1 first spiral inductor, C
5 First Capacitor, C1 Second Capacitor, L2
Second spiral inductor, C3 third capacitor, C2 fourth capacitor, C4 fifth capacitor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takatoshi Kato, Nagakute-cho, Aichi-gun, Aichi 1st 41st Yokomichi, Yokoshiro Central Research Institute Co., Ltd. (72) Inventor Hiroaki Hayashi Nagakute, Aichi-gun 41, Yokoshiro Road Inside Toyota Central Research Institute Co., Ltd.

Claims (2)

[Claims] 1. An active element, a first inductor having one end connected to an input terminal of the active element, a first capacitor connected between an input terminal of the active element and ground, A second capacitor connected between the other end of the first inductor and an input terminal for inputting an input signal to be amplified, and a second capacitor connected between the other end of the first inductor and ground A second inductor, and an amplifier circuit including :. 2. The amplifier circuit according to claim 1, wherein the second inductor is connected to the ground via a third capacitor.