JP2002252550A - Semiconductor integrated circuit and system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can increase the usable input power value without increasing the gate width of a transistor used for a variable attenuator and a system which uses the semiconductor integrated circuit. SOLUTION: This circuit is equipped with the variable attenuator which has an FET 5 connected to main lines 4a and 4b in parallel and provided with a drain, a source, and a gate and attenuates signals inputted to the main lines 4a and 4b with a control voltage applied to the gate of the FET 5; and the drain of the FET 5 is connected to the main lines 4a and 4b and a resistor 10 is connected between the source of the FET 5 and the ground.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an MMIC (Microwave Monolithic Integrated Circuit) using a distributed constant type variable attenuator as a circuit type.
Related to t).

[0002]

2. Description of the Related Art In recent years, due to the depletion of frequency resources, high frequencies such as microwaves and millimeter waves have been used for communication purposes. An MMIC is a key component for realizing such communication using microwaves and millimeter waves. This MMIC is composed of an active element having good characteristics even at a high frequency such as a HEMT (high electron mobility transistor), a MESFET, an HBT (heterojunction bipolar transistor), or a Schottky junction diode, a transmission line, an MIM capacitor, and a resistor. The passive components thus formed are collectively formed.

One of the important circuit elements formed by using the MMIC is a variable attenuator. An important role of the variable attenuator is to function as a compensation circuit for keeping an output signal at a constant level because an amplifier or the like mounted in the same module causes a characteristic change due to a temperature change.

One of the methods for constructing such a variable attenuator is to use a three-terminal active element. FIG.
1 shows a configuration of a conventional variable attenuator using an FET. FIG.
Is a main line 1 for transmitting an RF signal from an RF signal input terminal 101 to an RF signal output terminal 102.
04a, 104b, and a variable attenuator for attenuating an RF signal by an FET 105 connected in parallel to the main lines 104a, 104b. FET10
5 is connected in parallel to the main lines 104a and 104b, the source of the FET 105 is grounded, and the voltage applied to the gate electrode terminal 103 is changed.
By controlling the impedance of the attenuator, it acts as a variable attenuator.

FIG. 9 shows a drain current-drain voltage characteristic of a FET as a representative of a three-terminal element. By using the non-saturated region of the FET, by controlling the voltage of the gate terminal, it becomes possible to operate as a variable resistor in the non-saturated region of the FET and to act as a variable attenuator.

FIG. 10 shows the relationship between the gate voltage and the attenuation of the variable attenuator. When the gate voltage is applied below the pinch-off voltage (Vg1 in the figure), the impedance of the FET looks ideally infinite, and the RF signal is not attenuated by the FET connected in parallel to the main line. When the FET is applied with a voltage sufficiently higher than the pinch-off (Vg5 in the figure), the impedance of the FET is ideally very small, and the RF signal is greatly attenuated by the FET. The FET gate voltage is set to an intermediate state (Vg2, Vg3,
In the case of Vg4), the amount of RF signal passing can be controlled by changing the impedance of the FET.

[0007]

As described above, it is possible to use three terminals represented by FETs as a variable attenuator.

However, when the FET is used as a variable attenuator as described above, the following problem may occur.

FIG. 11 shows an input voltage value (P1) at which the attenuation is reduced by 1 dB with respect to the gate voltage used for the variable attenuator.
(dB). When the input power value to the variable attenuator is increased, the FE
The resistance value indicated by T fluctuates more than when a small signal is input. In particular, the fluctuation of the resistance value indicated by the FET becomes large when a gate voltage slightly higher than the pinch-off voltage is applied. Therefore, at a specific attenuation amount indicated by a gate voltage value slightly higher than the pinch-off voltage, the attenuation amount of the set value becomes smaller than the value of the input power. As a result, the variable attenuator cannot be used above a certain input power value. Normally, when a variable attenuator is used in a specific system, the amount of attenuation is controlled at certain intervals. If the interval is wide, it can be used without being biased to the above-mentioned gate voltage value, so that no problem occurs. However, if it is necessary to take steps of the attenuation amount in many steps, the available input power amount is limited by the upper limit of the input power amount at the bias point described above.

FIG. 12 shows an example in which the amount of attenuation by the variable attenuator is controlled with a certain interval. FIG. 12A shows three control steps. In this case, since the attenuation amount indicated by the gate voltage value near the pinch-off is not used, the value of P1dB in each control step is almost constant. On the other hand, as shown in FIG. 12 (b), when the control steps are finely taken (four in the case of this figure), the variable attenuator is used in the above-mentioned region where the P1 dB decreases near the pinch-off. Will be. For this reason,
The value of P1dB in this region determines the value of the input power amount that can be handled by the entire system.

As a method of improving such a decrease in the amount of input power, it is conceivable to increase the gate width of the FET to be used and to reduce the amount of change in the resistance value of the FET with respect to a constant input power. . However, in general, when this method is applied, the maximum operating frequency that the variable attenuator can handle decreases as the maximum operating frequency of the FET decreases due to the increase in the gate width.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a semiconductor integrated circuit capable of increasing a usable input power value without increasing a gate width of a transistor used for a variable attenuator. A circuit and a system using the same.

[0013]

In order to solve the above problems, a semiconductor integrated circuit according to the present invention is provided with a first main electrode, a second main electrode, and a control electrode connected in parallel to a main line. A variable attenuator having a semiconductor element and attenuating a signal input to the main line by a control voltage applied to a control electrode of the semiconductor element, a first main electrode of the semiconductor element is connected to the main line, A resistor is connected between the second main electrode of the semiconductor element and ground.

According to the present invention, since the resistor is connected between the second main electrode of the semiconductor element and the ground, a change in impedance exhibited by the semiconductor element when the input voltage value increases is suppressed by feedback using the resistor. be able to. Therefore, the P1 of the variable attenuator is not increased without increasing the gate width of a semiconductor element such as an FET used for the variable attenuator.
The dB can be increased, which can increase the available input power value.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor integrated circuit according to the present invention and a system using the same will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a first embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in FIG. 1A is an MMIC, and an RF signal is input from an RF signal input terminal 1 to an RF signal output terminal 2.
Main lines 4a and 4b, which are transmission lines for transmitting signals, and an FET 5 connected in parallel to the main lines 4a and 4b.
And a variable attenuator for attenuating the RF signal. The main lines 4a and 4b are formed of microstrip lines and have an inductance component.

This variable attenuator includes three electrodes, a drain (corresponding to the first main electrode of the present invention), a source (corresponding to the second main electrode of the present invention), and a gate (corresponding to the control electrode of the present invention). An FET 5 having a drain connected to a connection point between the main line 4a and the main line 4b; a resistor 6 connected between the gate of the FET 5 and the gate electrode terminal 3;
, And a resistor 10 (R1) connected between the source and the ground. As the resistor 10 on the MMIC, for example, a thin film resistor or a semiconductor resistor is used.

In the variable attenuator having the above structure, the control voltage applied to the gate electrode terminal 3 is changed to
, The RF signal transmitted from the main line 4a to the main line 4b can be attenuated.

FIG. 2 is a diagram illustrating an analysis of the input power value (P1 dB) at the time of 1 dB gain compression with respect to the gate bias value when the resistance value R1 inserted into the source is changed by using simulation. By increasing the resistance value to 30Ω with respect to the conventional example (when R1 = 0Ω), P
It can be seen that the lowest value of the 1 dB value is increased by about 2.0 dB. The reason why P1dB is increased by loading the resistor is that a change in the impedance indicated by the FET when the input voltage value increases can be suppressed by the feedback of the resistor 10.

Therefore, the P1dB of the variable attenuator can be increased without increasing the gate width of the FET used for the variable attenuator. As a result, the usable input power value can be increased.

If the value of the resistor 10 is too large (for example, 500 Ω), the change of the attenuation with respect to the change of the control voltage becomes narrow, which is not preferable. For this reason, the value of the resistor 10 may be determined in consideration of the impedance characteristics of the FET 6, the amount of increase in P1dB, and the characteristics of attenuation with respect to the control voltage.

FIG. 1B shows an example in which a variable attenuator is formed using bipolar transistors. In the example shown in FIG. 1B, a bipolar transistor 7 is used instead of the FET 5 shown in FIG. The bipolar transistor 7 has three electrodes: a collector (corresponding to the first main electrode of the present invention), an emitter (corresponding to the second main electrode of the present invention), and a base (corresponding to the control electrode of the present invention). The collector is connected to a connection point between the main line 4a and the main line 4b, the base is connected to the resistor 6, and the emitter is connected to the resistor 10. Even with the variable attenuator using the bipolar transistor 7, the same effect as the variable attenuator using the FET 5 can be obtained.

(Second Embodiment) FIG. 3 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. The variable attenuator according to the second embodiment shown in FIG. 3A includes an FET 5, a resistor 11 connected to a connection point between the main lines 4a and 4b and a drain of the FET 5,
5 has a resistor 6 connected between the gate and the gate electrode terminal 3, and is configured such that the source of the FET 5 is grounded.

As described above, by loading the resistor 11 at the connection point between the main line 4a and the main line 4b and the drain of the FET 5, the decrease in P1dB can be reduced by the feedback effect of the resistor 11. Therefore, P1dB of the variable attenuator can be increased without increasing the gate width of the FET 5 used for the variable attenuator. As a result, the usable input power value can be increased.

FIG. 3B shows an example in which a variable attenuator is formed using bipolar transistors. FIG. 3 (b)
In the example shown in FIG. 3, a bipolar transistor 7 is used instead of the FET 5 shown in FIG. The bipolar transistor 7 has a collector connected to a connection point between the main line 4a and the main line 4b via a resistor 11, a base connected to the resistor 6, and an emitter grounded. Even with the variable attenuator using the bipolar transistor 7, F
The same effect as the effect of the variable attenuator using ET5 can be obtained.

(Third Embodiment) FIG. 4 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. The variable attenuator shown in FIG. 4A is characterized in that a capacitor 12 is connected in parallel with a resistor 10 to the variable attenuator shown in FIG. FIG. 4 (b)
1 is characterized in that a capacitor 12 is connected in parallel with a resistor 10 to the variable attenuator shown in FIG.

When the capacitor 12 is connected in parallel to the resistor 10 as described above, a combined impedance is obtained by connecting the resistor 10 and the capacitor 12 in parallel, and the feedback effect of the combined impedance can reduce the P1 dB reduction. it can. Therefore, FET used for variable attenuator
5 without increasing the gate width of the variable attenuator.
1 dB can be increased. As a result, the usable input power value can be increased.

(Fourth Embodiment) FIG. 5 is a block diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention. The variable attenuator shown in FIG. 5A is characterized in that a capacitor 12 is further connected in parallel with the resistor 11 to the variable attenuator shown in FIG. FIG. 5 (b)
3 is characterized in that a capacitor 12 is connected in parallel with a resistor 11 to the variable attenuator shown in FIG.

When the capacitor 12 is connected in parallel with the resistor 11, a combined impedance is obtained by connecting the resistor 11 and the capacitor 12 in parallel, and the feedback effect of the combined impedance can reduce the P1 dB reduction. it can. Therefore, FET used for variable attenuator
5 without increasing the gate width of the variable attenuator.
1 dB can be increased. As a result, the usable input power value can be increased.

(Fifth Embodiment) FIG. 6 is a block diagram of a semiconductor integrated circuit according to a fifth embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 6A is an MMIC, which is connected in series,
Three main lines 2 for transmitting an RF signal to the signal output terminal 22
4a, 24b, 24c and the main lines 24a, 24
b, 24c and each main line 24
a, 24b, 24c, three Fs connected in parallel
ET25a, 25b, 25c
A distributed constant type variable attenuator configured to attenuate a signal input to each of the main lines 24a, 24b, 24c by a control voltage applied to the gates of 5b, 25c.

In this distributed constant type variable attenuator, the drain (corresponding to the first main electrode of the present invention) has main lines 24a, 24a.
b, 24c, three FETs 25a, 25b,
25c, and resistors 26a, 26a connected between the gates of the FETs 25a, 25b, 25c and the gate electrode terminal 23.
26b, 26c, and resistors 30a, 30b, 30c connected between the sources (corresponding to the second main electrode of the present invention) of the FETs 25a, 25b, 25c and the ground. That is, the distributed constant type variable attenuator according to the fifth embodiment shown in FIG. 6 has a configuration in which the variable attenuators shown in FIG. Main lines 24a, 24b, 2
4c is formed of a microstrip line and has an inductance component. Resistors 30a and 30 on MMIC
For b and 30c, for example, a thin film resistor or a semiconductor resistor is used.

As a method of obtaining a variable attenuator operating over a wide band using an FET, there is a method using a distributed constant type circuit shown in FIG. In the distributed constant type circuit configuration, the inductance (L) of the main lines 24a to 24c, which are transmission lines, and the drain-source capacitance (Cds) of the FETs 25a to 25c (indicated by a dotted line in the figure) are connected in a distributed manner. Thus, a 50Ω pseudo transmission line of a signal source and a load is formed, and matching in a wide band is enabled. Therefore, the inductance value L and the drain-source capacitance Cds have the following relationship.

[0033]

(Equation 1) Since the number of FETs used is finite,
The pseudo transmission line has an upper limit frequency (cutoff frequency) having a certain impedance. This cutoff frequency (fc) is shown as follows.

[0034]

(Equation 2) When designing a distributed constant type variable attenuator, it is necessary to set this cutoff frequency sufficiently higher than the operating frequency. When the gate width of the FET used for the distributed constant type variable attenuator is increased by n times for the purpose of increasing P1dB, the capacitance Cds between the drain and the source also increases by n times. In order to keep it constant, the value of L needs to be n times as shown in equation (1). In this case, from (2), the cutoff frequency fc of the pseudo transmission line is also reduced to 1 / n. The problem occurs. Therefore, it is impossible to realize a wideband characteristic, which is the original intention using the distributed constant circuit configuration.

Therefore, by forming a distributed constant type variable attenuator using the present embodiment, a variable attenuator which has a constant attenuation characteristic over a wide frequency band and can be used even at a high input power is realized. can do.

The distributed constant type variable attenuator shown in FIG. 6 (b) has basically the same configuration as the distributed constant type variable attenuator shown in FIG. 6 (a), and FETs 25a, 25b, 25
The difference is that c is changed to bipolar transistors 27a, 27b and 27c. Even if such a distributed constant type variable attenuator shown in FIG. 6B is used, an effect similar to that of the distributed constant type variable attenuator shown in FIG. 6A can be obtained.

In the distributed constant variable attenuator according to the fifth embodiment shown in FIG. 6, the variable attenuators shown in FIG. 1 are connected in cascade, but, for example, the variable attenuators shown in FIG. Even if a distributed constant type variable attenuator configured by cascading multiple stages is used, the same effect as that of the distributed constant type variable attenuator of the fifth embodiment can be obtained.

FIG. 7 is a block diagram of an embodiment of a semiconductor system using a semiconductor integrated circuit according to the present invention. In the semiconductor system shown in FIG. 7A, a semiconductor integrated circuit according to the first embodiment (shown in FIG. 1A) and a control voltage to be applied to a gate electrode terminal 3 of the semiconductor integrated circuit are specified. And a voltage control unit 15 for variably controlling the voltage in a stepwise manner within the voltage variable range of
(S is a natural number) is 4 or more.

The semiconductor system shown in FIG. 7B is applied to the semiconductor integrated circuit of the second embodiment (shown in FIG. 3A) and the gate electrode terminal 3 of this semiconductor integrated circuit. A voltage control unit for variably controlling the control voltage to be controlled in a stepwise manner within a predetermined voltage variable range, wherein the number of steps s (s is a natural number) for controlling the control voltage is 4 or more. Here, the voltage variable range is the range shown in FIG.
This is a voltage range from control voltages V1 to V4 shown in FIG. The number of steps is, for example, four of V1, V2, V3, and V4.
The number of control steps for one voltage.

As described above, the variable attenuator having the circuit form of the first embodiment or the second embodiment is used for a system having a control step number s (natural number) of 4 or more. For example, in the example shown in FIG. 12B, a decrease in P1dB is observed at the control voltage V2.
Since 0 and 11 are provided, a decrease in P1dB can be suppressed. That is, it is possible to use the FET in the gate terminal voltage region where the decrease in P1dB that occurs near the pinch-off of the FET used for the variable attenuator is remarkably observed.

The present invention is not limited to the above-described variable attenuator and distributed constant type variable attenuator. In the variable attenuator of each embodiment described above, the drain of the FET is the first main electrode and the source is the second main electrode. For example, the source may be the first main electrode and the drain may be the second main electrode. good. Further, in the variable attenuator of each embodiment described above, the collector of the bipolar transistor is used as the first main electrode and the emitter is used as the second main electrode. For example, the emitter is used as the first main electrode, and the collector is used as the second main electrode. It may be an electrode.

The distributed constant type variable attenuator shown in FIG. 6 is obtained by connecting the variable attenuators shown in FIG. 1 in multiple stages. For example, the distributed attenuator shown in FIG. Even when a constant-type variable attenuator is configured, the same effect as that of the distributed constant-type variable attenuator shown in FIG. 6 can be obtained.

[0043]

As described above, according to the present invention, the P1dB of the variable attenuator can be increased without increasing the gate width of the semiconductor device used for the variable attenuator. Possible input power values can be increased. Further, it is possible to provide a distributed constant type variable attenuator having good linearity with respect to a high input power value.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a diagram illustrating a simulation example of the semiconductor integrated circuit according to the first embodiment;

FIG. 3 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a fifth embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 7 is a block diagram of an embodiment of a semiconductor system using a semiconductor integrated circuit according to the present invention.

FIG. 8 is a diagram showing a configuration of a conventional variable attenuator using an FET.

FIG. 9 is a graph showing drain current-drain voltage characteristics of an FET.

FIG. 10 is a diagram showing a relationship between a gate voltage and an attenuation of a variable attenuator.

FIG. 11 is a diagram showing a value of an input voltage value (P1 dB) in which an attenuation amount is compressed by 1 dB with respect to a gate voltage used for a variable attenuator.

FIG. 12 is a diagram showing an example in which the amount of attenuation by a variable attenuator is controlled with a certain interval.

[Explanation of symbols]

1, 21, 101 ... RF signal input terminals, 2, 22, 10
2. RF signal output terminal, 3, 23, 103 gate electrode terminal, 4a, 4b, 24a, 24b, 24c, 104
a, 104b: Main line, 5, 25a to 25c, 105 ...
FET, 6, 10, 11, 26a to 26c, 30a to 3
0c: resistance, 7: bipolar transistor, 12: capacitor, 14: semiconductor system, 15: voltage controller.

Claims (7)

[Claims] A first line connected to the main line in parallel with the first line;
A semiconductor device provided with a main electrode, a second main electrode, and a control electrode, comprising a variable attenuator for attenuating a signal input to a main line by a control voltage applied to a control electrode of the semiconductor device; Wherein the first main electrode is connected to the main line, and a resistor is connected between the second main electrode of the semiconductor element and ground. 2. The method according to claim 1, further comprising:
A semiconductor element provided with a main electrode, a second main electrode, and a control electrode, a variable attenuator for attenuating a signal input to the main line by a control voltage applied to a control electrode of the semiconductor element, A semiconductor integrated circuit, wherein a resistor is connected between a first main electrode of the element and the main line. 3. A first main electrode, a second main electrode, and a control electrode which are provided corresponding to each main line of a plurality of main lines connected in series, are connected in parallel to each main line, and are connected to each other. A distributed constant variable attenuator having a plurality of semiconductor elements provided and attenuating a signal inputted to each main line by a control voltage applied to a control electrode of each semiconductor element, wherein a first main electrode of each semiconductor element is provided; Connected to the main line, the second of each semiconductor element
A semiconductor integrated circuit, wherein a resistor is connected to a main electrode. 4. A first main electrode, a second main electrode, and a control electrode, which are provided corresponding to each main line of a plurality of main lines connected in series and are connected in parallel to each main line. A distributed constant type variable attenuator having a plurality of semiconductor elements provided and attenuating a signal input to each main line by a control voltage applied to a control electrode of each semiconductor element; and a first main electrode of each semiconductor element. A semiconductor integrated circuit, wherein a resistor is connected to the main line. 5. The semiconductor device according to claim 1, wherein the semiconductor element is a field-effect transistor, the first main electrode is a drain, and the second main electrode is a source. A semiconductor integrated circuit according to claim 1. 6. The semiconductor device according to claim 1, wherein the semiconductor element is a bipolar transistor, the first main electrode is a collector, and the second main electrode is an emitter. 2. The semiconductor integrated circuit according to claim 1. 7. The semiconductor integrated circuit according to claim 1, wherein said control voltage to be applied to a terminal of said control electrode of said semiconductor integrated circuit is set within a predetermined voltage variable range. And a voltage control means for variably controlling the control voltage, wherein the number of steps s (s is a natural number) for controlling the control voltage is 4 or more.