KR100796740B1 - Time delay phase shifter - Google Patents

Abstract

A time delay phase shifter is provided to obtain an insertion gain, to occupy a small area, and to control the phase of a broadband signal digitally. A time delay phase shifter includes a plurality of switches, elements with inductance components, and an on-off driving unit. The plurality of switches include parasitic capacitance components respectively and have input terminals and an output terminals. The elements with the inductance component play a role of a medium of connecting the input terminal of each switch to a cascade. The on-off driving unit turns on-off the plurality of switches, thereby showing an output signal through the output terminal of each switch. The parasitic capacitance component derived from each switch and the elements with the inductance components function as a part of a time delay circuit together, thereby controlling the phase of the signal digitally.

Description

Time Delay Phase Shifter

1 is a view showing the configuration of a time delay circuit according to an example of the prior art;

2 is a diagram showing the configuration of a time delay circuit according to another example of the prior art;

3 is a view for explaining a time delay phase shifter using a cascode switch according to an embodiment of the present invention;

4 is a view showing a state further provided with a load and a shock absorber to be suitable for the broadband characteristics in the time delay phase shifter shown in FIG.

5 is a view showing a state further provided with a variable gain amplifier in the time delay phase shifter shown in FIG.

6 is a diagram showing the configuration circuit of a 3-bit phase shifter as a specific example of the phase shifter according to the present invention; And

FIG. 7 is a graph illustrating a phase change and an insertion gain with respect to the frequency of the 3-bit phase shifter of FIG. 6.

Explanation of symbols on the main parts of the drawings

210: transmission line line

220: element having capacitance

301: inductor forming a distributed transmission line

302: Capacitor forming a distribution transmission line

303: inductance element between cascode switches

304: active element corresponding to parallel capacitance of distributed transmission line

305: Active device for turning on and off the cascode switch

401: load

402: shock absorber

501 variable gain adjustment amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shifter for changing a phase of a signal. In particular, a plurality of switches formed of a cascode are used, and the input terminals of the switches are connected to a cascade through an inductance element. The parasitic capacitance component and the inductance element caused by each switch form a distributed transmission line to be used as a time delay circuit, turn each switch on and off, and display an output signal through the output terminal of each switch. The present invention relates to a phase shifter that has a small area and takes up a small area and allows digitally controlling the phase of a wideband signal.

In general, a phase shifter is required for each antenna to adjust an antenna beam in a phased array antenna system, and a time delay circuit is required to change a phase of a wideband signal. Conventional time delay circuits are implemented by using the difference in length between two transmission lines caused by the operation of a PIN diode or MEMS switch or by converting the capacitance analogously by inserting the MEMS switch into the distribution transmission line circuit.

1 is a view showing the configuration of a time delay circuit according to an example of the prior art. Referring to FIG. 1, a time delay circuit is implemented by using SPDT switches at input and output sides, respectively, and using transmission line lengths in the upper part and transmission line lengths in the lower part generated by their operation. At this time, the SPDT switch has been implemented using a PIN diode or a MEMS switch. However, power dissipation issues in PIN diodes and high operating voltages and reliability issues in MEMS switches continue to be studied because of the need for improvement. As shown in Fig. 1, the difference between the transmission line lengths at the top and the bottom is Δℓ. The phase difference at this time is βΔL. Where β is the propagation constant of the transmission line. In order to change the phase of the signal up to 360 degrees, the phase shifters as shown in FIG. 1 must be cascaded bit by bit. As a result, the insertion loss generated in each switch is added to increase the insertion loss. In addition, connecting each bit in series increases the overall circuit area and phase error.

2 is a view showing the configuration of a time delay circuit according to another example of the prior art. Referring to FIG. 2, a time delay difference may be obtained by periodically connecting the elements 220 having capacitances in parallel to the transmission line line 210 to form a distributed transmission line and simultaneously changing capacitance components. As the element 220 having this capacitance, a Schottky varactor or a MEMS switch can be used, and the capacitance can be changed by adjusting the voltage. However, due to the limited range of capacitance variation with voltage, the variation in time delay difference is very small. In order to digitally change the voltage using a computer, an additional converter (DAC) is required to convert the digital signal into an analog signal.

Accordingly, the technical problem of the present invention is to provide a phase shifter which has an insertion gain and occupies a small area and can digitally control the phase of a wideband signal.

The time delay phase shifter of the present invention for solving the above technical problem is:

A plurality of switches each of which includes a parasitic capacitance component, the switch having an input terminal and an output terminal;

Elements having an inductance component, which serves as a medium for cascading the input terminals of the switches;

An on-off driving unit for turning on and off the plurality of switches to display an output signal through each of the output terminals of the plurality of switches;

And the parasitic capacitance and the inductance component due to each of the plurality of switches function together as part of a time delay circuit, thereby controlling the phase of the signal digitally.

Here, it is preferable that the plurality of switches form a cascode structure, and in this case, each of the plurality of switches is formed using any one selected from an active device group consisting of MOSFET, HEMT, MESFET, BJT, and HBT. More preferred.

In addition, a buffer or an amplifier may be further provided to pass through an output signal output through the output terminal of each switch, and for the purpose of changing the magnitude of the output signal output through the output terminal of each switch. A variable gain amplifier may be further provided.

It is also preferable to further include a buffer for additionally passing the output signal through the amplifier or the variable gain amplifier in a state in which the amplifier or the variable gain amplifier is further provided as described above.

In addition, a transmission line or an inductor may be used as an element having an inductance component, which serves as a medium for connecting the input terminals of the switches to the cascade.

And, in a high frequency digital time delay phase shifter comprising several bits, some of the several bits are:

A plurality of switches each of which includes a parasitic capacitance component, the switch having an input terminal and an output terminal;

Elements having an inductance component, which serves as a medium for cascading the input terminals of the switches;

An on-off driving unit for turning on and off the plurality of switches to display an output signal through each of the output terminals of the plurality of switches;

It is also preferred that the parasitic capacitance and the inductance component attributable to each of the plurality of switches function together as part of a time delay circuit to digitally control the phase of the signal.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

FIG. 3 is a diagram illustrating a time delay phase shifter using a cascode switch according to an embodiment of the present invention. More specifically, FIG. 3A illustrates the principle of the time delay phase shifter. FIG. 3B is a circuit diagram illustrating the time delay phase shifter. Referring to FIG. 3A, the distribution transmission line includes the inductors 301 and the capacitors 302. In the case of such a distribution transmission line, a phase difference can be obtained by extracting a signal in the direction of each upward arrow. In this case, the inductance L and the capacitance C can be expressed by Equation 1 from the characteristic impedance of the transmission line and the phase difference of each signal.

In Equation 1, Z ₀ is a characteristic impedance of a transmission line, and φ is a phase difference for each section by L and C in FIG. For example, in order to obtain a phase difference of 50? And a phase difference of 22.5 degrees at a frequency of 10 GHz, C = 0.125pF and L = 0.312nH can be obtained from Equation (1).

In Figure 3 (b), the time delay phase shifter according to an embodiment of the present invention uses a cascode switch employing an active element, such as NMOS as a component. Reference numeral 303 denotes an inductance element between cascode switches in forming a phase shifter. The reference numeral 303 may be configured using a general inductor, but may be configured using a microstrip. That is, a transmission line having a high characteristic impedance can be used as an inductor by itself, and thus can be used as part of a distribution transmission line. In particular, when a general inductor is installed on a semiconductor substrate, the use frequency is limited due to the resonance frequency of the inductor. Therefore, it may be desirable to implement an inductance device in the form of a microstrip to solve this problem. In order to extract signals in parallel from the time delay phase shifter of the present invention, a cascode switch composed of reference numerals 304 and 305 is used. Reference numeral 304 is an active device corresponding to the parallel capacitance of the distribution transmission line in the cascode switch, and reference number 305 is an active device for driving the cascode switch on and off. In the active device 304 corresponding to the parallel capacitance, the capacitance between the gate and the source of the NMOS forms the parallel capacitance of the distribution transmission line. The high frequency signal is thus transmitted along the distributed transmission line and amplified by reference numerals 304 and 305. One of the gate biases (Vg1 to VgN) of reference numeral 305 is turned ON to extract signals in parallel, and a phase shifter can be implemented by using a phase difference between the signals. Since the transistor of 304 and the inductor of 303 actually contain a resistance component, the signal is attenuated as it is transmitted along the distribution transmission line. Therefore, the magnitude of each parallel pulled signal becomes smaller as it goes backward, resulting in a difference in signal size between each state of the phase shifter. In order to solve this problem, increasing the transfer conductivity (g _m ) of each cascode switch by increasing the size of each transistor of reference numeral 305 toward the back, thereby increasing the signal amplification rate toward the back. By using this method, it is possible to minimize the size change between the states of the phase shifter.

FIG. 4 is a view illustrating a state in which a load and a buffer are further provided to be suitable for broadband characteristics in the time delay phase shifter shown in FIG. More specifically, Figure 4 (a) is a conceptual diagram of a state further provided with a load and a buffer to be suitable for the broadband characteristics in the time delay phase shifter shown in Figure 3 (b), Figure 4 (b) Is a circuit diagram including the actual configuration of such a load and a shock absorber.

When comparing (a) and (b) of FIG. 4 with (b) of FIG. 3, the difference is that in FIG. 4 (a) and (b), the output of each cascode switch of (b) of FIG. The load 401 and the buffer 402 were inserted to bundle the final high frequency output. Since the components of other parts are the same when comparing (a) and (b) of FIG. 4 with (b) of FIG. 3, the reference numerals are omitted or duplicate descriptions thereof are omitted for clarity of illustration. . Reference numeral 401 denotes a load used to obtain a wideband gain characteristic of the cascode switch output, and a combination of a resistor and an inductor may be used. Reference numeral 402 denotes a buffer for obtaining a wide bandwidth output matching characteristic and may be implemented using an active element. In (b) of FIG. 4, the load 401 is implemented to obtain a wide gain characteristic using two inductors and one resistor, and the buffer 402 is implemented in the form of a source follower to generate a wide band output. Matching was achieved.

5 is a view showing a state further provided with a variable gain control amplifier in the time delay phase shifter shown in FIG. Referring to FIG. 5, a variable gain adjustment amplifier 501 may be inserted between the load 401 and the buffer 402 to serve as a phase shifter and an attenuator. The addition of the variable gain amplifier 501 allows for further amplification and signal scaling. In addition, the shape and side lobe of the antenna beam may be adjusted by adjusting the magnitude of a signal injected into each antenna in the phased array antenna system.

6 is a view showing the configuration circuit of the 3-bit phase shifter as a specific example of the phase shifter according to the present invention. Referring to FIG. 6, a 3-bit phase shifter is implemented using eight cascode switches, and the variable gain amplifier 501 is a cascode amplifier and adjusts a gain by adjusting a gate bias A. . Inductors and transistors were sized to achieve a phase difference of 22.5 degrees at a frequency of 10 GHz.

7 (a) and 7 (b) are graphs showing the phase change and the insertion gain with respect to the frequency of the 3-bit phase shifter of FIG. 6, respectively. As shown in (a) of FIG. 7, it can be seen that the function of the time delay circuit operates normally from the phase change linearly with frequency, and the change from 15 GHz to 27.5 degrees at 10 GHz. have. In addition, (b) of FIG. 7 shows gain characteristics for frequencies for each state. Referring to this, the gain change of each state is within 0.5 dB with an insertion gain of 5 dB or more by a cascode switch and a variable gain amplifier. Able to know.

As described above, the present invention relates to a phase shifter for changing a phase of a signal, using a plurality of switches formed of a cascode, and the input terminal of each switch is connected to a cascade through an inductance element. The parasitic capacitance component and the inductance element caused by each switch are connected to each other to form a distributed transmission line to be used as a time delay circuit, turn each switch on and off, and display an output signal through the output terminal of each switch. In addition, it has the advantage of having an insertion gain, taking up a small area, and digitally controlling the phase of the wideband signal.

Claims (11)

A plurality of switches each of which includes a parasitic capacitance component, the switch having an input terminal and an output terminal; Elements having an inductance component, which serves as a medium for cascading the input terminals of the switches; An on-off driving unit for turning on and off the plurality of switches to display an output signal through each of the output terminals of the plurality of switches; And a parasitic capacitance and an inductance component attributable to each of the plurality of switches together to function as part of a time delay circuit to digitally control the phase of the signal. The time delay phase shifter of claim 1, wherein the plurality of switches form a cascode structure. 3. The time delay phase shifter of claim 2, wherein each of the plurality of switches is formed using any one selected from a group of active elements consisting of MOSFETs, HEMTs, MESFETs, BJTs, and HBTs. 3. The time delay phase shifter of claim 2, further comprising a buffer for additionally passing the output signal through the output terminal of each switch. 3. The time delay phase shifter of claim 2, further comprising an amplifier for amplifying an output signal from the output terminals of each switch. 3. The time delay phase shifter of claim 2, further comprising a variable gain amplifier for the purpose of varying the magnitude of the output signal exiting the output terminals of each switch. 6. The time delay phase shifter of claim 5, further comprising a buffer to further pass the output signal through the amplifier. 7. The time delay phase shifter of claim 6, further comprising a buffer to further pass the output signal through the variable gain amplifier. 3. The time delay phase shifter as claimed in claim 2, wherein an element having an inductance component, which serves as a medium for cascading the input terminals of the switches, is a transmission line. 3. The time delay phase shifter of claim 2, wherein an element having an inductance component acting as a medium for cascading the input terminals of each switch is an inductor. In a high frequency digital time delay phase shifter comprising several bits, some of the several bits are: A plurality of switches each of which includes a parasitic capacitance component, the switch having an input terminal and an output terminal; Elements having an inductance component, which serves as a medium for cascading the input terminals of the switches; An on-off driving unit for turning on and off the plurality of switches to display an output signal through each of the output terminals of the plurality of switches; And a parasitic capacitance resulting from each of the plurality of switches and an element having the inductance component together to function as part of a time delay circuit so as to digitally control the phase of the signal. Displacement machine.

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