JP2003297856A - Semiconductor device and semiconductor circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress frequency dispersions that HEMT elements have. <P>SOLUTION: A device comprises of first and second HEMT elements 21 and 22. The first and second HEMT elements 21 and 22 have a common channel layer 13 and a source electrode of the first HEMT element 21, and a drain electrode of the second HEMT element 22 are made to be a common source electrode 17. The source electrode 17 is grounded, and a voltage applied to the source electrode 19 of the second HEMT element 22 is set lower than that of the source electrode 17. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device using an EMT element and a semiconductor circuit using the same.

[0002]

2. Description of the Related Art First, the influence of frequency dispersion of a HEMT device on a circuit and a method of suppressing the frequency dispersion of a HEMT device proposed so far will be described. It is very important for circuit application that the transconductance and the drain conductance, which are the main parameters of the FET element, can maintain stable values regardless of the signal frequency. When frequency dispersion is observed in the above-mentioned parameters, that is, when the value varies depending on the signal frequency, various problems occur depending on the circuit type using the HEMT element. In addition, HEMT
The frequency dispersion characteristic also changes at each DC bias point of the element. This means that the waveform distortion due to the frequency dispersion characteristic occurs even when the HEMT element is operated in a large signal by CW.

By the way, when a HEMT element is used in a high-speed digital circuit, (1) increase in BER (bit error rate) due to movement of cross points depending on signal mark ratio (temporal ratio of high level in digital signal). ,
(2) There are waveform distortions (gate lag, drain lag) observed at the rising and falling edges of signals. When using a HEMT element in a general analog circuit, (3)
This is a problem in the form of gain variation, (4) increase in higher-order distortion, and the like. There are two causes of the frequency dispersion of the HEMT element, that is, the influence of the trap order inside the device and the influence of the holes generated by the impact ionization in the drain region.

As a first conventional example of the coping method, optimization of the channel layer composition (eye triple e-transaction)
Of Electron Device, Vol. 38, No. 4, 1
991, April, pp. 862 to 870). H
When the trap exists near the channel region of the EMT, frequency dispersion depending on the time constant of charge / discharge of the trap can be seen in the transconductance and the drain conductance. In used in InP-HEMT
It has been reported that the trap density existing in the GaAs channel layer is minimum when the In composition is 60%, and the frequency dispersion is most suppressed at this time.

As a second conventional example of the coping method, optimization of the recess region width (Eye Triple E Transaction of Electron Device, Vol. 45, No. 12, 1)
998, December, pp. 2390-p. 2399). When the gate-drain voltage of the HEMT device becomes high, a high electric field domain is generated on the drain side of the gate to accelerate electrons, and as a result, excessive holes are generated inside the channel due to impact ionization. If the holes do not recombine rapidly and accumulate in the source region of the HEMT element, the pseudo-Fermi level of the holes shifts toward the valence band in the source side recess region (the semiconductor region in contact with the gate in the source region), The excess holes start moving to the semiconductor surface of the recess region and accumulate on the semiconductor surface of the recess region. As a result, the channel potential increases and the electron concentration in the recess region increases. This means that the resistance of the recess region decreases and the drain current increases, which causes fluctuations in the transconductance and the drain conductance. Since the movement of excess holes from the channel to the recess surface is accompanied by a time constant, the above transconductance and drain conductance fluctuations have frequency dispersion.

To prevent this, the recess region is shortened to make it less susceptible to hole movement, and the doping amount is increased to keep the electron concentration in the recess region high from the beginning so that the resistance change in the recess portion is relatively high. It has been shown that reducing the size is effective.

As a third conventional example of the coping method, there is a compensation circuit (Japanese Patent Laid-Open No. 5-114825). When considering only the small signal region, the frequency dispersion of the drain conductance is always constant if the device structure and the DC bias condition are determined. Therefore, the influence of frequency dispersion can be compensated by providing an additional circuit between the drain and source of the HEMT element, which has a frequency dispersion opposite to the frequency dispersion of the drain conductance of the HEMT device. As the additional circuit, a circuit including a passive element including a resistor and an inductor is used. Regarding the transconductance, the influence can be reduced by providing a compensating circuit for each HEMT element.

[0008]

However, each of the conventional methods for suppressing the frequency dispersion of the HEMT device described above has the following problems. First, although the method by optimizing the channel composition is effective for an InP-HEMT device having a long channel gate with a gate length of about 0.7 μm, it has a gate length of 0.1 μ used for high-speed optical communication or a high-frequency amplifier circuit.
In the m-class high-performance InP-HEMT element, the effect of holes due to impact ionization is dominant, and a sufficient effect cannot be expected in a device actually used.

In the method of optimizing the width of the recess area, even if the recess area is shortened to a position close to the miniaturization limit of the exposure technique used for pattern formation, the influence of frequency dispersion is still observed. Further, even if the recess area width can be further narrowed by improving the exposure technique, a certain recess area width is necessary to secure the reverse DC withstand voltage between the gate and the source. The trade-off cannot be resolved. Further, the doping concentration is set to a high value close to the upper limit in a normal HEMT element, and it is technically difficult to increase the electron concentration in the recess region to a large extent as compared with the conventional HEMT element.

On the other hand, the method using the compensation circuit can be applied only when the signal is small and the signal frequency changes slowly. For example, in a circuit used for optical communication, an input signal is a large signal, and a wideband signal having various frequency components is input. In this case, it is virtually impossible to remove the frequency dispersion with a simple compensation circuit. Further, even in a high frequency amplifier, an input signal is often a large signal and is accompanied by fluctuations in the input amplitude, which limits the application of the method using a compensation circuit.

The present invention has been made in view of the above points, and an object thereof is a semiconductor device in which the frequency dispersion of transconductance and drain conductance which occurs in a high performance HEMT element with a gate length of 0.1 μm is removed. It is to provide a semiconductor circuit using the same.

[0012]

The invention according to claim 1 is composed of first and second FETs, and the source electrode of the first FET and the drain electrode of the second FET have a common terminal. In the semiconductor device, the channel layers of the first and second FETs are formed of the same layer, and the common terminal is grounded and applied to the source electrode of the second FET. The semiconductor device is characterized in that the voltage applied to the common terminal is set lower than the voltage applied to the common terminal.

According to a second aspect of the present invention, in the first aspect of the present invention, the voltage applied to the gate electrode of the second FET is the same as the voltage applied to the source electrode of the second FET and the second electrode. The semiconductor device is characterized in that it is set lower than the sum of the threshold voltage of the FET of No. 2.

The invention according to claim 3 is the invention according to claim 1 or 2.
In the invention according to the first aspect, the semiconductor device is characterized in that the DC voltage applied to the gate electrode of the first FET is set to a constant value.

The invention according to claim 4 is the invention according to claim 1 or 2.
According to another aspect of the present invention, there is provided a semiconductor circuit using the semiconductor device according to the present invention, characterized in that a separate impedance matching circuit is connected to each of the gate electrode and the drain electrode of the first FET.

The invention according to claim 5 is a semiconductor circuit using the semiconductor device according to claim 2, wherein the second source electrode is an anode electrode and the second gate electrode is a cathode electrode. With a diode connected,
The semiconductor circuit is characterized in that the voltage applied to the cathode electrode of the diode is set lower than the voltage of the source electrode of the second FET.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION [First Embodiment] FIG.
A 200 nm-thick buffer layer 12 made of InAlAs is formed on the nP substrate 11 and made of InGaAs.
3 is a cross section of the InP-HEMT element 10 of the present embodiment in which a channel layer 13 having a thickness of nm and a carrier supply layer 14 having a thickness of 15 nm made of InAlAs are formed.

A first HEMT element 21 having a first gate electrode 16 and used for a circuit, and a second HEMT element 22 having a second gate electrode 18 and functioning as an element for absorbing impact ionized holes. Are directly connected in the HEMT layer 20. Reference numeral 15 is a drain electrode, 17 is a source electrode of the first HEMT element 21, and a second HEMT.
A first source electrode which also serves as a drain electrode of the element 22, 1
Reference numeral 9 is a second source electrode. The combination of the film types and the film thicknesses of the layers 11 to 14 is possible in any film type and film thickness as long as the HEMT layer 20 can be formed.

FIG. 1 (b) is a diagram showing the potential distribution of the channel layer 13 in the cross section of FIG. 1 (a). In the present embodiment, the potential of the second source electrode 19 of the second HEMT element 22 is kept lower than that of the first source electrode 17 of the first HEMT element 21. Therefore, the potential of the valence band 36 is the first HEMT device 21.
From the first to the second HEMT element 22 is maintained so as to rise almost monotonously. Therefore, the holes 35 generated by the impact ionization in the region 34 of the first HEMT element 21 are the regions 3 that are the source of the first HEMT element 21.
It reaches the region 31 or the region 32 which is the source of the second HEMT element 22 without accumulating in 3, and eventually recombines with the electron and disappears.

When it is desired to suppress an increase in power consumption due to the drain current flowing through the second HEMT element 22,
The second gate electrode 18 needs to be kept at a potential such that a drain current does not flow in the second HEMT element 22. In the case of the present embodiment, since the threshold voltage of the second HEMT element 22 was −0.4 V, the second gate electrode 18
The voltage applied to the second source electrode 19 is 0.
Make it a voltage lower than 4V. At this time, the conduction band 37 has a higher potential in the vicinity of the second gate electrode 18 than the Fermi level 38, and the electrons 39 are depleted in this portion, so that only a small drain current flows through the second HEMT element 22. Absent. As a result, in the HEMT device 10 of this embodiment, a current substantially flows only between the first source electrode 17 and the drain electrode 15 of the first HEMT device 21,
The second HEMT element 22 has no influence on the circuit operation of the first HEMT element 21 and does not increase the power consumption of the circuit.

Since the first source electrode 17 of the first HEMT element 21 is used in a grounded state, it is terminated here in terms of high frequency. Therefore, as compared with the case where the additional circuit having the frequency dispersion opposite to the frequency dispersion of the drain conductance of the HEMT element described in the related art is provided, there is an advantage that no extra circuit is inserted in the signal path. As a result, the frequency dispersion of the first HEMT element 21 can be suppressed without causing unwanted signal attenuation or extra phase rotation due to the influence of the additional circuit.

[Second Embodiment] FIG. 2 shows H shown in FIG.
It is a circuit diagram of a differential amplifier circuit using the EMT element 10 as a HEMT element 10A for a constant current source. 41 and 42 are load resistors, 43 and 44 are differentially connected FETs, 45 and 46 are input terminals, and 47 and 48 are output terminals. Since it is for a constant current source, the first gate electrode 16 of the HEMT element 10A is
Then, the first source electrode 17 is grounded. When making the current value variable, a voltage other than the ground voltage can be applied to the gate electrode 16. The VG terminal 49 connected to the second gate electrode 18 of the HEMT element 10A and the VS terminal 50 connected to the second source electrode 19 are drawn to the outside so that a control voltage can be applied.

Here, in order to obtain the effect of improving the frequency dispersion suppression according to this embodiment, it is necessary to apply a bias voltage to the VG terminal 49 and the VS terminal 50. First, VS terminal 50
Is the source electrode 1 within a range that does not cause a problem in the breakdown voltage of the FET.
A voltage lower than the voltage of 7 is applied. Further, when it is desired to suppress power consumption, the threshold value of the above InP-HEMT is −0.
Since it is 4 V, the VG terminal 49 is connected to the VS terminal 50 by 0.
It is necessary to make the voltage lower than 4V.

In FIG. 2, the power supply voltage is VDD, the resistance values of the load resistors 41 and 42 are R, and the HEMT element 1 for constant current source is shown.
Considering the case where the current flowing through 0 A is Id and the input signal applied to the input terminals 45 and 46 is sufficiently large and the output amplitude is saturated, the output amplitudes of the output terminals 47 and 48 are “R × I”.
d ”, the center voltage of the output signal is“ VDD−0.5 × R × I
d ”. Therefore, if frequency dispersion exists in the constant current source HEMT element 10A, Id changes depending on the frequency of the signals input to the input terminals 45 and 46 and the mark ratio (temporal ratio of high level in digital signal). Thus, it can be seen that the output amplitude and the center voltage of the output signal fluctuate. However, in the present embodiment, the Id is stabilized by the effect of suppressing the frequency dispersion, so that the above variation in the output signal is not seen.

The HEMT element 10 for a constant current source shown in FIG.
The portion A is a HEMT element 10B for a constant current source shown in FIG.
Even if the form is replaced with the above form, a similar improvement effect can be obtained. Figure 3
In the first HEMT element 21 having the gate electrode 16, its source electrode 17 is grounded together with the gate electrode 16 via the capacitor 51. In this case, since the drain current also flows through the second HEMT element 22 having the gate terminal 18, the power consumption of the entire circuit increases, but
A bias circuit to be connected to the VG terminal 49 and the VS terminal 50 becomes unnecessary, and the circuit can be simplified.

[Third Embodiment] FIG. 4 shows a high-frequency power amplifier circuit according to a third embodiment of the present invention, which is a HEM of the first embodiment.
The case where a T element is used is shown. Here, a high-frequency power amplifying HEMT element 10 that constitutes a one-stage source-grounded amplifier is used.
As C, the InP-HEMT element 10 described in FIG. 1 is used. The output side of the input matching circuit 61 is connected to the gate electrode 16 of the HEMT element 10C for high frequency power amplification, and the input side of the output matching circuit 62 is connected to the drain electrode 15. By setting both the VG terminal 49 and the VS terminal 50 to the same voltage as in the second embodiment, a high frequency power amplifier with less gain variation and distortion can be obtained. Note that the circuit similar to that in FIG. 3 can be simplified also in the present embodiment.

[Fourth Embodiment] In the circuits of the second and third embodiments shown in FIGS. 2 and 4, it is necessary to apply a control voltage to two points of the VG terminal 49 and the VS terminal 50. The external control circuit becomes complicated. In order to improve this point, in the present embodiment, as shown in FIG. 5A, a diode 71 for level shifting has a source electrode 19 of the HEMT element 10A (or 10C) as its anode and a HEMT element 10A as its cathode. (Or 10 C) The diode 71 connected to the gate electrode 18 may be used, and the VC terminal 52 may be connected to the cathode of the diode 71. Further, as shown in FIG. 5 (b), a resistor 72 is attached to the cathode 71 of the diode 71.
The VC terminal 52 may be connected via. By doing so, the control terminal can be only one of the VC terminals 52. Two or more diodes 71 may be connected in series when the HEMT element has a low threshold voltage.

[0028]

As described above, according to the semiconductor device of the present invention, the frequency dispersion of the HEMT element can be suppressed, and at this time, the increase in power consumption can also be suppressed. As a result, in a semiconductor circuit such as a high-speed digital circuit using this semiconductor device, the movement of the cross point depending on the signal mark ratio and the distortion of the waveform seen at the rising and falling edges of the signal are suppressed. In the case of a semiconductor circuit using this semiconductor device for a general analog circuit,
It is possible to suppress fluctuations in gain and increase in higher-order distortion.

[Brief description of drawings]

FIG. 1A is a semiconductor device H of the first embodiment,
FIG. 3B is a cross-sectional view of the EMT element, and FIG. 6B is an explanatory diagram showing energy bands along the channel layer of FIG.

FIG. 2 is a circuit diagram of a differential amplifier circuit according to a second embodiment.

FIG. 3 is a circuit diagram showing a modified example of the differential amplifier circuit of FIG.

FIG. 4 is a circuit diagram of a differential amplifier circuit according to a third embodiment.

5A and 5B are circuit diagrams of a fourth embodiment showing modified examples of the bias circuit of the differential amplifier circuit of FIG. 2 and the high frequency power amplifier circuit of FIG.

[Explanation of symbols]

10: InP-HEMT element 11: Substrate (InP), 12: Buffer layer (InAlA
s), 13: channel layer (InGaAs), 14: carrier supply layer (InAlAs), 15: drain electrode, 1
6: first gate electrode, 17: first source electrode, 1
8: second gate electrode, 19: second source electrode, 2
0: HEMT layer, 21: first HEMT element, 22: second HEMT element 31 to 34: region, 35: hole, 36: valence band, 3
7: conduction band, 38: Fermi level, 39: electron 41, 42: load resistance, 43, 44: FET, 45, 4
6: Input terminal, 47, 48: Output terminal, 49: VG terminal, 50: VS terminal, 51: Capacitor, 52: VC terminal 10A, 10B: HEMT element for constant current source, 10C: HEMT element 61 for high frequency power amplification : Input matching circuit, 62: output matching circuit, 71: diode, 72: resistor

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takachi Enoki             2-3-1, Otemachi, Chiyoda-ku, Tokyo             Inside Telegraph and Telephone Corporation F-term (reference) 5F102 FA07 GA01 GA14 GA16 GA17                       GB01 GC01 GD01 GJ06 GK04                       GL04 GM04 GQ01

Claims (5)

[Claims] 1. A semiconductor device comprising first and second FETs, wherein a source electrode of the first FET and a drain electrode of the second FET serve as a common terminal. And the channel layer of the second FET is formed of the same layer, and the common terminal is grounded,
A semiconductor device, wherein the voltage applied to the source electrode of the second FET is set lower than the voltage of the common terminal. 2. The voltage applied to the gate electrode of the second FET is set lower than the sum of the voltage applied to the source electrode of the second FET and the threshold voltage of the second FET. The semiconductor device according to claim 1, wherein the semiconductor device comprises: 3. The semiconductor device according to claim 1, wherein the DC voltage applied to the gate electrode of the first FET is set to a constant value. 4. A semiconductor circuit using the semiconductor device according to claim 1, wherein a separate impedance matching circuit is connected to the gate electrode and the drain electrode of the first FET, respectively. Semiconductor circuit. 5. A semiconductor circuit using the semiconductor device according to claim 2, further comprising a diode in which an anode electrode is connected to the second source electrode and a cathode electrode is connected to the second gate electrode. A semiconductor circuit in which the voltage applied to the cathode electrode of the diode is set lower than the voltage of the source electrode of the second FET.