JPH0832087A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPH0832087A
JPH0832087A JP6169127A JP16912794A JPH0832087A JP H0832087 A JPH0832087 A JP H0832087A JP 6169127 A JP6169127 A JP 6169127A JP 16912794 A JP16912794 A JP 16912794A JP H0832087 A JPH0832087 A JP H0832087A
Authority
JP
Japan
Prior art keywords
integrated circuit
resistor
semiconductor layer
compound semiconductor
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6169127A
Other languages
Japanese (ja)
Inventor
Ikuo Fujiwara
郁夫 藤原
Katsue Kawahisa
克江 川久
Tomotoshi Inoue
智利 井上
Masami Nagaoka
正見 長岡
Kenji Ishida
賢二 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6169127A priority Critical patent/JPH0832087A/en
Publication of JPH0832087A publication Critical patent/JPH0832087A/en
Pending legal-status Critical Current

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  • Microwave Amplifiers (AREA)
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Abstract

PURPOSE:To make it possible to compensate the variation of a power gain due to a temperature change of an integrated circuit, without causing complexity of a circuit constitution, which is caused by adding a temperature compensating circuit or the like to the circuit constitution, and an increase in the number of elements. CONSTITUTION:As a resistive material for a resistor 14 connected with an input part of an FET 13, a metal, such as tungsten, iron and nickel, whose resistance value increases with a temperature rise of an integrated circuit, or a laminated material having a hetero-structure is used. By forming the integrated circuit into such a structure, the ratio of the amount of a current, which flows in the side of the resistor 14, is decreased with the temperature rise and the amount of a current, which is inputted in the FET 13, is increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、集積回路に係わり、特
に,温度変化による自己の電力利得の変動を補償しうる
集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to an integrated circuit capable of compensating for fluctuations in its own power gain due to temperature changes.

【0002】[0002]

【従来の技術】近年、移動通信などの分野の拡大と共に
高周波信号を増幅させる機能を有する集積回路の需要が
増大している。このような回路では、一般に増幅素子と
してGaAsMESFET等の化合物半導体FETが用
いられている。しかし、FETの電力利得は温度の上昇
と共に減少し、増幅器としての特性を劣化させる。また
回路内にこのFETの他に整合回路等を有する場合に
は、この整合回路に用いられる金属配線の抵抗値の増大
による損失もFETへの正味の入力電力の低下となっ
て、増幅器としての見かけ上の利得の低下の原因とな
る。これらの理由から温度の上昇は増幅作用を有する集
積回路の特性劣化を招く原因となる。
2. Description of the Related Art In recent years, the demand for integrated circuits having the function of amplifying high frequency signals has increased with the expansion of fields such as mobile communications. In such a circuit, a compound semiconductor FET such as GaAs MESFET is generally used as an amplification element. However, the power gain of the FET decreases as the temperature rises, deteriorating the characteristics of the amplifier. Further, when a matching circuit or the like is provided in the circuit in addition to the FET, the loss due to the increase in the resistance value of the metal wiring used in the matching circuit also results in a decrease in the net input power to the FET, and the loss as an amplifier. This causes a decrease in apparent gain. For these reasons, the rise in temperature causes the deterioration of the characteristics of the integrated circuit having the amplifying effect.

【0003】これに対し従来、図7に示すように、利得
調整用FET103、室温モニタ抵抗104、定電流供
給用FET105などを付加することにより、温度上昇
に応じてゲートバイアスを正側にシフトさせ、それによ
る相互コンダクタンスの増加を利用してFET等を起因
とする温度上昇に伴う電力利得の減少を補償するものが
ある。しかしながら、回路構成の複雑化、素子数の増加
によりチップサイズが大きくる問題があった。
On the other hand, conventionally, as shown in FIG. 7, by adding a gain adjusting FET 103, a room temperature monitor resistor 104, a constant current supplying FET 105, etc., the gate bias is shifted to the positive side according to the temperature rise. In some cases, the increase in mutual conductance is used to compensate for the decrease in power gain due to the temperature rise due to the FET or the like. However, there is a problem that the chip size becomes large due to the complicated circuit configuration and the increase in the number of elements.

【0004】一方、このFETの入力部と接地面との間
には、一般にその入力電力の一部を分割し外部に逃がす
ことによってFETの発振を防止する役割を持った安定
化抵抗が接続される。通常安定化抵抗には、半導体ドー
ピング層、ニッケルなどを用いた合金、及び酸化タンタ
ルなどの金属化合物が用いられ、一般にその抵抗値は温
度依存性の少ないものが選ばれており、室温から100
℃までの温度上昇に伴う抵抗変化は、たかだか1〜6%
の上昇率であるにすぎない。
On the other hand, a stabilizing resistor having a role of preventing oscillation of the FET is generally connected between the input portion of the FET and the ground plane so that a part of the input power is divided and released to the outside. It Usually, a semiconductor doping layer, an alloy using nickel or the like, and a metal compound such as tantalum oxide are used for the stabilizing resistance. Generally, the resistance value of which has little temperature dependency is selected, and the resistance value is from room temperature to 100%.
Resistance change with temperature rise up to ℃ is at most 1-6%
Is just the rate of increase.

【0005】[0005]

【発明が解決しようとする課題】以上述べた様に、増幅
作用を有する集積回路の電力利得の温度依存性を補償す
るためには、新たに温度補償回路等の付加が必要であ
り、それに伴う回路構成の複雑化、素子数の増加が問題
であった。本発明は、以上の点に鑑みてなされたもので
あり、簡便な形態で温度による利得変動が小さな集積回
路を提供することを目的とする。
As described above, in order to compensate the temperature dependence of the power gain of the integrated circuit having the amplifying action, it is necessary to add a temperature compensating circuit and the like. The problem is that the circuit configuration is complicated and the number of elements is increased. The present invention has been made in view of the above points, and an object of the present invention is to provide an integrated circuit in which the gain variation due to temperature is small in a simple form.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
に本発明は、入力信号を増幅させる増幅素子と、この増
幅素子の入力部と所定電位の間に配置された温度変化補
償用の抵抗体とを有する。この抵抗体を構成する抵抗材
料としては、室温から100℃までの温度上昇に対して
その抵抗値が30%以上増加するような材料を用いるこ
とが必要である。
SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an amplification element for amplifying an input signal, and a temperature change compensating resistor arranged between an input portion of the amplification element and a predetermined potential. Having a body. It is necessary to use, as the resistance material forming this resistor, a material whose resistance value increases by 30% or more with a temperature rise from room temperature to 100 ° C.

【0007】[0007]

【作用】このように構成されたものにおいては、増幅素
子の入力部と所定電位の間に配置された抵抗体の抵抗値
がその温度上昇に伴って増加し、この抵抗体に入力する
電流量が減少する。このため増幅素子に入力される電流
量が増加し、増幅素子の相互コンダクタンスの減少、金
属配線の抵抗値の上昇による損失等が補われ、温度変化
に伴う集積回路の電力利得の変動が補償される。
In this structure, the resistance value of the resistor arranged between the input part of the amplifying element and the predetermined potential increases as its temperature rises, and the amount of current input to this resistor is increased. Is reduced. Therefore, the amount of current input to the amplification element increases, the mutual conductance of the amplification element decreases, the loss due to the increase of the resistance value of the metal wiring, etc. are compensated for, and the fluctuation of the power gain of the integrated circuit due to the temperature change is compensated. It

【0008】[0008]

【実施例】以下、本発明の実施例を、図面を参照して説
明する。図1は、本発明の第1、及び第2の実施例であ
るGaHs集積回路の概略図を示す。この集積回路は入
力信号として高周波信号を予定するものである。高周波
信号は、入力端子11に入力され、入力整合回路12を
通り、増幅素子であるFET13に入力される。FET
13には、室温での最大発振周波数が35GHz、ゲー
ト幅が4mmのGaAs MESFETを用いている。
また、このFET13の入力部と接地面(0V)との間
には、抵抗体14が接続される。この抵抗体14はFE
T13の発振を防止するために、その入力電流の一部を
分割し外部に逃がす安定化抵抗としての役割も担う。最
後に、FET13からの出力信号は、出力整合回路15
を通り、出力端子16から出力される。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic view of a GaHs integrated circuit according to the first and second embodiments of the present invention. This integrated circuit is intended for high frequency signals as input signals. The high frequency signal is input to the input terminal 11, passes through the input matching circuit 12, and is input to the FET 13, which is an amplification element. FET
A GaAs MESFET having a maximum oscillation frequency of 35 GHz at room temperature and a gate width of 4 mm is used as the element 13.
A resistor 14 is connected between the input part of the FET 13 and the ground plane (0V). This resistor 14 is FE
In order to prevent the oscillation of T13, it also plays a role as a stabilizing resistor that splits a part of the input current and releases it to the outside. Finally, the output signal from the FET 13 is the output matching circuit 15
And is output from the output terminal 16.

【0009】図2は第1の実施例である集積回路に抵抗
体14として用いられる薄膜抵抗の断面図である。この
薄膜抵抗は、断面が0.01μm×2μm、長さが14
μmのピュアメタル状のニッケル薄膜抵抗で、室温での
抵抗値が約50Ω程度であり、室温から100℃間での
温度変化でおよそ4〜5割程度の抵抗値の増加が見込ま
れる。図3に、従来からの温度依存性が小さい抵抗材料
を安定化抵抗に用いた場合と本実施例の薄膜抵抗を用い
た場合での、電力利得の温度依存性を示す。図3からわ
かるように、本実施例の集積回路で得られる電力利得
は、室温で15.2dB、100℃で15.0dBと、
温度の上昇により減少することなくほぼ一定の値を示し
ている。
FIG. 2 is a sectional view of a thin film resistor used as the resistor 14 in the integrated circuit of the first embodiment. This thin film resistor has a cross section of 0.01 μm × 2 μm and a length of 14 μm.
This is a pure metal nickel thin film resistor having a thickness of μm, the resistance value at room temperature is about 50Ω, and it is expected that the resistance value will increase by about 40 to 50% by the temperature change from room temperature to 100 ° C. FIG. 3 shows the temperature dependence of the power gain when using a conventional resistance material having a small temperature dependence as a stabilizing resistance and when using the thin film resistance of this embodiment. As can be seen from FIG. 3, the power gain obtained by the integrated circuit of this embodiment is 15.2 dB at room temperature and 15.0 dB at 100 ° C.
It shows an almost constant value without decreasing as the temperature rises.

【0010】これは、次の理由による。FET13で
は、温度上昇によるゲート抵抗の増加により相互コンダ
クタンスの減少が、整合回路12、15及び伝送経路な
どを構成する金属配線の抵抗値の上昇が起こる。これら
により、集積回路の電力利得は温度の上昇と共に減少す
る。ここで、抵抗体14として、温度の上昇と共にその
抵抗値が増加するような抵抗材料を用いると、温度の上
昇に伴い抵抗体14側に流れ出す電流値の割合が減少
し、これによりFET13への入力電流値が増加する。
このため、FET13の入力電流の増加と相互コンダク
タンスの減少が相殺して、FET13の電力利得が見か
け上減少しないようになる。同様に整合回路12、15
及び配線に起因する電力損失も補われることとなる。
This is for the following reason. In the FET 13, the increase of the gate resistance due to the temperature rise causes a decrease of the mutual conductance, and the resistance values of the metal wirings forming the matching circuits 12 and 15 and the transmission path increase. These reduce the power gain of the integrated circuit with increasing temperature. Here, if a resistance material whose resistance value increases as the temperature rises is used as the resistor 14, the ratio of the current value flowing out to the resistor 14 side decreases as the temperature rises. Input current value increases.
Therefore, the increase of the input current of the FET 13 and the decrease of the mutual conductance cancel each other out, and the power gain of the FET 13 does not apparently decrease. Similarly, the matching circuits 12 and 15
Also, the power loss due to the wiring will be compensated.

【0011】以上のように、本発明を用いれば、温度補
償回路のための回路の複雑化や素子数の増加を見ること
なく、温度変化による電力利得の変動を押さえることが
できる。
As described above, according to the present invention, the fluctuation of the power gain due to the temperature change can be suppressed without observing the complication of the circuit for the temperature compensation circuit and the increase of the number of elements.

【0012】ここで、上記第1の実施例では、抵抗体1
4としてピュアメタル状のニッケル薄膜抵抗を用いた
が、本発明はこれに捕われるものではなく、室温から1
00℃の温度変化で用いられる回路に必要とされる抵抗
値の増加があれば良く、例えば、タングステン、鉄、銅
などのピュアメタルを材料とすることもできる。また、
抵抗材料はピュアメタルに限らず他の材料でも良い。更
に、所望により図4のような拡散抵抗30を用いて用い
ることもできる。この拡散抵抗30は1導電型の半導体
基板に逆導電型の不純物をイオン注入等により添加する
ことにより得られる。
Here, in the first embodiment, the resistor 1
A pure metal nickel thin-film resistor was used as No. 4, but the present invention is not limited to this, and it is possible to obtain the temperature from room temperature to 1
It suffices if there is an increase in the resistance value required for the circuit used with a temperature change of 00 ° C., for example, pure metal such as tungsten, iron, or copper can be used as the material. Also,
The resistance material is not limited to pure metal, and other materials may be used. Further, if desired, the diffused resistor 30 as shown in FIG. 4 may be used. The diffusion resistance 30 is obtained by adding an impurity of opposite conductivity type to a semiconductor substrate of one conductivity type by ion implantation or the like.

【0013】さらに、図5(a)、(b)にあるよう
に、抵抗体14として、その抵抗値の温度依存性の異な
った複数の金属が横方向(図5(a))、もしくは縦方
向(図5(b))に連続して形成されたものであれば、
それらの種類を適当に選択することにより、その抵抗値
の温度依存性を、FET13等の電力利得の温度依存性
を補償するに最適な特性に合わせ込むことができる。例
えば、回路の温度変化(20℃から100℃)に対する
利得減少が45%である場合に、この温度変化で45%
の補償を持たせる抵抗体をMo,Wを用いて形成する。
つまり、抵抗値の上昇が40%であるWをスパッタ法に
より厚さ0.01μmの膜状に形成し、CF4 等の弗素
系のガスによりRIE(リアクティブ イオン エッチ
ング)処理し縦18μm、横7μmのW膜31とする。
さらに抵抗値の上昇が50%のNi膜を厚さ0.01μ
mに堆積しレジストによりマスクしてRIE処理するこ
とで、W膜31に隣接させて縦18μm、横7μmのN
i膜32を形成する。この様な構造とすることで予定し
た45%の抵抗値上昇を持つ抵抗体14が形成される。
Further, as shown in FIGS. 5 (a) and 5 (b), as the resistor 14, a plurality of metals having different temperature dependences of their resistance values are arranged laterally (FIG. 5 (a)) or vertically. If it is formed continuously in the direction (FIG. 5 (b)),
By appropriately selecting those types, it is possible to match the temperature dependence of the resistance value with the optimum characteristics for compensating the temperature dependence of the power gain of the FET 13 or the like. For example, if the gain decrease with respect to the temperature change of the circuit (20 ° C to 100 ° C) is 45%, this temperature change causes 45%.
A resistor that gives compensation for is formed using Mo and W.
That is, W having a resistance increase of 40% is formed into a film having a thickness of 0.01 μm by a sputtering method, and is subjected to RIE (reactive ion etching) with a fluorine-based gas such as CF4, and the length is 18 μm and the width is 7 μm Of W film 31.
Furthermore, a Ni film with a resistance increase of 50% has a thickness of 0.01 μm.
By depositing on the W film 31 and masking with a resist and performing RIE, N of 18 μm in length and 7 μm in width is formed adjacent to the W film 31.
The i film 32 is formed. With such a structure, the resistor 14 having a predetermined resistance value increase of 45% is formed.

【0014】次に、図1、及び図6を用いて、本発明の
第2の実施例について説明する。本実施例においては、
図1に示す各構成要素はAu系配線からなる伝送線路で
接続され、半絶縁性GaAs基板上に形成されている。
本実施例では、抵抗体14として図6に示すような積層
構造を用い、第1の実施例と同様にFET13の発振を
防止するための安定化抵抗としての役割も担う。この積
層構造はGaAs基板41上に電子親和力の大きいアン
ド−プGaAs層42、及び電子濃度0.5〜4.0×
1018cm-3の電子親和力が小さいn型Alx Ga1-x
As層43(x〜0.3)のヘテロ構造からなる。さら
にAuGe合金からなるオ−ミック接合電極44、45
がAlx Ga1-x As層43の表面に形成される。本実
施例では、n型Alx Ga1-x As層43とGaAs層
42のヘテロ接合の界面に生じる2次元電子ガスによる
電気伝導を用いている。このような構造では、ヘテロ接
合界面の2次元電子ガス濃度は、1.0〜1.5×10
12cm-2になっており、この時、室温でのシ−ト抵抗は
600〜900Ω/□である。ここで縦横比を適切に設
定することで所望の抵抗値を与え得る。本実施例の場
合、約55Ωに設定している。
Next, a second embodiment of the present invention will be described with reference to FIGS. 1 and 6. In this embodiment,
Each component shown in FIG. 1 is connected by a transmission line composed of Au-based wiring, and is formed on a semi-insulating GaAs substrate.
In this embodiment, a laminated structure as shown in FIG. 6 is used as the resistor 14, and it also serves as a stabilizing resistor for preventing the oscillation of the FET 13 as in the first embodiment. This laminated structure has an AND-type GaAs layer 42 having a large electron affinity on a GaAs substrate 41 and an electron concentration of 0.5 to 4.0 ×.
N-type Al x Ga 1-x with a small electron affinity of 10 18 cm -3
The As layer 43 (x to 0.3) has a heterostructure. Further, ohmic contact electrodes 44, 45 made of AuGe alloy
Are formed on the surface of the Al x Ga 1-x As layer 43. In the present embodiment, electric conduction by a two-dimensional electron gas generated at the interface of the heterojunction between the n-type Al x Ga 1-x As layer 43 and the GaAs layer 42 is used. In such a structure, the two-dimensional electron gas concentration at the heterojunction interface is 1.0 to 1.5 × 10.
The sheet resistance is 12 cm -2 and the sheet resistance at room temperature is 600 to 900 Ω / □. Here, a desired resistance value can be given by appropriately setting the aspect ratio. In the case of this embodiment, it is set to about 55Ω.

【0015】この、2次元電子ガスはイオン化不純物と
分離されているため基本的にイオンが不純物散乱を受け
ない。つまりフォノン散乱が支配的であるため温度上昇
に応じて抵抗が大きく増大する。例えば室温から100
℃まで上昇すると、この電気抵抗は4割程度増大する。
この特性を利用して、安定化抵抗として用いることによ
り、温度上昇と共にグラウンド側に逃がす電力を減ら
し、FETへの入力電流値を増加させる。このようにす
ることで、FETの利得低下を見かけ上抑えることがで
きる。
Since the two-dimensional electron gas is separated from the ionized impurities, basically the ions do not undergo impurity scattering. That is, since phonon scattering is dominant, the resistance greatly increases as the temperature rises. For example, from room temperature to 100
When the temperature rises to ℃, this electric resistance increases by about 40%.
By utilizing this characteristic and using it as a stabilizing resistor, the electric power released to the ground side is reduced as the temperature rises, and the input current value to the FET is increased. By doing so, the gain reduction of the FET can be apparently suppressed.

【0016】以上の構成からなる、安定化抵抗を用い
て、図1に示す集積回路にf=1.9GHzの信号を入
力した時、室温での利得は15.1dBであった。次
に、周囲温度を100℃まで上げて新ためて計測したと
ころ、15.0dBと、ほとんど変化がなかった。
When a signal of f = 1.9 GHz was input to the integrated circuit shown in FIG. 1 by using the stabilizing resistor having the above structure, the gain at room temperature was 15.1 dB. Next, when the ambient temperature was raised to 100 ° C. and a new measurement was performed, it was 15.0 dB, which was almost unchanged.

【0017】このように本実施例で効果が得られたの
は、以下の理由による。つまり、FET13の有する増
幅特性が温度上昇にともない低下したこと、また整合回
路12、15、及び伝送線路などを構成するAu系配線
の抵抗が増大したことにより信号損失が増大したのと同
時に、FET13のゲ−ト端子に並列接続された抵抗体
14の抵抗値が増大することでFET13への入力電力
値が増大し、両者の効果が相殺したことによる。
The reason why the effect is obtained in this embodiment is as follows. That is, the signal loss is increased due to the decrease in the amplification characteristic of the FET 13 with the temperature rise and the increase in the resistance of the Au-based wirings that form the matching circuits 12 and 15 and the transmission line. This is because the resistance value of the resistor 14 connected in parallel to the gate terminal increases, the input power value to the FET 13 increases, and the effects of the both cancel each other out.

【0018】以上のように、半絶縁層の積層構造を安定
化抵抗として用いることで、簡便な構成で温度による利
得変動が小さい高周波増幅器集積回路が得られる。な
お、上記の積層構造の、ヘテロ構造としてはアンド−プ
GaAs層42とn型Alx Ga1-x As層43(x〜
0.3)の組み合わせに限らず、所望の抵抗温度係数が
得られる材料であれば良い。例えば、アンド−プ層にI
x Ga1-xAs層を用いても良く、また上記実施例の
n型Alx Ga1-x As層43もx〜0.3に限られな
い。
As described above, by using the laminated structure of the semi-insulating layers as the stabilizing resistor, it is possible to obtain a high frequency amplifier integrated circuit having a simple structure and a small gain variation due to temperature. As a heterostructure of the above-mentioned laminated structure, an and-type GaAs layer 42 and an n-type Al x Ga 1-x As layer 43 ( x to
Not limited to the combination of 0.3), any material may be used as long as it has a desired temperature coefficient of resistance. For example, the I and
An n x Ga 1-x As layer may be used, and the n-type Al x Ga 1-x As layer 43 of the above embodiment is not limited to x to 0.3.

【0019】さらに上記の積層構造に不純物が添加され
た化合物半導体層を組み合わせることも可能である。例
えば上記の積層構造に室温付近での温度係数の小さい高
不純物濃度のGaAs層を組み合わせる。これにより2
次元電子ガスによる電気伝導とこのGaAs層の電気伝
導を同程度に用い、多様な温度範囲、及び利得の温度依
存性に対応できる。
Further, it is possible to combine the above-mentioned laminated structure with a compound semiconductor layer to which an impurity is added. For example, a GaAs layer of high impurity concentration having a small temperature coefficient near room temperature is combined with the above-mentioned laminated structure. This makes 2
By using the electric conduction by the dimensional electron gas and the electric conduction of the GaAs layer to the same degree, it is possible to cope with various temperature ranges and temperature dependence of gain.

【0020】さらに上記各実施例では増幅素子としてF
ETを用いたが、入力信号としては高周波に限定するも
のではなく、周囲温度の上昇によりその利得が減少する
ような他の増幅素子にも適用可能であり、上述の効果が
同様に得られる。
Further, in each of the above-mentioned embodiments, F is used as an amplifying element.
Although the ET is used, the input signal is not limited to the high frequency, and the present invention can be applied to other amplifying elements whose gain decreases as the ambient temperature rises, and the above-mentioned effects can be obtained similarly.

【0021】[0021]

【発明の効果】本発明によれば、温度上昇による増幅素
子の利得減少、整合回路及び配線等による損失増大等に
よる集積回路の利得特性の変動を、簡便な形態で補償で
きる。
According to the present invention, fluctuations in the gain characteristics of an integrated circuit due to a decrease in gain of an amplifier element due to a temperature rise and an increase in loss due to a matching circuit and wiring can be compensated for in a simple form.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1及び第2の実施例の集積回路を説
明するための回路図。
FIG. 1 is a circuit diagram for explaining an integrated circuit according to first and second embodiments of the present invention.

【図2】本発明の第1の実施例において安定化抵抗とし
て用いた薄膜抵抗の断面図。
FIG. 2 is a sectional view of a thin film resistor used as a stabilizing resistor in the first embodiment of the present invention.

【図3】本発明の第1の実施例と従来の集積回路の電力
利得の温度依存性を示す特性図。
FIG. 3 is a characteristic diagram showing the temperature dependence of the power gain of the first embodiment of the present invention and the conventional integrated circuit.

【図4】本発明の第1の実施例において安定化低抗とし
て用いる拡散抵抗を有する抵抗の断面図。
FIG. 4 is a cross-sectional view of a resistor having a diffusion resistance used as a stabilizing resistor in the first embodiment of the present invention.

【図5】本発明の第1の実施例において安定化抵抗とし
て用いるピュアメタルの積層構造を有する抵抗の断面
図。
FIG. 5 is a sectional view of a resistor having a laminated structure of pure metal used as a stabilizing resistor in the first embodiment of the present invention.

【図6】本発明の第2の実施例において安定化抵抗とし
て用いる半絶縁層の積層構造の断面図。
FIG. 6 is a sectional view of a laminated structure of a semi-insulating layer used as a stabilizing resistor in the second embodiment of the present invention.

【図7】本発明の従来技術を説明するための回路図。FIG. 7 is a circuit diagram for explaining a conventional technique of the present invention.

【符号の説明】[Explanation of symbols]

11・・・入力端子 12・・・入力整合回路 13・・・FET 14・・・安定化抵抗 15・・・出力整合回路 16・・・出力端子 17・・・金属 18・・・金属配線 19・・・絶縁膜 30・・・拡散抵抗 31・・・金属膜A 32・・・金属膜B 11 ... Input terminal 12 ... Input matching circuit 13 ... FET 14 ... Stabilizing resistor 15 ... Output matching circuit 16 ... Output terminal 17 ... Metal 18 ... Metal wiring 19・ ・ ・ Insulating film 30 ・ ・ ・ Diffusion resistance 31 ・ ・ ・ Metal film A 32 ・ ・ ・ Metal film B

───────────────────────────────────────────────────── フロントページの続き (72)発明者 長岡 正見 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 石田 賢二 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masami Nagaoka, No. 1 Komukai Toshiba Town, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Corporate Research & Development Center, Toshiba Corporation (72) Kenji Ishida Komukai Toshiba, Kawasaki City, Kanagawa Prefecture Town No. 1 Toshiba Corporation Research & Development Center

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】入力信号を増幅させる増幅素子と、この増
幅素子の入力部と所定電位の間に配置される温度変化補
償用の抵抗体を有することを特徴とする集積回路。
1. An integrated circuit comprising: an amplifying element for amplifying an input signal; and a temperature change compensating resistor arranged between an input portion of the amplifying element and a predetermined potential.
【請求項2】前記増幅素子はFETであることを特徴と
する請求項1記載の集積回路。
2. The integrated circuit according to claim 1, wherein the amplification element is a FET.
【請求項3】前記抵抗体は、抵抗値の温度依存性の異な
る複数の金属膜を組み合わせて形成されたものであるこ
とを特徴とする請求項1記載の集積回路。
3. The integrated circuit according to claim 1, wherein the resistor is formed by combining a plurality of metal films whose resistance values have different temperature dependences.
【請求項4】前記増幅素子に入力する信号は高周波信号
であることを特徴とする請求項1記載の集積回路。
4. The integrated circuit according to claim 1, wherein the signal input to the amplifying element is a high frequency signal.
【請求項5】前記抵抗体は、n型の不純物が添加された
第1の化合物半導体層と、前記第1の化合物半導体層よ
りも電子親和力の大きい第2の化合物半導体層の積層構
造を有し、主たる電気伝導に前記第1の化合物半導体層
と前記第2の化合物半導体層の界面に生じる2次元電子
ガスを用いることを特徴とする請求項1記載の集積回
路。
5. The resistor has a laminated structure of a first compound semiconductor layer to which an n-type impurity is added and a second compound semiconductor layer having an electron affinity higher than that of the first compound semiconductor layer. 2. The integrated circuit according to claim 1, wherein a two-dimensional electron gas generated at the interface between the first compound semiconductor layer and the second compound semiconductor layer is used for main electrical conduction.
【請求項6】前記抵抗体は、前記第1の化合物半導体層
と前記第2の化合物半導体層の積層構造、及び前記第1
の化合物半導体層よりも電子親和力が大きく、n型の不
純物が添加された第3の化合物半導体層を有し、主たる
電気伝導に前記2次元電子ガス、及び第3の化合物半導
体層を用いることを特徴とする請求項1記載の集積回
路。
6. The resistor has a laminated structure of the first compound semiconductor layer and the second compound semiconductor layer, and the first compound semiconductor layer.
Of the third compound semiconductor layer having an electron affinity larger than that of the compound semiconductor layer and having an n-type impurity added, and using the two-dimensional electron gas and the third compound semiconductor layer for main electrical conduction. The integrated circuit according to claim 1, which is characterized in that:
【請求項7】入力信号を増幅させる増幅素子と、この増
幅素子の入力部と所定電位の間に配置される抵抗体とを
有し、前記抵抗体はその抵抗値が室温から100℃の温
度変化に対して少なくとも30%以上増加する抵抗材料
からなることを特徴とする集積回路。
7. An amplifying element for amplifying an input signal, and a resistor arranged between an input portion of the amplifying element and a predetermined potential, the resistor having a resistance value of room temperature to 100 ° C. An integrated circuit comprising a resistance material that increases by at least 30% or more with respect to a change.
【請求項8】前記抵抗体は、タングステン、銅、ニッケ
ルの少なくとも1つからなることを特徴とする請求項7
記載の集積回路。
8. The resistor is made of at least one of tungsten, copper and nickel.
The integrated circuit described.
JP6169127A 1994-07-21 1994-07-21 Integrated circuit Pending JPH0832087A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6169127A JPH0832087A (en) 1994-07-21 1994-07-21 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6169127A JPH0832087A (en) 1994-07-21 1994-07-21 Integrated circuit

Publications (1)

Publication Number Publication Date
JPH0832087A true JPH0832087A (en) 1996-02-02

Family

ID=15880785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6169127A Pending JPH0832087A (en) 1994-07-21 1994-07-21 Integrated circuit

Country Status (1)

Country Link
JP (1) JPH0832087A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006262348A (en) * 2005-03-18 2006-09-28 Fujitsu Ltd Semiconductor circuit
WO2007086238A1 (en) * 2006-01-27 2007-08-02 Tokyo Institute Of Technology Temperature sensor
US9800210B2 (en) 2016-01-15 2017-10-24 Mitsubishi Electric Corporation Power amplifier including a plurality of FET cells connected in parallel

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006262348A (en) * 2005-03-18 2006-09-28 Fujitsu Ltd Semiconductor circuit
WO2007086238A1 (en) * 2006-01-27 2007-08-02 Tokyo Institute Of Technology Temperature sensor
JP2009524798A (en) * 2006-01-27 2009-07-02 国立大学法人東京工業大学 Temperature sensor
US8449180B2 (en) 2006-01-27 2013-05-28 Adarsh Sandhu Temperature sensor
US9800210B2 (en) 2016-01-15 2017-10-24 Mitsubishi Electric Corporation Power amplifier including a plurality of FET cells connected in parallel

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