JP3499394B2 - Microwave integrated circuit - Google Patents
Microwave integrated circuitInfo
- Publication number
- JP3499394B2 JP3499394B2 JP04502997A JP4502997A JP3499394B2 JP 3499394 B2 JP3499394 B2 JP 3499394B2 JP 04502997 A JP04502997 A JP 04502997A JP 4502997 A JP4502997 A JP 4502997A JP 3499394 B2 JP3499394 B2 JP 3499394B2
- Authority
- JP
- Japan
- Prior art keywords
- pair
- integrated circuit
- microwave integrated
- conductive region
- ohmic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【0001】[0001]
【発明の属する技術分野】本発明は、GaAsなどの半
絶縁性半導体基板上に形成されるマイクロ波集積回路に
関する。TECHNICAL FIELD The present invention relates to a microwave integrated circuit formed on a semi-insulating semiconductor substrate such as GaAs.
【0002】[0002]
【従来の技術】近年、マイクロ波固体回路では小型化、
低価格化のために整合回路とFET等の半導体をGaA
sなどの半絶縁性半導体基板上に一体化するモノリシッ
クマイクロ波集積回路(以下、MMIC)が広く用いら
れている。2. Description of the Related Art In recent years, miniaturization of microwave solid-state circuits has
GaA semiconductors such as matching circuits and FETs for cost reduction
A monolithic microwave integrated circuit (hereinafter, MMIC) integrated on a semi-insulating semiconductor substrate such as s is widely used.
【0003】図4はGaAs FETを用いた増幅器の
一例を示す等価回路である。図において、401はGa
As FET、402〜405は整合回路を構成する伝
送回路、406、407は直流阻止用キャパシタ、41
0は安定化抵抗である。FIG. 4 is an equivalent circuit showing an example of an amplifier using a GaAs FET. In the figure, 401 is Ga
As FETs, 402 to 405 are transmission circuits forming a matching circuit, 406 and 407 are DC blocking capacitors, 41
0 is a stabilizing resistor.
【0004】 図4中の410で示す抵抗体は、FET
のゲート電極に直列に接続され、MMICに用いるFE
T401の特性ばらつきを吸収し、またFETの寄生発
振などの動作をおさえる働きがある。通常、抵抗値とし
ては接続されるFETのゲート側の入力インイーダンス
に比例し、例えば、ゲート幅に反比例して選択される。A resistor denoted by reference numeral 410 in FIG. 4 is a FET.
FE used in MMIC connected in series to the gate electrode of
It has a function of absorbing characteristic variations of T401 and suppressing operations such as parasitic oscillation of FET. Normally, the resistance value is selected in proportion to the input impedance on the gate side of the connected FET, for example, in inverse proportion to the gate width.
【0005】上記のような抵抗体を実現するには、高抵
抗金属薄膜を用いる方法、半導体の導電性領域と一対の
オーム性電極を用いて構成する方法などがあるが、FE
Tプロセスとの整合性がよいことから導電性領域と一対
のオーム性電極を用いる構成をとる場合が多い。To realize the above resistor, there are a method using a high resistance metal thin film, a method using a conductive region of a semiconductor and a pair of ohmic electrodes, and the like.
In many cases, a structure using a conductive region and a pair of ohmic electrodes is adopted because of good compatibility with the T process.
【0006】図5は導電性領域と一対のオーム性電極を
用いた構成の抵抗体の従来例を図示したものである。図
において、501aと501bは例えばAuGe/Ni
を用いた各々オーム性電極であり、一定の間隔を隔てて
対向し、一対のオーム性電極を構成している。また、図
中の502は半絶縁性の半導体基板上に選択的に形成さ
れた導電性領域である。この導電性領域は例えば半絶縁
性のGaAs基板に対してSiイオンを選択的に注入す
ることにより形成する。FIG. 5 shows a conventional example of a resistor having a structure using a conductive region and a pair of ohmic electrodes. In the figure, 501a and 501b are AuGe / Ni, for example.
, Respectively, and are opposed to each other at a constant interval to form a pair of ohmic electrodes. Reference numeral 502 in the figure denotes a conductive region selectively formed on the semi-insulating semiconductor substrate. This conductive region is formed, for example, by selectively implanting Si ions into a semi-insulating GaAs substrate.
【0007】このような構造の抵抗体により所望の抵抗
値を得るには、半導体の導電性領域の面抵抗率を変える
か、対をなすオーム性電極の間隔(抵抗体の長さ)を変
えるか、オーム性電極の対向する辺で導電性領域に重な
っている長さ(図中でB、抵抗体の幅)を変えることに
より実現できる。In order to obtain a desired resistance value with the resistor having such a structure, the surface resistivity of the conductive region of the semiconductor is changed or the interval between the ohmic electrodes forming a pair (the length of the resistor) is changed. Alternatively, it can be realized by changing the length (B in the drawing, the width of the resistor) that overlaps the conductive region on the opposite sides of the ohmic electrode.
【0008】[0008]
【発明が解決しようとする課題】近年MMICの高出力
化に伴い、FETのゲート幅が大型化し、結果として、
FETの入力および出力インピーダンスが低くなってい
る。これに対応して、安定化抵抗などの整合回路の抵抗
体に要求される抵抗値も低くなっており、例えばゲート
幅10mmのFETに対しては、一般的には5〜6Ω程
度の値が要求される。In recent years, as the output power of MMIC has increased, the gate width of FET has become larger, and as a result,
The input and output impedances of the FET are low. Correspondingly, the resistance value required for the resistor of the matching circuit such as the stabilizing resistor is also low, and for example, for an FET having a gate width of 10 mm, a value of about 5 to 6 Ω is generally set. Required.
【0009】上記の従来例の抵抗体で低い抵抗値を実現
するには、不純物濃度を上げることにより導電性領域の
面抵抗率を下げ、また、オーム性電極の電極間隔を狭
め、また、対向する辺を長くすることで低い抵抗値を実
現できる。ところが、電極間隔をあまり狭めると短絡に
より歩留まり低下を起こしたり、電圧をかけたときに高
電界になり、このことにより破壊してしまうなどの欠点
が出てくる。このため、一般的には数ミクロン程度の間
隔よりは狭くしないことが多い。In order to realize a low resistance value with the resistor of the above-mentioned conventional example, the surface resistivity of the conductive region is lowered by increasing the impurity concentration, the electrode interval of the ohmic electrodes is narrowed, and the resistance is opposite. A low resistance value can be realized by increasing the length of the side. However, if the electrode interval is made too narrow, the yield will decrease due to a short circuit, or a high electric field will be generated when a voltage is applied, and this will lead to defects such as destruction. For this reason, in general, it is often not narrower than an interval of several microns.
【0010】また、導電性領域の面抵抗率も、ある量以
上不純物濃度を増しても、抵抗率が下がらなくなる。こ
のため、より低い抵抗値が要求される場合は、オーム性
電極の対向する辺の長さBを長くすることで抵抗値を下
げている。このため、低い抵抗値を要求される高出力M
MICなどでは、高出力のためFETが大きくなるだけ
でなく、整合素子である抵抗体も大きくなり、結果的に
素子面積が非常に大きなMMICとなっている。このた
め、集積度が上がらず歩留まり低下やMMIC単価の上
昇を招く原因となっていた。Also, the surface resistivity of the conductive region does not decrease even if the impurity concentration is increased by a certain amount or more. Therefore, when a lower resistance value is required, the resistance value is lowered by increasing the length B of the opposite sides of the ohmic electrode. For this reason, a high output M that requires a low resistance value
In a MIC or the like, not only the FET is large due to the high output, but also the resistor as a matching element is large, resulting in a very large element area of the MMIC. For this reason, the degree of integration is not increased, which causes a decrease in yield and an increase in MMIC unit price.
【0011】本発明は、上記欠点を解決し、能動領域と
一対のオーム性電極より構成される抵抗体で、狭い面積
で低い抵抗値を実現できる構造の抵抗体を備えたマイク
ロ波集積回路を提供することを目的とする。The present invention solves the above-mentioned drawbacks and provides a microwave integrated circuit having a resistor having an active region and a pair of ohmic electrodes and having a structure capable of realizing a low resistance value in a small area. The purpose is to provide.
【0012】[0012]
【0013】[0013]
【0014】[0014]
【課題を解決するための手段】上記課題を解決するため
本発明は、
半絶縁性半導体基板上の所望の領域に、半導
体の導電性領域と一対のオーム性電極を配置したマイク
ロ波集積回路において、半導体の導電性領域上に渦巻状
の一対のオーム性電極を構成したことを特徴とする。 [Means for Solving the Problems] To solve the above problems
The present invention relates to a microwave integrated circuit in which a semiconductor conductive region and a pair of ohmic electrodes are arranged in a desired region on a semi-insulating semiconductor substrate, and a spiral ohmic pair is formed on the semiconductor conductive region. It is characterized in that an electrode is formed.
【0015】[0015]
【0016】[0016]
【0017】また、半絶縁性半導体基板上に電界効果ト
ランジスタを配置し、前記半絶縁性半導体基板上の所望
の領域に半導体の導電性領域と一対のオーム性電極を配
置したマイクロ波集積回路において、半導体の導電性領
域上に渦巻状の一対のオーム性電極を構成したことを特
徴とする。Further, in a microwave integrated circuit in which a field effect transistor is arranged on a semi-insulating semiconductor substrate, and a conductive region of a semiconductor and a pair of ohmic electrodes are arranged in a desired region on the semi-insulating semiconductor substrate. A pair of spiral ohmic electrodes is formed on the conductive region of the semiconductor.
【0018】また、前記半絶縁性半導体基板上に選択的
イオン注入により形成した半導体の導電性領域を用いる
ことを特徴とする。Further, a conductive region of a semiconductor formed by selective ion implantation on the semi-insulating semiconductor substrate is used.
【0019】[0019]
【0020】また、一対のオーム性電極がAuGe/N
iより成ることを特徴とする。The pair of ohmic electrodes are AuGe / N.
i.
【0021】また、一対のオーム性電極がAuGe/P
tより成ることを特徴とする。The pair of ohmic electrodes is AuGe / P.
and t.
【0022】 本発明によるマイクロ波集積回路はオー
ム性電極が交互に対向して配置された一対の電極を構成
し、例えば渦巻状の構造をしている。このため従来と同
じ面積で対向する電極長を長くできるため、低い抵抗を
狭い面積で実現できる。The microwave integrated circuit according to the present invention constitutes a pair of electrodes in which ohmic electrodes are alternately opposed to each other, and has, for example, a spiral structure. Therefore, the length of the electrodes facing each other can be increased in the same area as the conventional one, and low resistance can be realized in a small area.
【0023】[0023]
【発明の実施の形態】図1は本発明の実施の形態を示す
平面図である。図1において、101aと101bは例
えばAuGe/Niを用いた第一のオーム性電極と第二
のオーム性電極であり、一定の間隔を置いて各々櫛形で
対向し、一対のオーム性電極を構成している。また、図
中の102は半絶縁性半導体基板上に選択的に形成され
た導電性領域である。この導電性領域は、例えば半絶縁
性のGaAs基板に対してSiイオンを選択的に注入す
ることにより形成する。1 is a plan view showing an embodiment of the present invention. In FIG. 1, 101a and 101b are a first ohmic electrode and a second ohmic electrode made of, for example, AuGe / Ni, which are opposed to each other in a comb shape at regular intervals to form a pair of ohmic electrodes. is doing. Further, 102 in the figure is a conductive region selectively formed on the semi-insulating semiconductor substrate. This conductive region is formed by selectively implanting Si ions into a semi-insulating GaAs substrate, for example.
【0024】一対のオーム性電極 101aと101b
はFETのソース電極およびドレイン電極のパターンを
利用して作成することができる。このため、製造の工程
は増加せずに低い抵抗値の抵抗体を小さい面積で実現で
きる。A pair of ohmic electrodes 101a and 101b
Can be formed using the pattern of the source electrode and drain electrode of the FET. Therefore, a resistor having a low resistance value can be realized in a small area without increasing the number of manufacturing steps.
【0025】図に示すように本発明による抵抗体では一
対のオーム性電極が、各々櫛形をして対向している。こ
のため、従来例での対向する辺の長さBに相当する長さ
は、長さAに櫛形で対向している電極対の対向数n(図
中の実施例では4対)を掛けた長さA×nとなる。この
ため、例えば、5Ωの抵抗値を実現するために、従来例
の場合約3500μm2 の面積が必要であったが、本発
明によれば対向数を4対とした場合1000μm2 とな
り、面積で約70%の削減が可能となる。よって、従来
例に比べ、同じ面積で低い抵抗値を実現できる。As shown in the figure, in the resistor according to the present invention, a pair of ohmic electrodes face each other in a comb shape. Therefore, the length corresponding to the length B of the facing sides in the conventional example is obtained by multiplying the length A by the number n of facing electrode pairs facing each other in a comb shape (4 pairs in the embodiment in the drawing). The length is A × n. Therefore, for example, in order to realize a resistance value of 5Ω, an area of about 3500 μm 2 was required in the case of the conventional example, but according to the present invention, when the number of facings is 4, it becomes 1000 μm 2 , which is an area. A reduction of about 70% is possible. Therefore, a lower resistance value can be realized in the same area as compared with the conventional example.
【0026】また、本発明による他の実施の形態を図2
に示す。この場合、櫛歯型のオーム性電極の両端の電極
が図1の例よりも長くなっており、かつ、導電性領域が
櫛歯型の間隙のすべてに形成されている。このため、対
向する長さを図1の場合のA×nよりもさらに長くでき
るため、同一面積でより低い抵抗を実現できる。FIG. 2 shows another embodiment according to the present invention.
Shown in. In this case, the electrodes at both ends of the comb-teeth type ohmic electrode are longer than those in the example of FIG. 1, and the conductive regions are formed in all the comb-teeth type gaps. Therefore, the opposing length can be made longer than A × n in the case of FIG. 1, so that lower resistance can be realized in the same area.
【0027】また本発明では、同一半絶縁性半導体基板
にFETを形成しているが、説明では省略した。記載し
ていないFETは対向した櫛歯型の電極を構成すること
が多く、一対のオーム性電極101a、101bはFE
Tのソース電極およびドレイン電極のパターンを利用し
て作成することができる。このため、製造工程を増加す
ることなく狭い面積に低抵抗の抵抗体を実現することが
できる。In the present invention, the FET is formed on the same semi-insulating semiconductor substrate, but it is omitted in the description. FETs not shown often form opposing comb-teeth type electrodes, and the pair of ohmic electrodes 101a and 101b are FE.
It can be formed by utilizing the pattern of the T source electrode and the drain electrode. Therefore, it is possible to realize a resistor having a low resistance in a small area without increasing the number of manufacturing steps.
【0028】また、本発明の他の実施の形態を図3に示
した。上記の説明では一対のオーム性電極が櫛歯型の場
合について述べたが、図3に示した渦巻状であっても本
発明は実施できる。Another embodiment of the present invention is shown in FIG. In the above description, the case where the pair of ohmic electrodes are comb-teeth type has been described, but the present invention can be implemented even when the pair of ohmic electrodes has the spiral shape shown in FIG.
【0029】このように本発明によれば、同じ面積で、
従来よりも低い抵抗値を実現できるため、より集積度の
高い抵抗体を提供できる。このため、同一の機能を有す
るマイクロ波集積回路を小さな半導体基板上に実現する
ことが可能となり、製造コストを削減できる。Thus, according to the present invention, with the same area,
Since a resistance value lower than the conventional one can be realized, a resistor having a higher degree of integration can be provided. Therefore, the microwave integrated circuit having the same function can be realized on a small semiconductor substrate, and the manufacturing cost can be reduced.
【0030】なお、上記実施の形態ではオーム性電極と
してAuGe/Niを例示したが、AuGe/Ptでも
よく、また半絶縁性基板もGaAsに限らずInPでも
よいのは上記説明より明らかであり、導電性領域の形成
方法もイオン注入法に限らず本発明は実施できる。Although AuGe / Ni is used as the ohmic electrode in the above embodiment, AuGe / Pt may be used and the semi-insulating substrate may be InP instead of GaAs. The method of forming the conductive region is not limited to the ion implantation method, and the present invention can be implemented.
【0031】また、分岐した電極の枝の本数、電極の枝
の長さ、導電性領域の形状も図1、図2の形に限らない
のは上記説明から明らかである。また、渦巻の形状も図
3の形に限らない。It is apparent from the above description that the number of branched electrode branches, the length of the electrode branches, and the shape of the conductive region are not limited to those shown in FIGS. 1 and 2. Further, the shape of the spiral is not limited to the shape shown in FIG.
【0032】[0032]
【発明の効果】本発明によれば、同じ面積で低い抵抗値
を実現できるため、より集積度の高い抵抗体、より集積
度の高いマイクロ波半導体を提供できる。According to the present invention, since a low resistance value can be realized in the same area, a resistor having a higher degree of integration and a microwave semiconductor having a higher degree of integration can be provided.
【図1】本発明を説明する平面図である。FIG. 1 is a plan view illustrating the present invention.
【図2】本発明を説明する平面図である。FIG. 2 is a plan view illustrating the present invention.
【図3】本発明を説明する平面図である。FIG. 3 is a plan view illustrating the present invention.
【図4】従来例のFETを用いた増幅器の等価回路図で
ある。FIG. 4 is an equivalent circuit diagram of an amplifier using a conventional FET.
【図5】従来例を説明する平面図である。FIG. 5 is a plan view illustrating a conventional example.
101a…第一のオーム性電極 101b…第二のオーム性電極 102…導電性領域 A…長さA 201a…第一のオーム性電極 201b…第二のオーム性電極 202…導電性領域 301a…第一のオーム性電極 301b…第二のオーム性電極 302…導電性領域 401…GaAs FET 402〜405…伝送線路 406、407…直流阻止用キャパシタ 408、409…高周波短絡用キャパシタ 410…安定化抵抗 501a…第一のオーム性電極 501b…第二のオーム性電極 502…導電性領域 B…長さB 101a ... First ohmic electrode 101b ... second ohmic electrode 102 ... Conductive region A ... Length A 201a ... First ohmic electrode 201b ... second ohmic electrode 202 ... Conductive area 301a ... First ohmic electrode 301b ... second ohmic electrode 302 ... Conductive area 401 ... GaAs FET 402-405 ... Transmission line 406, 407 ... DC blocking capacitors 408, 409 ... Capacitor for high frequency short circuit 410 ... Stabilizing resistance 501a ... First ohmic electrode 501b ... Second ohmic electrode 502 ... Conductive area B ... Length B
フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 27/04 H01L 21/822 Front page continuation (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 27/04 H01L 21/822
Claims (5)
半導体の導電性領域と一対のオーム性電極を配置したマ
イクロ波集積回路において、半導体の導電性領域上に渦
巻状の一対のオーム性電極を構成したことを特徴とする
マイクロ波集積回路。1. A desired region on a semi-insulating semiconductor substrate,
In a microwave integrated circuit in which a conductive region of a semiconductor and a pair of ohmic electrodes are arranged, a vortex is formed on the conductive region of the semiconductor.
A microwave integrated circuit comprising a pair of spiral ohmic electrodes.
ジスタを配置し、前記半絶縁性半導体基板上の所望の領
域に半導体の導電性領域と一対のオーム性電極を配置し
たマイクロ波集積回路において、半導体の導電性領域上
に渦巻状の一対のオーム性電極を構成したことを特徴と
するマイクロ波集積回路。2. A field effect transistor on a semi-insulating semiconductor substrate.
In a microwave integrated circuit in which a transistor is arranged and a conductive region of a semiconductor and a pair of ohmic electrodes are arranged in a desired region on the semi-insulating semiconductor substrate, a pair of spiral ohmic layers is formed on the conductive region of the semiconductor. A microwave integrated circuit having a conductive electrode.
ン注入により形成した半導体の導電性領域を用いること
を特徴とする請求項1または請求項2記載のマイクロ波
集積回路。3. A selective ion on the semi-insulating semiconductor substrate.
Using conductive regions of the semiconductor formed by ion implantation
The microwave integrated circuit according to claim 1 or 2, wherein:
り成ることを特徴とする請求項1または請求項2記載の
マイクロ波集積回路。4. The pair of ohmic electrodes is made of AuGe / Ni.
The microwave integrated circuit according to claim 1 or 2, further comprising:
り成ることを特徴とする請求項1または請求項2記載の
マイクロ波集積回路。5. The pair of ohmic electrodes is AuGe / Pt.
The microwave integrated circuit according to claim 1 or 2, further comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04502997A JP3499394B2 (en) | 1997-02-28 | 1997-02-28 | Microwave integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04502997A JP3499394B2 (en) | 1997-02-28 | 1997-02-28 | Microwave integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10242387A JPH10242387A (en) | 1998-09-11 |
JP3499394B2 true JP3499394B2 (en) | 2004-02-23 |
Family
ID=12707919
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JP04502997A Expired - Fee Related JP3499394B2 (en) | 1997-02-28 | 1997-02-28 | Microwave integrated circuit |
Country Status (1)
Country | Link |
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JP (1) | JP3499394B2 (en) |
-
1997
- 1997-02-28 JP JP04502997A patent/JP3499394B2/en not_active Expired - Fee Related
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JPH10242387A (en) | 1998-09-11 |
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