JPH0311945Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable attenuator, and particularly to a variable attenuator that electrically varies the amount of attenuation using a transistor.

An example of the configuration of a variable attenuator using conventional transistors is shown in FIG. Input terminal 11 and output terminal 12
Two field effect transistors (hereinafter abbreviated as FET) 13 are connected in series between them, and an FET 14 is connected between the middle of these FETs 13 and the ground, and an FET 15 and a resistor are connected between the DC circuit and the high frequency circuit. The configuration is such that a DC bias is applied to the gates of FETs 13 and 14 via FET 16. No DC bias is applied to the source and drain of the FET 13. Therefore, the RF equivalent circuit of this attenuator is basically a T-connected resistance circuit as shown in FIG.
There are actually 14 parasitic capacitances 23, 24.

To increase the allowable power of this variable attenuator
It is necessary to widen the gate width of FET13. For example, if the allowable power is about 1W, the gate width of FET14 is 200μm, and the gate width of FET13 is 600μm.
Must be m. Since almost no current flows through the FET 15, a very small gate width of 25 μm is sufficient. Further, when the gate width is widened in order to increase the allowable power, the parasitic capacitance 23 increases, resulting in deterioration of frequency characteristics.

An object of the present invention is to improve the above-mentioned conventional drawbacks and to provide a variable attenuator that can obtain high allowable power by using a FET with a narrow gate width.

The variable attenuator of the present invention includes first and second field effect transistors connected in series between an input terminal and an output terminal, and connected in parallel with the first and second field effect transistors, respectively. It has two resistors and a third field effect transistor that connects between the first and second field effect transistors and a common line, and applies a voltage to the first, second, and third field effect transistors. The attenuation amount between the input terminal and the output terminal is made variable by making the DC bias variable.

Hereinafter, the present invention will be explained in detail using drawings showing embodiments.

FIG. 3 is a diagram for explaining the principle of the variable attenuator of the present invention. It is assumed that the resistors R ₁ , R ₂ and R ₃ are T-connected, the input terminal 11 is connected to the power source impedance Z ₁ and the output terminal 12 is connected to the load impedance Z ₂ . The input impedance of this variable attenuator is Z ₁ and the output impedance is Z ₂ ,
The following equation can be obtained from the conditions for impedance matching.

(R ₁ + R ₃ - Z ₁ ) (R ₂ + R ₃ + Z ₂ ) - R ² ₃ = 0...(1) (R ₁ + R ₃ + Z ₁ ) (R ₂ + R ₃ - Z ₂ ) - R ² ₃ = 0 ...(2) Let P ₁ be the input power, P ₂ be the power consumed by the load impedance Z ₂ , and let P ₂ /P ₁ = a ² ...(3) When matching is achieved on the input side, a is It is expressed by the following formula.

From these equations (1), (2) and (4), the low resistance value of the attenuator is determined relative to a, R ₃ = 2a√ _{1 2} / (1-a ² ) …(5) R ₂ +R ₃ = Z ₂ (1+a ² )/(1-a ² )...(6) R ₁ +R ₃ = Z ₁ (1+a ² )/(1-a ² )...(7). Further, if the power consumed by the resistor R ₁ is P ₁ ', the ratio to the input power is given by the following equation.

P ₁ ′/P ₁ = R ₁ /Z ₁ …(8) Now, the resistance R ₁ is a fixed resistance as shown in Figure 4.
When expressed by R _f and variable resistance R _a , R ₁ =R _f R _a /(R _f +R _a ) (9). If the power consumed by the resistor R _a is P _a , then P _a for the power P ₁ ′ consumed by these two resistors
The ratio of P _a /P ₁ '=R _f /(R _f +R _a ) is obtained, and from equation (8), the ratio of P _a to input power P ₁ can be found as shown in the following equation.

P _a /P ₁ = R _f ² R _a /Z ₁ (R _f + R _a ) ² …(10) For simplicity, power supply and load impedance Z ₁ ,
When Z ₂ is made equal and R _f =Z ₁ , and the attenuation amount L L of the attenuator is calculated as -20 loga (dB), the resistance value and power ratio are expressed as shown in FIG.

As seen in Figure 5, when the amount of attenuation L is increased, the power consumption P ₁ ' in the slave resistor R ₁ increases, and when the amount of attenuation is infinite, all of the input power P ₁ is consumed in the resistor R ₁ . . However, if R ₁ is divided into two as shown in Figure 4, the power consumed by variable resistor R _a is
It is maximum when R _a is equal to R _f , and even in this case it is 1/4 of the input power P ₁ .

FIG. 6 is a diagram showing an embodiment of the present invention, and shows only the RF circuit portion excluding the DC bias circuit. Two FET61 are connected in series, FET62 is connected between this midpoint and the common electrode, and FET6
In this configuration, a resistor 63 is connected in parallel with 1. By changing the gate bias voltages of these FETs 61 and 62, they can be operated as a variable attenuator.

Resistor 63 corresponds to resistor R _f in Figure 4, and FET6
1 corresponds to variable resistance R _a , and FET62 is the third
It is thought to correspond to resistance R ₃ in the figure. If the input/output impedance is 50 ohms and the resistor 63 is 50 ohms, in the conventional example, FET 13 corresponding to resistor R ₁
In this example, compared to the power consumed by FET
The power consumed by 61 is approximately 1/4 as shown in Figure 5.
reduced to Therefore, the gate width of FET61 is
It is also possible to make the gate width smaller than that of FET62, reducing the area occupied by the FET and
The parasitic capacitance 23 of the FET is also reduced and the frequency characteristics are improved. The resistor 63 can be made of the same semiconductor as the active layer of the FET 61, or can be made using a resistor thin film.

As mentioned above, in this embodiment, the gate width
Even if a relatively small FET of about 200 μm is used, a variable attenuator with an allowable power of about 1 W can be constructed.

Further, as shown in the above operating principle, a variable attenuator with impedance matching can be constructed even when the input impedance and output impedance are different. However, in this case, the attenuation amount L is set to zero (a=
1) cannot be done. Minimum attenuation at this time
Lmin is given by the following formula.

Lmin=−20log(√ _{2 1} −√ _{2 1} −1) In this way, when the input and output impedances are different, the two resistors 63 are set to different values Z ₁ and Z ₂
It is better to choose

According to the present invention, compared to a conventional variable attenuator, the allowable power of the variable attenuator is increased by more than four times even if elements with the same power capacity are used.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional variable attenuator, Figure 2 is a circuit diagram showing a conventional variable attenuator.
The figure is an RF equivalent circuit diagram of Figure 1, Figure 3 is a principle diagram explaining the variable attenuator according to the present invention, and Figure 4 is an equivalent circuit when resistor R ₁ in Figure 3 is replaced with two resistors. 5 is a characteristic diagram of the variable attenuator shown in FIG. 3, and FIG. 6 is a circuit diagram showing an embodiment of the present invention. 11...Input terminal, 12...Output terminal, 13,
14,15...FET, 16...Resistance, 21,2
2...FET resistance, 23, 24...parasitic capacitance,
Z ₁ ...Power supply impedance, _Z2 ...Load impedance, 61, 62...FET, 63...Resistance,
V ₁ , V ₂ ... Gate bias voltage of FET61, 62.

Claims (1)

[Scope of utility model registration request] first and second field effect transistors connected in series between the input terminal and the output terminal; two resistors connected in parallel with the first and second field effect transistors, respectively; and the first field effect transistor. and a third field effect transistor connecting between the second field effect transistors and the common line,
A variable attenuator characterized in that the amount of attenuation between the input terminal and the output terminal is made variable by making variable the DC bias applied to the first, second, and third field effect transistors.