JPS58222606A - Electronic circuit - Google Patents

Abstract

PURPOSE:To simplify the adjustment of an output impedance in an electronic circuit using a dual gate type FET chip, by applying a DC voltage to a midpoint of a series circuit comprising a resistor and a capacitor connected to the 2nd gate terminal. CONSTITUTION:The series circuit comprising a resistor 15 of resistance 5-100OMEGA and a capacitor 16 one terminal of which is grounded, is connected to the outside of the 2nd gate terminal 14 of a dual gate type FET chip having an input terminal 10, an output terminal 11, the 1st and the 2nd power supply terminals 12, 13, and the 2nd gate terminal 14. Further, a DC voltage supply source (AGC voltage or the like) 17 is connected to a connecting point between the resistor 15 and the capacitor 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic circuit including a dual-gate field effect transistor chip (hereinafter referred to as FET chip) used in high frequencies and having two gates between a pair of drains and sources.

Dual gate type FBT chips have conventionally been commercially available and used in large numbers because they have a second gate terminal as an AGC (automatic gain control) terminal and have a high gain obtained by a cascode structure.

However, the currently used dual gate FET chips have a drain terminal 1, a source terminal 2, a first gate terminal 3, and a second gate terminal 4 (these terminals are all connected to the chip as shown in Figure 1). However, the gate terminal does not include any pure resistance, and in particular, the second gate terminal 4 has the purpose of shorting with the source terminal 2 in terms of AC. Or, for the purpose of securing the gate, a diode 5 is provided as shown in Fig. 2, or
Alternatively, a structure has been adopted in which the second gate is directly short-circuited to the source or the substrate.

2nd gate) 4'ii - When using a FET chip with an external terminal, the AC terminal should be connected to the minimum possible device side of the second gate terminal of the FET to reduce parasitic inductance and other instabilities. It is necessary to short-circuit to ground point.

However, in such a circuit, a single gate type FE
Since the channel has a high resistance compared to T, Dufur) y
Due to the high output impedance, which is one of the characteristics of the ``-) type FET, the output side, when drawn as an isometric lumped constant circuit, has a high output impedance, excluding a small amount of parasitic resistance and inductance, both in terms of design and actual measurement. is mostly expressed only by the capacitance between the drain and the second gate, and in the Smith diagram used in circuit design, 822 (reflection coefficient between drain and source) is located at the outer periphery of #1 (S2221). This means that it is extremely difficult to match impedance with external circuitry without degrading gain or noise.

For example, if a pure resistor is used in the output matching circuit, it will directly result in loss, and it is extremely difficult to actually manufacture such a matching circuit, which is especially disadvantageous when the operating current is large.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic circuit that makes it possible to easily adjust the output impedance in an electronic circuit using a dual gate, FET chip.

In the electronic circuit of the present invention, when a Puar gate type FET chip having two gates between the drain and the source, both of which are electrically not common to the source, is used in the circuit, a second gate FET chip provided on the drain side is used. 5 ohm to 1 ohm external to the chip in series with the gate terminal.

It is characterized by connecting a pure resistor of approximately ohm, further connecting a capacitor that is short-circuited to the source terminal or ground potential point in an alternating current manner, and applying a DC voltage (AGC voltage, etc.) to the connection point between this resistor and the capacitor. do.

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is its circuit diagram. In the figure, the -- marks indicate external terminals, and the Φ marks indicate connection points within the chip.

The FET chip has input terminal 10. Output terminal 11. First and second power supply terminal 12 = 13% and second gate terminal 1
4, and the chip includes an input/output matching circuit, an FET element, and a coil element. A series circuit consisting of a resistor 15 of 5 to 100 ohms and a capacitor 16 whose one end is grounded is connected to the outside of the second gate terminal 14, and a direct current voltage supply source (AGC) 17 is connected therebetween. The value of the resistor 15 can be determined, for example, from numerical analysis of a lumped constant circuit as shown in Figure 4.
It is determined by the frequency to be used and the combination of each element, so it cannot be said in general, but considering the characteristics of FETs currently on the market, a resistance of a few ohms to 100 ohms is appropriate. It is.

According to this embodiment, the second gate terminal has a series circuit of a resistor and a capacitor, and the configuration is such that the AGC voltage is applied to the midpoint of the series circuit, so that the output impedance can be easily adjusted, and noise and gain can be reduced. It also does not reduce the Furthermore, the advantages of the electronic circuit according to the present invention are extremely effective in high-frequency parallel multiple switches (OR circuit type).

This means that the conventional dual gate FET chip is OFF.
At times, the output impedance becomes extremely high, which causes the impedance of the entire circuit to shift, resulting in a loss of stability. However, with the present invention, the output impedance can be easily lowered, so this can be sufficiently compensated for. can.

[Brief explanation of the drawing]

1 and 2 are conventional FET circuit diagrams, FIG. 3 is an electronic circuit diagram according to an embodiment of the present invention, and FIG. 4 is an equivalent circuit diagram thereof. 1.11...Drain terminal, 2.10...
...Source terminal, 3...First gate terminal, 4.
14... Second gate terminal, 5... Diode, 12.13... Power supply terminal, 15...
...Resistor, 16...Capacitor, 17...
...source of bias.

Claims (1)

[Claims] In an electronic circuit using a dual-gate field effect transistor that has two gates between the drain and the source, a resistive element is connected in series with the gate provided on the drain side, and the voltage is changed to the source or ground potential point. A capacitive element that is short-circuited is connected, and a gap is placed between the resistive element and the capacitive element.
An electronic circuit characterized by applying an ias.