JPS5950118U - gain control circuit - Google Patents
gain control circuitInfo
- Publication number
- JPS5950118U JPS5950118U JP14666782U JP14666782U JPS5950118U JP S5950118 U JPS5950118 U JP S5950118U JP 14666782 U JP14666782 U JP 14666782U JP 14666782 U JP14666782 U JP 14666782U JP S5950118 U JPS5950118 U JP S5950118U
- Authority
- JP
- Japan
- Prior art keywords
- gain control
- control circuit
- gain
- dual gate
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の利得制御回路、第２図は本考案の一実施
例構成図である。
１・・・入力端子、２・・・利得制御部、２−１．２−
２．２−３・・・ピンダイオード、３・・・出力端子、
４・・・バイアス用トランジスタ、５・・・利得制御電
圧端子、６・・・電源端子、１０・・・抵抗アッテネー
タ、１１・・・デュアルゲートＦＥＴ、１２・・・抵抗
アッテネータ、１３・・・バイアス用抵抗、１４・・１
バイパスコンデンサ、１５−・・チョークコイル、１６
・・・利得制御電圧端子、１７・・・電源端子。FIG. 1 is a conventional gain control circuit, and FIG. 2 is a configuration diagram of an embodiment of the present invention. 1... Input terminal, 2... Gain control section, 2-1.2-
2.2-3...Pin diode, 3...Output terminal,
4... Bias transistor, 5... Gain control voltage terminal, 6... Power supply terminal, 10... Resistance attenuator, 11... Dual gate FET, 12... Resistance attenuator, 13... Bias resistor, 14...1
Bypass capacitor, 15--Choke coil, 16
... Gain control voltage terminal, 17... Power supply terminal.
Claims (1)
にそれぞれ抵抗減衰器を接続したことを特徴とする利得
制御回路。 ２ 利得制御可能な増幅素子としてデュアルゲート電界
効果型トランジスタを使用したことを特徴とする実用新
案登録請求の範囲第１項記載の利得制御回路。[Claims for Utility Model Registration] 1. A gain control circuit characterized in that a resistive attenuator is connected to the input side and output side of an amplifying element capable of controlling gain. 2. The gain control circuit according to claim 1, which is characterized in that a dual gate field effect transistor is used as the gain controllable amplification element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14666782U JPS5950118U (en) | 1982-09-28 | 1982-09-28 | gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14666782U JPS5950118U (en) | 1982-09-28 | 1982-09-28 | gain control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5950118U true JPS5950118U (en) | 1984-04-03 |
Family
ID=30326400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14666782U Pending JPS5950118U (en) | 1982-09-28 | 1982-09-28 | gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950118U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58222606A (en) * | 1982-06-21 | 1983-12-24 | Nec Corp | Electronic circuit |
-
1982
- 1982-09-28 JP JP14666782U patent/JPS5950118U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58222606A (en) * | 1982-06-21 | 1983-12-24 | Nec Corp | Electronic circuit |
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