JPS6115817U - Mute circuit - Google Patents

Mute circuit

Info

Publication number
JPS6115817U
JPS6115817U JP9682484U JP9682484U JPS6115817U JP S6115817 U JPS6115817 U JP S6115817U JP 9682484 U JP9682484 U JP 9682484U JP 9682484 U JP9682484 U JP 9682484U JP S6115817 U JPS6115817 U JP S6115817U
Authority
JP
Japan
Prior art keywords
mute circuit
amplifier
circuit
transistor circuit
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9682484U
Other languages
Japanese (ja)
Other versions
JPH0321062Y2 (en
Inventor
喜夫 種市
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP9682484U priority Critical patent/JPS6115817U/en
Publication of JPS6115817U publication Critical patent/JPS6115817U/en
Application granted granted Critical
Publication of JPH0321062Y2 publication Critical patent/JPH0321062Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例のミュート回路、第２図は
従来のミュート回路である。 １，４，８：入力端子、２：増幅器、３：出力端子、５
，９：抵抗、６．７：トランジスタ。FIG. 1 shows a mute circuit according to an embodiment of this invention, and FIG. 2 shows a conventional mute circuit. 1, 4, 8: Input terminal, 2: Amplifier, 3: Output terminal, 5
, 9: Resistor, 6.7: Transistor.

Claims (1)

【実用新案登録請求の範囲】 増幅器の電源端子と電源との間に、直列にトランジスタ
回路を接続し、このトランジスタ回路によって前記増幅
器の増幅作用を制御させるミュート回路において、前記
トランジスタ回路はミュート時に、前記増幅器を増幅作
用がない半動作状態一 に制御することを特徴としたミュート回路。[Claims for Utility Model Registration] A mute circuit in which a transistor circuit is connected in series between a power supply terminal of an amplifier and a power supply, and the transistor circuit controls the amplification action of the amplifier, wherein the transistor circuit, when muted, A mute circuit characterized in that the amplifier is controlled to be in a half-operational state with no amplification effect.
JP9682484U 1984-06-29 1984-06-29 Mute circuit Granted JPS6115817U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9682484U JPS6115817U (en) 1984-06-29 1984-06-29 Mute circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9682484U JPS6115817U (en) 1984-06-29 1984-06-29 Mute circuit

Publications (2)

Publication Number Publication Date
JPS6115817U true JPS6115817U (en) 1986-01-29
JPH0321062Y2 JPH0321062Y2 (en) 1991-05-08

Family

ID=30656338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9682484U Granted JPS6115817U (en) 1984-06-29 1984-06-29 Mute circuit

Country Status (1)

Country Link
JP (1) JPS6115817U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115723U (en) * 1981-01-09 1982-07-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115723U (en) * 1981-01-09 1982-07-17

Also Published As

Publication number Publication date
JPH0321062Y2 (en) 1991-05-08

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