JP2661397B2 - Low-pass filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-pass filter comprising a transmission line formed on a semiconductor substrate and a variable capacitance element.

[0002]

FIG. 3 is a perspective view showing a conventional low-pass filter formed on a semiconductor substrate. In this figure, 1 is a semiconductor substrate, 2 is a ground conductor formed on the back surface of the semiconductor substrate 1, 3 is an input terminal, 4 is a microstrip line serving as an inductor component formed on the semiconductor substrate 1, and 13 is a microstrip line. The output terminal 14 is an open stub serving as a capacitance component.

Next, the operation will be described. Assuming that the inductor component of the microstrip line 4 is L and the capacitance component of the open stub 14 is C, a low-pass filter is constituted by both of them, and the characteristic impedance Z ₀ is
Equation (1) is obtained.

[0004]

(Equation 1) The cutoff frequency f _C is as shown in equation (2).

[0005]

(Equation 2)

[0006]

Since the conventional low-pass filter is configured as described above, the cutoff frequency f _C is fixed to one by the pattern, and the open stub 14 of the capacitance component C increases the capacitance value. Therefore, it is necessary to increase the width and length of the pattern, so that there is a problem that the chip size becomes large.

The present invention has been made to solve the above problems, and has as its object to obtain a low-pass filter that can change the cutoff frequency and does not need to change the chip size.

[0008]

According to the present invention, there is provided a low-pass filter according to the present invention, comprising a ground disposed on a first main surface of a semiconductor substrate.
A second conductor of the semiconductor substrate facing the first main surface;
On the main surface of the
Transmission line that constitutes the
One or more dual games arranged on two main surfaces
And a field-effect transistor disposed on the second main surface.
Dual-gate field-effect transistor with capacitor
A gate drive circuit of the star.

[0009]

According to the present invention, the second main line is arranged along the transmission line.
One or more dual-gate electric fields disposed on a surface
Effect type transistor and a capacitor disposed on the second main surface.
Of dual gate field effect transistor
The cutoff frequency is changed by changing the capacitance component using the heat driving circuit .

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing one embodiment of the low-pass filter of the present invention. 3, the same reference numerals as those in FIG. 3 denote the same components, 5 is a dual-gate FET using a capacitance as a variable element, 6 is a via hole connected to the ground conductor 2, and 7 is the first of the dual-gate FET 5. A gate electrode, 11 is also a second gate electrode, 8 is a high-resistance element for supplying gate bias, and 9 is a MIM for DC cut.
A capacitor 10 is a first gate bias power supply pad of each of the dual gate FETs 5, and 12 is a second gate bias power supply pad.

Next, the operation will be described. As described in the conventional example, the low-pass filter has a cutoff frequency f
_C is represented by the above-mentioned equation (2).

FIG. 2 shows an equivalent circuit diagram of the embodiment of FIG. 2A is an equivalent circuit diagram of the low-pass filter, FIG. 2B is an equivalent circuit diagram when both gates of the dual gate FET 5 are turned off, and FIG. 2C is a dual gate FE.
FIG. 4 is an equivalent circuit diagram when the first gate of T5 is ON and the second gate is OFF. The cutoff frequency f _C1 when the dual gate FET 5 is set in the state of FIG. 2B is expressed by the following equation (3).

[0013]

(Equation 3)

The cutoff frequency f _C2 when the dual gate FET 5 is set in the state shown in FIG. 2C is expressed by the following equation (4). However, the on-resistance R _{1O N} of the first gate is set to 0 .OMEGA.

[0015]

(Equation 4)

Therefore, two kinds of cutoff frequencies can be obtained by setting the gate bias of the dual gate FET 5.

[0017] In the above embodiment uses the Deyuarugeto FET5 as a variable capacitance element, this cash
It is also contemplated to use Ete variable capacitance diode
However, in this case, as in dual gate FET 5,
It is not a digital adjustment but an analog adjustment.

[0018]

As described above, the present invention relates to a transmission line.
One or more data disposed on the second major surface along
Dual gate field effect transistor and on the second main surface
Dual-gate field-effect type with capacitors arranged
By using a transistor gate drive circuit ,
A low-pass filter having a variable cutoff frequency can be configured. Therefore, it is not necessary to use an open stub having a large pattern area as in the conventional example.
The chip size can be reduced, and the device can be inexpensive. Also,
The effect is obtained that the cutoff frequency can be digitally adjusted .

[Brief description of the drawings]

FIG. 1 is a perspective view illustrating a low-pass filter according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a low-pass filter.

FIG. 3 is a perspective view showing a conventional low-pass filter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Ground conductor 3 Input terminal 4 Transmission line 5 Dual gate FET 6 Via hole 7 First gate electrode of dual gate FET 8 High resistance material 9 MIM capacitor 10 First gate bias power supply pad 11 Second of dual gate FET Gate 12 Second gate bias power supply pad 13 Output terminal

Claims (1)

(57) [Claims] A semiconductor substrate provided on a first main surface of the semiconductor substrate;
A ground conductor and a second semiconductor substrate facing the first main surface.
On the main surface of the
A transmission line forming a trip line; and a transmission line disposed on the second main surface along the transmission line.
One or more dual-gate field-effect transistors
And a capacitor disposed on the second main surface and having a capacitor.
Gate drive circuit of dual gate field effect transistor
Road and low pass filter with.