JP2873123B2 - Microwave frequency multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave frequency multiplying circuit for multiplying and outputting an input signal.

[0002]

2. Description of the Related Art FIG. 9 is a circuit diagram of a conventional balanced microwave frequency multiplier. The frequency multiplier of this conventional example can be roughly divided into a 180-degree hybrid circuit 30 that divides an input signal into two signals having the same amplitude and opposite phase, and outputs the two signals; Utilizing an area where the relationship between the gate-source electrode voltage and the drain current is non-linear, the input signal is frequency-converted into a signal having a fundamental signal component of the signal and a harmonic component whose frequency is multiplied. Frequency multiplier circuits 31 and 32 having the same circuit configuration and outputting
It comprises a Y-type power combiner 33 that combines two signals output from each of the frequency multiplier circuits 31 and 32 in phase and outputs the combined signal.

[0003] The 180-degree hybrid circuit 30 is 1/4.
Wavelength microwave lines 34, 35, 36, 37 and 38
And a terminating resistor 39 having an impedance Z ₀ . Each of the microwave lines 34 and 38 forms a directional coupling circuit having one end grounded, and operates as a phase inversion circuit. Therefore, the signal input from the input terminal 10 is distributed by the 180-degree hybrid circuit 30 into two signals having the same amplitude and opposite phase, and one of the signals is frequency-multiplied via the terminal 30c. While being output to the circuit 31, the other signal is output to the frequency multiplier 32 via the terminal 30d.

The frequency multiplying circuit 31 includes an input matching circuit 21
, A capacitor 41, a bias resistor 42, a source-grounded field effect transistor 11, and an output matching circuit 22. The input matching circuit 21 provided in the frequency multiplication circuit 31 is a terminal 30c of the 180-degree hybrid circuit 30.
And the gate electrode 11g of the field-effect transistor 11 having a common source. The output matching circuit 22 includes a drain electrode 11d of the field-effect transistor 11 having a common source and a terminal 33 of the Y-type power combiner
and impedance matching between the two.

The frequency multiplying circuit 32 is composed of the input matching circuit 21
, A capacitor 41, a bias resistor 42, a source-grounded field effect transistor 11, and an output matching circuit 22.

In order to operate the field effect transistors 11 in the frequency multipliers 31 and 32 in a frequency multiplied state, it is necessary to apply an appropriate bias voltage to each gate electrode 11g. The gate electrode 11g is biased from the terminal 43 via the DC bias resistor 42 so as to have a non-linear region having a second-order component where the relationship between the gate-source electrode voltage and the drain current is the largest. When a fundamental signal voltage is applied between the gate and source electrodes of the field effect transistor 11 and the combined voltage of the fundamental signal voltage and the bias voltage is larger than the pinch-off voltage,
The drain current flows quadratically with respect to the gate-source voltage. Therefore, the drain current has a fundamental signal component of the input signal and a second harmonic component whose frequency is doubled with respect to the signal. Therefore, a drain current having a fundamental signal component and a second harmonic component is output to the terminals 33a and 33b of the Y-type power combiner 33. On the other hand, when a fundamental wave signal voltage is applied between the gate and source electrodes of the field effect transistor 11 and the combined voltage of the fundamental wave signal voltage and the bias voltage is smaller than the pinch-off voltage, the drain current Is shut off.

As described above, the frequency multipliers 31 and 3
2, two signals output from the 180-degree hybrid circuit 30 and having the same amplitude and opposite phase with each other are input. The two signals are frequency-converted by the field-effect transistors 11 in the frequency multipliers 31 and 32 into a signal having a fundamental frequency signal component and a second harmonic component having a double frequency, and are output. You.
Here, each second harmonic component having twice the frequency is represented by the quadratic function of the gate-source electrode voltage and the drain current.
Since they are output as the next term, they have the same amplitude and phase relationship. The Y-type power combiner 33 includes the frequency multiplying circuit 31
And 32 are in-phase synthesized. As a result, the second harmonic components of the two signals are emphasized and combined with each other, and output from the output line 13.

On the other hand, the fundamental wave signal components of the two signals are output as first-order terms of a quadratic function expression of a gate-source electrode voltage and a drain current, and thus have the same amplitude and antiphase relationship. . Therefore, the Y-type power combiner 33
In the above, 2 output from the frequency multiplier circuits 31 and 32
When the two signals are combined in phase, the fundamental signal components of the two signals cancel each other out and are not output to the output line 13. Thereby, the leakage suppression performance of the fundamental wave signal is established.

[0009]

However, in the above-mentioned conventional balanced-type microwave frequency multiplier, each microwave line used for the input matching circuit 21 and the output matching circuit 22 and the 180-degree hybrid 30 are formed. Microwave lines 34, 35, 36, 37 and 38
Further, the length of each of the microwave lines 33c and 33d constituting the Y-type power combiner 33 depends on the wavelength of the signal frequency transmitted to the microwave line, and when the signal frequency is low, The microwave line causes a disadvantage that the area of the circuit is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microwave frequency multiplying circuit having a circuit area that does not depend on the wavelength of a signal and is smaller than a conventional example.

[0011]

A microwave frequency multiplying circuit according to the present invention is a microwave frequency multiplying circuit for multiplying the frequency of a signal input to an input line and outputting the same to an output line, wherein a source electrode is provided. A grounded-gate field-effect transistor connected to the input line, and two drain-grounded field-effect transistors having a common drain electrode and a source electrode, and one of the field-effect transistors has a gate electrode connected to the grounded gate. The first and second gates are connected to the drain electrode of the field effect transistor, the gate electrode of the other field effect transistor is connected to the gate electrode of the grounded field effect transistor, and the source electrode is connected to the output line. And the first and second grounded electric fields. A first slot line is constituted by two gate electrodes of the transistor, a second slot line is constituted by a gate electrode of the first grounded field effect transistor and the shared drain electrode, and a gate of the second grounded drain transistor is formed. A third slot line having the same width as the second slot line is formed by the electrode and the common drain electrode, and the signals transmitted through the first slot line are inverted by the first to third slot lines with the same amplitude. It is characterized in that it constitutes a branch circuit for distributing two signals having a phase relationship and outputting the signals to the second slot line and the third slot line.

[0012]

In the microwave frequency multiplying circuit according to the present invention, the gate-grounded field effect transistor having the source electrode connected to the input line performs impedance matching between the input line and the source electrode by its impedance matching action. The first and second drain-grounded field-effect transistors constitute first to third slot lines by respective electrodes, and two signals having the same amplitude and opposite phase with respect to each other are transmitted through the first slot line. A branch circuit for distributing the signal to output to the second and third slot lines is configured. The first and second grounded field-effect transistors receive two signals of the same amplitude and opposite phases output to the second and third slot lines, respectively, via a gate electrode, and receive the two received signals. Each region is frequency-converted using a region where the relationship between the gate-source electrode voltage and the drain current is non-linear, and is subjected to in-phase synthesis at a common source electrode, and then output to an output line connected to the source electrode. . Further, the first and second grounded field effect transistors perform impedance matching between the source electrode and the output line by the impedance matching action.

[0013]

【Example】

First Embodiment FIG. 1 is a diagram showing a balanced microwave frequency multiplier according to a first embodiment of the present invention. This circuit includes a grounded field effect transistor 112 instead of the input matching circuit 2 of the conventional example, and a 180-degree hybrid circuit 3
0, a branch circuit of a slot line is provided, and frequency multiplier circuits 31 and 32 and an output matching circuit 22 therein are provided.
And a hybrid integrated circuit including, in place of the Y-type power combiner 33, two grounded field effect transistors 121 and 122 having respective source electrodes connected to each other.

The above-mentioned balanced microwave frequency multiplier is constituted as follows. On the dielectric substrate 101, a first conductor 113, a second conductor 114, and a third conductor 130 are formed. A strip-shaped fourth conductor 105 is formed on the back surface of the dielectric substrate 101 so as to face the first conductor 113 serving as a ground conductor, and a strip-shaped fourth conductor 105 is provided facing the third conductor 130 serving as a ground conductor. A fifth conductor 107 having a shape is formed. The fourth conductor 10
5 and the first conductor 113 of the ground conductor constitute a microstrip line 150 which is an input line having a characteristic impedance Z ₀ . Similarly, the fifth conductor 107 and the third conductor 130 as a ground conductor constitute a microstrip line 151 which is an output line having a characteristic impedance Z ₀ .

One end of the fourth conductor 105 is connected to the dielectric substrate 1
01 through the inner conductor formed in the through hole 106 penetrating the first field effect transistor 11 in the thickness direction.
2 is connected to the second source electrode 112s. Similarly, one end of the fifth conductor 107 is connected to the source of the second and third field effect transistors 121 and 122 via an inner conductor formed in a through hole 108 penetrating the dielectric substrate 101 in the thickness direction. The electrodes 121s and 122s are connected to a conductor 143 that connects the electrodes to each other. The gate electrode 112g of the first field-effect transistor 112 is connected to the first conductor 11
3 and its drain electrode 112 d is connected to the second conductor 114. Here, the first conductor 113 and the second conductor 114 are formed at a predetermined distance from each other to form a slot line 115. First conductor 1
Reference numeral 13 is connected to one end of an inductance 120 at a high frequency from a position to which the gate electrode 112g is connected, via a DC bias cut capacitance 118 formed at the right edge in the drawing. The second conductor 114 is connected at a high frequency to one end of an inductance 119 from a position where the drain electrode 112d is connected, via a DC bias cut capacitance 117 formed at the right edge in the drawing.

Further, the inductances 119 and 120
Are connected to conductors 140 and 141 formed on the dielectric substrate 101, respectively. Conductors 140 and 1
Reference numeral 41 denotes gate electrodes 121g and 122 of the second and third field-effect transistors 121 and 122, respectively.
g is connected. Each of the drain electrodes 121d and 1d of the second and third field effect transistors 121 and 122
22d is a conductor 142 formed on the dielectric substrate 101
Are connected at the same distance. The conductor 142
A high frequency connection to the third conductor 130 via a jumper wire 126 and a DC bias cut capacitance 123 and a third conductor 130 via a jumper wire 127 and a DC bias cut capacitance 124.
Is connected at high frequency and grounded.

As shown in the enlarged view of FIG.
0 and the conductor 141 are formed apart from each other by a predetermined distance to form the slot line 160. Also, the conductor 140
The conductor 142 and the conductor 142 are formed at a predetermined distance from each other to form a slot line 161. Furthermore, conductor 1
41 and the conductor 142 are formed apart from each other by the same width as the slot line 161 to form the slot line 162. Here, the slot line 160 and the slot lines 161 and 162 divide the signal transmitted to the slot line 160 into two signals having the same amplitude and opposite phase, and output the two signals to the slot lines 161 and 162. Configure a branch circuit.

The gate electrode 121g is connected to the third conductor 130, which is a ground conductor, via the conductor 140 and the resistor 132, so that a zero bias voltage is applied to the gate electrode 12g.
Applied to 1 g. Further, the gate electrode 122g is connected to the third conductor 130, which is a ground conductor, via the conductor 141 and the resistor 133, whereby a zero bias voltage is applied to the gate electrode 122g. The drain bias voltages of the first, second, and third field effect transistors 112, 121, and 122 are applied via a jumper line 128. The drain bias voltage of the first field-effect transistor 112 is such that the current of the drain electrode 112d is equal to the gate voltage.
The signal is superimposed on the input AC signal in the conductor 114 and applied so as to change in a linear region in relation to the voltage between the source electrodes. Further, the source bias voltage of the second and third field effect transistors 121 and 122 is such that the current of the drain electrodes 121d and 122d connected to each other of the field effect transistors 121 and 122 is large in relation to the gate-source electrode voltage. The signal is superimposed on the output AC signal of the fifth conductor 107 so as to change in a nonlinear region having only the second-order component.

FIG. 3 is a diagram showing an equivalent circuit of the balanced microwave frequency multiplier of the first embodiment. The input signal has a characteristic impedance Z ₀ constituted by the fourth conductor 105 and the first conductor 113 which is a ground conductor.
Is input to the first grounded gate field effect transistor 112 via the microstrip line 150, and the slot line 115 and the capacitances 117 and 118
, And second and third field effect transistors 121 and 1 via inductances 119 and 120 and a branch circuit.
22 are applied to the gate electrodes 121g and 122g.
Here, the impedance of the source electrode 112s of the first field-effect transistor 112 can be matched to the characteristic impedance Z ₀ of the microstrip line 150 as an input line by the impedance matching function of the first field-effect transistor 112. . The inductances 119 and 120 are the same as those of the field effect transistor 1.
It has a role to correct the deterioration of the high frequency characteristic due to the capacitance component of the capacitor parasitic on 12, 121 and 122 and to widen the frequency characteristic. Specifically, the inductance 11
9, 120 are the parasitic capacitance between each drain and gate electrode of the field effect transistors 112, 121 and 122 and LC
A low-pass filter is formed, and the LC low-pass filter realizes a wide band of the frequency of the multiplying operation, that is, realizes a flat characteristic in a desired frequency band.

The slot lines 160, 161 and 16
The branch circuit composed of 2 is represented in the equivalent circuit diagram shown in FIG. 3 by a transformer having two coils of equal inductance connected in series on the secondary side. The input signal input to the slot line 160 is divided into two signals having the same amplitude and opposite phase by a transformer, which is a branch circuit, and then the signals are respectively divided into the slot line 161 and the slot line 16.
2 is output. These two signals are converted by the second and third field effect transistors 121 and 122 into a fundamental signal component of the input signal and its fundamental signal using a region where the relationship between the gate-source electrode voltage and the drain current is non-linear. The frequency is converted into a signal having a harmonic component whose frequency is multiplied, and is output to the source electrodes 121 s and 122 s connected to each other by the conductor 143. Further, the source electrodes 121s of the second and third field effect transistors 121 and 122 are formed by the impedance matching function of the second and third field effect transistors 121 and 122.
, And 122 s can be matched to the characteristic impedance Z ₀ of the microstrip line 151 that is the output line.

The two signals output to each of the source electrodes 121s and 122s are
Since s are connected to the fifth conductor 107 at equal distances by the conductors 143, they are combined in phase. Here, the fundamental signal component and the third harmonic component of the two signals are output as the first and third order terms of the quadratic function equation of the gate-source electrode voltage and the drain current, respectively. The signal components have amplitude opposite phases, and these signal components are combined and cancel each other, and are not output to the microstrip line 151 which is the output line.

Each second harmonic component having twice the frequency of the above two signals is output as a second order term of a quadratic function expression of a gate-source electrode voltage and a drain current. The second harmonic components having the same amplitude and the same phase are output, these components are combined in the same phase, emphasize each other, and output via the microstrip line 151.

As described above, the source bias voltages of the second and third field effect transistors 121 and 122 have a non-linear relationship having only a secondary component in which the relationship between each drain current and the voltage between the gate and source electrodes is large. Therefore, the fourth-order and higher harmonic components are negligibly small. As a result, only the signal having the second harmonic component is transmitted from the second and third field-effect transistors 121 and 122 to the microstrip line 1.
It is output via 51.

Second Embodiment FIG. 4 shows an MMIC-type microwave frequency multiplier according to a second embodiment of the present invention. This circuit includes a field-effect transistor 212 having a grounded gate in place of the input matching circuit 21 of the conventional example, a branch circuit formed of a slot line in place of the 180-degree hybrid circuit 30, and frequency multiplier circuits 31 and 32. And its internal output matching circuit 2
In place of the 2 and Y type power combiners 33, there are provided two drain-grounded field effect transistors 221 and 222 having respective source electrodes connected to each other, and on the semiconductor substrate 202 using a semiconductor integrated circuit manufacturing technique. It is characterized by being formed integrally and integrally.

The MMIC type microwave frequency multiplying circuit is configured as follows. The first conductor 213, the second conductor 214, and the third conductor 230 are formed on the semiconductor substrate 202 at appropriate intervals. The first conductor 213 is divided into two parts at a portion facing the gate electrode of the first field-effect transistor 212 so as to be separated from each other by a predetermined distance, and each first conductor 213 and a predetermined part are formed on the semiconductor substrate 202 therebetween. 4th of strip shape separated by interval
Conductor 205 is formed. The fourth conductor 205,
The first conductor 213 that is a ground conductor forms a coplanar line 210 that is an input line having a characteristic impedance Z ₀ . Similarly, the third conductor 230 is
The source electrodes 221 s and 222 s of the third field-effect transistors 221 and 222 are divided into two portions at predetermined intervals in the vicinity of the extending portions on the right side in the drawing, and each third electrode is formed on the semiconductor substrate 202 therebetween. A strip-shaped fifth conductor 207 is separated from the conductor 230 by a predetermined distance.
Is formed. By the fifth conductor 207 and the third conductor 230 which is a ground conductor, the characteristic impedance Z
A coplanar line 211, which is an output line having _zero , is formed.

One end of the fourth conductor 205 is connected to the source electrode 212 s of the first field effect transistor 212. Similarly, one end of the fifth conductor 207 is connected to the second and third conductors 207.
Are connected to the mutually connected source electrodes 221 s and 222 s of the field effect transistors 221 and 222.
Gate electrode 212 of first field effect transistor 212
g is the edge of each of the first conductors 213 divided into two and formed between them. Air bridge conductor 241
In order to make the first conductors 213 divided into two equal potentials, the first conductors 213 divided into two so as not to contact the fourth conductor 205 are connected as shown in FIG. The connection is made via the bridge pier conductor 241a.

The drain electrode 212d of the first field-effect transistor 212 is connected to the protruding portion of the second conductor 214, and the first conductor 213 and the second conductor 214 are formed at a predetermined interval from each other to form a slot line. 215. The second conductor 214 has a slot line 215.
Through a first MIM capacitance 217 formed by forming a metal conductor on a part of the second conductor 214 via an insulator (not shown) at the longitudinally extending end of
It has a dielectric reactance component and is connected to one end of a strip-shaped sixth conductor 219 formed on the semiconductor substrate 202. Similarly, the first conductor 213 is connected to the first conductor 213 at the longitudinally extending end of the slot line 215.
A strip shape formed on a semiconductor substrate 202 having a dielectric reactance component via a second MIM capacitance 218 formed by forming a metal conductor via an insulator (not shown) on an upper part thereof Is connected to one end of the seventh conductor 220. Further, the other ends of the sixth conductor 219 and the seventh conductor 220 are connected to the gate electrodes 221g and 222g of the second and third field effect transistors 221 and 222, respectively.

Second and third field effect transistors 22
Each of 1 and 222 has drain electrodes 221d and 222d formed integrally, and source electrodes 221s and 222s connected to each other. As shown in FIG. 6, the drain electrodes 221d and 222d are connected to the third conductor 230 which is a ground conductor via the pier conductor 245b, the air bridge conductor 245, the pier conductor 245a, and the MIM capacitance 223. The third conductor 230 which is connected at a high frequency and is a ground conductor via the pier conductor 245b, the air bridge conductor 245, the pier conductor 245c, and the MIM capacitance 224.
Is connected to a high frequency. Here, the air bridge conductor 245 is connected to the second and third field effect transistors 221.
And 222, so as not to contact each of the gate electrodes 221g and 222g and each of the source electrodes 221s and 222s.
It is formed using the pier conductors 245a, 245b and 245c. As shown in FIG. 6, the MIM capacitances 223 and 224 form metal conductor films 223a and 224a on the third conductor 230, which is a ground conductor, via insulator films 223b and 224b, respectively. It is composed.

As shown in FIG. 5, the strip-shaped sixth conductors 21 each having a dielectric reactance component
The 9th and seventh conductors 220 are formed at a predetermined interval from each other to form a slot line 260. The drain electrodes 221d and 222d are located at the center of the gap between the sixth conductor 219 and the seventh conductor 220 constituting the slot line 260 and have a triangular edge at the right end in the figure of the slot line 260. The end is located and the slot line 26
It has a triangular protrusion (hereinafter, referred to as an electrode protrusion) disposed so as to protrude in the direction toward zero. The electrode protruding portion and the sixth conductor 219 are formed so that the distance between them becomes smaller as approaching the second field-effect transistor 221 to form a tapered slot line 261. The seventh conductor 220 is formed so that the distance between the seventh conductor 220 and the third field-effect transistor 222 becomes smaller as it approaches the third field-effect transistor 222.
Is configured. Therefore, the signal input to the slot line 260 is divided into two with the same amplitude and opposite phase at the edge of the triangle of the electrode protrusion, and then the two divided signals are respectively transmitted to the slot line 261 and the slot line 262. Output
Second and third field effect transistors 221 and 222
Is input to Therefore, these slot lines 260, 2
61 and 262 constitute a branch circuit.

Second and third field effect transistors 22
The source electrodes 221 s and 222 s of 1 and 222 are both formed integrally with the center conductor 207 of the coplanar line 211. The gate electrode 221g is connected to the third conductor 230, which is a ground conductor, via a resistor 232, whereby a zero bias voltage is applied to the gate electrode 221g. Further, the gate electrode 222g is connected to the third conductor 230, which is a ground conductor, via the resistor 233, whereby a zero bias voltage is applied to the gate electrode 222g. The drain electrode 212d of the first field-effect transistor 212 is connected via a second conductor 214, a resistor 242, a strip-shaped conductor 228, and a metal conductor film 243a which is a component of the MIM capacitance 243 shown in FIG. Connected to the DC pad 229. This gives D
The drain bias voltage applied to the C pad 229 is
The voltage is applied to the drain electrode 212d. Here, as shown in FIG. 6, the MIM capacitance 243 is formed by forming a metal conductor film 243a on a part of the third conductor 230 via an insulator film 243b. Drain electrode 2 of second and third field effect transistors 221 and 222
21d and 222d are pier conductor 245b, air bridge conductor 245, pier conductor 245a, and MIM.
A metal conductor film 223a having a capacitance 223 and a resistance 2
44 to the DC pad 229. As a result, the drain bias voltage applied to the DC pad 229 is applied to the drain electrodes 221d and 222d. The drain bias voltage of the first field-effect transistor 212 is applied such that the current of the drain electrode 212d changes in a linear region in relation to the gate-source electrode voltage. The source bias voltage of the second and third field-effect transistors 221 and 222 is such that the current of the drain electrodes 221d and 222d of the field-effect transistors 221 and 222 is large in relation to the gate-source electrode voltage. It is applied so as to change in a nonlinear region having only a second-order component.

FIG. 8 is an equivalent circuit diagram of the MMIC type microwave frequency multiplier of the second embodiment. The input signal is input to the first field-effect transistor 212 via the coplanar line 210, and then is input to the slot line 215.
, The capacitances 217 and 218, the strip-shaped sixth conductor 219 and the seventh conductor 220 having an inductive reactance component, and the gates of the second and third field-effect transistors 221 and 222 through the branch circuit. The voltage is applied to the electrodes 221g and 222g. The impedance of the source electrode 212s of the first field-effect transistor 212 is reduced by the impedance matching action of the first field-effect transistor 212.
Can be matched to the characteristic impedance Z ₀ .
The strip-shaped sixth conductor 219 and the seventh conductor 220 each having an inductive reactance component are formed by the first field-effect transistor 212 and the capacitor capacitance component parasitic to the second and third field-effect transistors 221 and 222. It has the role of compensating for the deterioration of the high-frequency characteristics due to the noise and broadening the frequency characteristics. Specifically, the sixth conductor 219 and the seventh conductor 220 are connected to the field-effect transistors 212 and 22.
The LC low-pass filter and the parasitic capacitance between the respective drain and gate electrodes 1 and 222 are configured, and the LC low-pass filter realizes a wider frequency band of the multiplying operation, that is, a flattening of characteristics within a desired frequency band.

The slot lines 260, 261 and 26
In the equivalent circuit diagram shown in FIG. 8, the branch circuit constituted by 2 is represented by a transformer having two coils of equal inductance connected in series on the secondary side. The input signal input to the slot line 260 is divided into two signals having the same amplitude and opposite phases by a transformer, which is a branch circuit, and then the signals are respectively divided into the slot line 261 and the slot line 26.
2 is output. These two signals are converted by the second and third field effect transistors 221 and 222 into a fundamental wave signal component of the input signal and its fundamental signal using a region where the relationship between the gate-source electrode voltage and the drain current is non-linear. The signal is frequency-converted into a signal having a harmonic component whose frequency is multiplied, and is output to the source electrodes 221s and 222s connected to each other. The source electrode 22 connected to the second and third field effect transistors 221 and 222 is connected to each other by the impedance matching function of the second and third field effect transistors 221 and 222.
The impedance of 1 s and 222 s can be matched to the characteristic impedance Z ₀ of the output coplanar line 211.

The two signals output to each of the source electrodes 221 s and 222 s are
Since s are connected to the fifth conductor 207 at the same distance from each other, synthesis is performed. Here, the fundamental signal component and the third harmonic component of the two signals are output as the first and third order terms of the quadratic function equation of the gate-source electrode voltage and the drain current, respectively. The signal components have amplitude opposite phases, and these signal components are combined in phase and cancel each other, and are not output to the coplanar line 211 which is the output line.

Each second harmonic component having twice the frequency of the above two signals is output as a second order term of a quadratic function equation of a gate-source electrode voltage and a drain current. The second harmonic components having the same amplitude and the same phase are output, these components are combined in the same phase, emphasize each other, and output via the coplanar line 211.

As described above, the source bias voltages of the second and third field-effect transistors 221 and 222 have a non-linear relationship having only a secondary component in which the relationship between each drain current and the voltage between the gate and source electrodes is large. Therefore, the fourth-order and higher harmonic components are negligibly small. Therefore, as a result, only the signal having the second harmonic component is output from the second and third field-effect transistors 221 and 222 via the coplanar line 211.

<Other Embodiments> The sixth conductor 219 and the seventh conductor 220 of the second embodiment are described.
May have a spiral shape, meander shape or zigzag shape for miniaturization. Further, the branch circuits of the slot lines of the first and second embodiments are not limited to being formed by the slot lines.

[0037]

As described above in detail, the first and second grounded field-effect transistors provided in the microwave frequency multiplier of the present invention not only function as a frequency multiplier, but also have a branch circuit and an output. Functions as a matching circuit. Thereby, the configuration of the circuit can be simplified and the size can be reduced. Further, a grounded gate field-effect transistor constituting the microwave frequency multiplier,
The branch circuits formed by the first and second grounded field-effect transistors and the slot lines formed by the electrodes of the first and second grounded field-effect transistors all affect the frequency of the input signal. Not done. For this reason, compared with the conventional example using a microwave line whose length is determined by the frequency of the operating signal, it is possible to realize a significant reduction in the size of the balanced microwave frequency multiplier and a wider operating frequency band.

[Brief description of the drawings]

FIG. 1 is a plan view of a balanced microwave frequency multiplier according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view of a branch circuit formed in the balanced microwave frequency multiplier of FIG. 1;

FIG. 3 is an equivalent circuit diagram of the balanced microwave frequency multiplier of FIG. 1;

FIG. 4 is a plan view of an MMIC balanced microwave frequency multiplier according to a second embodiment of the present invention.

FIG. 5 is an enlarged plan view of a branch circuit formed in the MMIC balanced microwave frequency multiplier of FIG. 4;

FIG. 6 is a longitudinal sectional view taken along line AA ′ of FIG. 4;

FIG. 7 is a longitudinal sectional view taken along line BB ′ of FIG. 4;

8 is an equivalent circuit diagram of the MMIC-balanced microwave frequency multiplier shown in FIG.

FIG. 9 is a circuit diagram of a conventional balanced microwave frequency multiplier.

[Explanation of symbols]

112, 212 ... grounded field effect transistors 121, 122, 221, 222 ... grounded drain field effect transistors 150, 210 ... input lines 151, 211 ... output lines 160, 161, 162, 260, 261, 262 ... slot lines .

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-138008 (JP, A) JP-A-1-208908 (JP, A) JP-A-63-114305 (JP, A) JP-A-57- 124908 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H03B 19/14 H03H 11/28-11/40 H01P 5/02-5/20

Claims (1)

(57) [Claims] 1. A microwave frequency multiplying circuit for multiplying the frequency of a signal input to an input line and outputting the multiplied signal to an output line, the source electrode comprising: a gate-grounded field-effect transistor connected to the input line; A grounded drain field effect transistor having a common drain electrode and a source electrode, wherein the gate electrode of one field effect transistor is connected to the drain electrode of the grounded gate field effect transistor and the other field effect transistor The gate electrode of the first and second grounded field-effect transistors is connected to the gate electrode of the field-effect transistor, and the source electrode includes first and second grounded field-effect transistors connected to the output line. The first slot line is formed by the two gate electrodes of the two drain-grounded field effect transistors. A second slot line is formed by the gate electrode of the first grounded drain field effect transistor and the shared drain electrode, and the second slot line is formed by the gate electrode of the second grounded drain transistor and the shared drain electrode. A third slot line having the same width as the slot line is formed, and the signals transmitted through the first slot line are divided into two signals having the same amplitude and opposite phase with each other by the first to third slot lines. And a branch circuit for outputting to the second slot line and the third slot line.