JP2537518B2 - Phase shifter - Google Patents

Description

The present invention relates to a phase shifter capable of switching a phase amount.

[Prior Art] FIG. 5 is a plan view of a conventional microwave band path length switching type hybrid phase shifter.

In FIG. 5, an input strip conductor 18 and an output strip conductor 19 are formed on a dielectric substrate 1 having a ground conductor (not shown) formed on the entire back surface, and one end of each of the conductors 18 and 19 is an input / output terminal. It is 10 and 11. The other end of the conductor 18 is connected to the other end of the conductor 19 via the pin diode 12, the strip conductor 16 having a predetermined length, and the pin diode 13, and
The pin diode 14 and the conductor 16 are connected to the other end of the conductor 19 via a strip conductor 17 having a predetermined length different from that of the conductor 16 and the pin diode 15. Here, the pin diodes 12 to 15 operate as switches with a predetermined applied bias voltage. Also, the strip conductors 16, 17, 18, 19 and the ground conductor are
It constitutes a microstrip line.

In the phase shifter configured as described above, when the bias voltage is changed to turn on the pin diodes 12 and 13 and turn off the pin diodes 14 and 15, the microwave signal input to the input terminal 10 becomes Conductors 18, 16 and 19
Is output to the output terminal 11 via. On the other hand, when the pin diodes 12 and 13 are turned off and the pin diodes 14 and 15 are turned on, the microwave signal input to the input terminal 10 is transferred to the conductors 18 and 1.
It is output to the output terminal 11 via 7,19. By switching the pin diode to the strip conductor 16 side or the 17 side in this way, it is possible to obtain the phase difference of the output signals proportional to the difference in the path lengths of the strip conductors 16 and 17.

[Problems to be Solved by the Invention] However, in the conventional phase shifter as shown in FIG. 5, since the difference in line length is used, a strip conductor having a predetermined line length is formed, and the circuit becomes large. There was a point. Also,
The phase shifter using a diode as shown in FIG. 5 has a problem that electrical separation between input and output cannot be performed.

An object of the present invention is to solve these problems and to provide a phase shifter which is smaller than the conventional example and which can perform good electrical isolation between input and output.

[Means for Solving the Problems] In the present invention, the first electrode, which is a gate electrode, is connected to a signal input terminal, the second electrode is AC-grounded to ground, and the third electrode is a signal output. A field effect transistor connected to the terminal, wherein the bias voltage of the third electrode is higher than the bias voltage of the second electrode and the bias voltage of the second electrode is higher than the bias voltage of the gate electrode. A first bias state and a second bias in which the bias voltage of the second electrode is higher than the bias voltage of the third electrode and the bias voltage of the third electrode is higher than the bias voltage of the gate electrode. It is characterized in that the phase difference of the signal between the signal output terminals of the signal input terminal is changed by selectively switching the state.

The present invention also relates to a field effect transistor in which a first electrode, which is a gate electrode, is connected to a signal input terminal, a second electrode is AC grounded to earth, and a third electrode is connected to a signal output terminal. A susceptance element connected between the gate electrode and the third electrode, wherein the bias voltage of the third electrode is higher than the bias voltage of the second electrode and the bias voltage of the second electrode is A first bias state higher than the bias voltage of the gate electrode, a bias voltage of the second electrode higher than the bias voltage of the third electrode and a bias voltage of the third electrode of the gate electrode; It is characterized in that the phase difference of the signal between the signal input terminal and the signal output terminal is changed by selectively switching the second bias state higher than the bias voltage.

[Operation] In the first configuration, the bias voltage of the third electrode is higher than the bias voltage of the second electrode and the bias voltage of the second electrode is higher than the bias voltage of the gate electrode. By setting the bias state of 1, the second and third electrodes can be operated as a source electrode and a train electrode, respectively, and the field effect transistor can be operated as a source-grounded field effect transistor. Further, a second bias state in which the bias voltage of the second electrode is higher than the bias voltage of the third electrode and the bias voltage of the third electrode is higher than the bias voltage of the gate electrode is set. Thus, the second and third electrodes can be operated as a drain electrode and a source electrode, respectively, and the field effect transistor can be operated as a drain-grounded field effect transistor. Therefore, if the field-effect transistor is an ideal field-effect transistor, the phase difference of the signal between the signal input terminal and the signal output terminal differs by 180 degrees between the drain ground and the source ground, as is well known. By selectively switching between the two bias states, the phase difference of the signal between the signal input terminal and the signal output terminal can be changed from 0 degree to 180 degrees.

Further, by adopting the latter configuration, in addition to the above operation, the susceptance value of the susceptance element is set to an arbitrary value, and the two bias states are selectively switched, whereby the signal input terminal and the The phase difference of signals between the signal output terminals can be arbitrarily changed.

[Embodiment] First Embodiment FIG. 1 is a circuit diagram of a phase shifter including a microwave monolithic integrated circuit according to a first embodiment of the present invention.
In FIG. 1, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

This phase shifter focuses on the fact that the signal output phases of the drain-grounded field effect transistor (hereinafter, field-effect transistor is referred to as FET) and the source-grounded FET are different by 180 degrees. The feature is that the phase difference between input and output is changed by changing the bias voltage applied to the electrodes, and the line strip conductors 16 and 17 unlike the conventional example are not required.

In FIG. 1, Q ₀ is a Schottky gate type field effect transistor (hereinafter referred to as MESFET).
Q ₀ is the gate electrode 26 which is the first electrode, and the second and third electrodes 27 and 28 which are the source and drain electrodes, respectively.
It has. The gate electrode 26 is a DC blocking capacitor 20.
Bias terminal 29 for applying voltage Vg via choke coil 23 while being connected to input terminal 10 via
Connected to. Further, the gate electrode 26 is connected to the second electrode 27 via the susceptance element 50 having an impedance jY formed of a capacitor or a coil or a combined circuit of the capacitor and the coil. The second electrode 27 of the MESFET Q ₀ is connected to the bias terminal 30 for applying the bias voltage V ₁ via the choke coil 24 and to the output terminal 11 via the DC blocking capacitor 21.

Further, the third electrode 28 of the MESFET Q ₀ is connected to the ground via the DC blocking capacitor 22 and is also connected to the bias terminal 31 for applying the bias voltage V ₂ via the choke coil 25. Here, the capacitors 20 to 22 are composed of metal-insulator-metal capacitors (hereinafter referred to as MIM capacitors), and the choke coil 23 is used.
Numerals 25 to 25 are constituted by known ribbon-shaped inductances.

The bias terminal 29 is connected to the variable voltage source 61. The bias terminal 30 is connected to the variable voltage source 62 via the a side of the switch 60a and is connected to the variable voltage source 63 via the b side of the switch 60a. Bias terminal 31 is switch 60b
The switch 60b is connected to the variable voltage source 64 via the side a and the switch 60b is connected to the variable voltage source 65 via the side b.
Here, each of the variable voltage sources 61 to 65 can change each output voltage by changing the resistance value of the variable resistor VR.

Switches 60a and 60b are interlocked, and switch 6
When 0a and 60b are switched to the a side, the relationship between the bias voltages is set to be the following expression. Hereinafter, this bias setting is referred to as the first bias setting.

V ₁ > V ₂ > Vg When the switches 60a and 60b are switched to the b side,
The relation of each bias voltage is set to be the following equation.
Hereinafter, this bias setting is referred to as the second bias setting.

V ₂ ＞ V ₁ ＞ Vg MESFET Q ₀ 2nd drain electrode or source electrode
And the third electrodes 27, 28 have substantially the same shape and are formed symmetrically with respect to the gate electrode 26, the switch 60a,
By switching 60b to the a side and the b side, the second and third electrodes 27 and 28 become drain electrodes or source electrodes, respectively. That is, in the case of the first bias setting, the second electrode 27 serves as the drain electrode and the third electrode 28
Acts as the source electrode, and MESFET Q ₀
Operates as a MESFET. In the case of the second bias setting, the third electrode 28 operates as a drain electrode, the second electrode 27 operates as a source electrode, and the MESFET Q ₀ operates as a drain-grounded MESFET.

In the source-grounded or drain-grounded MESFET circuit 2 configured as described above, the microwave signal input to the input terminal 10 is input to the MESFET Q ₀ via the capacitor 20 and subjected to amplification and impedance conversion processing. After that, it is output to the output terminal 11 via the capacitor 21.

Regarding this MESFET circuit 2, (1) the susceptance element 50 is not connected under the condition that the MESFET Q ₀ is an ideal field effect transistor (hereinafter, the field effect transistor is referred to as FET) that can be described only by mutual conductance. When (Y = 0) and (2) Susceptance element 50
The following analysis will be performed separately for two cases where Y is connected (Y ≠ 0). Here, the mutual conductance of the MESFETQ ₀ of source ground and gms, a transconductance of the MESFET Q ₀ of the drain ground and gmd.

(1) When the susceptance element 50 is not connected (Y =
0) The S parameter of the MESFET circuit 2 in FIG. 1 is as shown in the following equation.

(A) When the first bias is set (V ₁ > V ₂ > Vg) S ₁₁ s = 1 …… (1) S ₁₂ s = 0 …… (2) S ₂₁ s = −2 gms ・ Z ₀ …… (3) S ₂₂ s = 1 (4) (b) When the second bias is set (V ₂ > V ₁ > Vg) S ₁₁ d = 1 (5) S ₁₂ d = 0 (( 6) S ₂₁ d = 2 gms · Z ₀ / (1 + gmd · Z ₀ ) …… (7) S ₂₂ d = (1-gmd · Z ₀ ) / (1 + gmd · Z ₀ ) …… (8) where Z ₀ is a characteristic impedance of the microwave line connected to the input terminal 10 and the output terminal 11, and subscripts s and d of the S parameter represent source grounding and drain grounding, respectively.

From the equations (2) and (6), the reverse transfer coefficients S ₁₂ s and S ₁₂ d of the MESFET circuit 2 are zero, and the input / output terminals 10 and 11 can be electrically separated. it can. Further, by changing the bias voltage V ₁ , V ₂ , Vg of the MESFET Q ₀ and changing the mutual conductances gms, gmd,
If the relation between the mutual conductances gms and gmd is set as the following equation, gms = gmd / (1 + gmd · Z ₀ ) ... (9) From the above equations (3) and (7), S ₂₁ s = − S ₂₁ d becomes (10).

By the way, if the signal voltage V ₁₀ input to the signal input terminal 10 is represented by the following equation, when V ₁₀ = Vsin (ωt + θ) MESFET Q ₀ is source grounded and drain grounded, the signal output terminal 11 Signal voltage output to V ₁₁ s, V ₁₁ d
Is represented by the following general formula. Here, a ₁ and a ₂ are amplification constants.

V ₁₁ s = a ₁ Vsin (ωt + θ + ψ ₁ ) V ₁₁ d = a ₂ Vsin (ωt + θ + ψ ₂ ) Therefore, the phase difference Δθ between the signal voltages V ₁₁ s and V ₁₁ d when switching the switches 60a and 60b is Represented.

Δθ = ψ ₁ −ψ ₂ On the other hand, as shown in the equation (10) as described above, the absolute values of the forward transfer coefficients S ₂₁ s and S ₂₁ d are equal in the first and second bias settings, and the signs are It is the opposite. Therefore, by switching the two bias settings using the switches 60a and 60b, the circuit 2 can be operated as a phase shifter of Δθ = 180 degrees. Also, especially gmdZ ₀ =
In the case of 1, S ₂₁ d = −S ₂₁ s = 1, and a circuit with an amplification factor of 1 can be configured.

(2) When the susceptance element 50 is connected (Y ≠ 0) The forward transfer coefficients S ₂₁ d and S ₂₁ s of the S parameter of the MESFET circuit 2 of FIG. 1 are as follows.

Here, using the condition of equation (9), and for simplification,
If gmd Z ₀ = 1 Therefore, by changing the susceptance Y of the susceptance element 50 from + ∞ to −∞, the forward transfer coefficient S ₂₁ s
And S ₂₁ d can be set to an arbitrary phase relationship. Therefore, set the two bias settings of MESFET Q ₀ to switch 60a,
By switching using 60b, the phase difference Δθ of an arbitrary signal can be set between the input / output terminals 10 and 11 of the MESFET circuit 2.

Here, when the parasitic capacitance exists in the MESFET Q ₀ , the input / output phase shift characteristic of the circuit 2 deteriorates in the high frequency band. In order to prevent this, the deterioration can be corrected by configuring the susceptance element 50 with an inductance. The difference between the absolute values of S ₂₁ d and S ₂₁ s when the susceptance element 50 is connected is about 2 dB when the susceptance Y is + ∞ or −∞, and the susceptance Y is generally close to zero. It takes a value, and | S ₂₁ d | ≈ | S ₂₁ s | at this time.

As described above, in the MESFET circuit 2 of FIG. 1, by selecting an appropriate value of the susceptance Y of the susceptance element 50 and switching the two bias settings by using the switches 60a and 60b, an arbitrary phase difference between signals can be obtained. A phase shifter having Δθ can be realized. Moreover, when the susceptance element 50 is not added, the input and output can be electrically separated.

Second Embodiment FIG. 2 is a circuit diagram of a phase shifter composed of a micro monolithic integrated circuit according to a second embodiment of the present invention.
In FIG. 2, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

This phase shifter differs from the first embodiment shown in FIG.
The MESFET circuit 3 having the MESFET Q ₁ having a gate grounded between the input terminal 10 and the capacitor 20 in front of the SFET circuit 2.
Is inserted. Hereinafter, the difference will be described in detail.

In Fig. 2, the source electrode of MESFET Q ₁ is the input terminal.
10 and the gate electrode is connected to ground. Also, the drain electrode of MESFET Q ₁ is the capacitor 20 of circuit 2.
And is connected to the ground via a gain adjusting resistor 35 having a resistance value R ₁ . This resistor 35 and MESFET
Q ₁ constitutes the MESFET circuit 3 for impedance matching between the microwave line connected to the input terminal 10 and the circuit 2.

The bias terminal 29 is connected to the variable voltage source 61 as described above, and the bias terminals 30 and 31 are the switches 60a,
It is connected to the variable voltage sources 26 to 65 via 60b.

In the phase shifter configured as above, the input terminal 10
The microwave signal input to is the gate grounded MESFET Q ₁
Input to the MESFET Q ₀ via the capacitor 20 after being subjected to amplification and impedance conversion processing. The microwave signal input to MESFET Q ₀ is processed for amplification and impedance conversion, and then the capacitor.
It is output to the output terminal 11 via 21. This phase shifter is analyzed under the condition that MESFETs Q ₀ and Q ₁ are ideal FETs as described above. Here, the transconductance of the gate-grounded MESFET Q ₁ is gmg.

(1) When the susceptance element 50 is not connected (Y =
0) (a) When the first bias is set (V ₁ > V ₂ > Vg) S ₁₁ s = (1-gmgZ ₀ ) / (1 + gmgZ ₀ ) …… (14) S ₁₂ s = 0 …… (15 ) S ₂₂ s = 1 (17) (b) When the second bias is set (V ₂ > V ₁ > Vg) S ₁₁ d = (1-gmgZ ₀ ) / (1 + gmgZ ₀ ) …… (18) S ₁₂ d = 0 (19) _{S 22 d = (1-gmgZ} 0) / (1 + gmgZ 0) ...... (21) from above (15) and (19), as in the first embodiment of FIG. 1, the reverse transfer coefficient S _{Since 12} s and S ₁₂ d are zero, the input / output terminals 10 and 11 can be electrically separated. Also, if gmgZ ₀ = 1 (22), the input end reflection coefficients S ₁₁ s and S ₁₁ d become zero,
Impedance matching can be achieved at the input terminal 10. Further, as in the case of the first embodiment of FIG. 1, if gms = gmd / (1 + gmdZ ₀ ) ... (23), then S ₂₁ s = −S ₂₁ d (24), In the first and second bias settings, the forward transfer coefficients S ₂₁ s and S ₂₁ d have the same absolute value and opposite signs, and the two bias settings are switched by using the switches 60a and 60b. The phase shifter of the signal
It can be operated as a phase shifter with θ = 180 degrees.

(2) When the susceptance element 50 is connected (Y ≠ 0) The forward transfer coefficient S of the S parameter of the phase shifter in FIG.
₂₁ d, S ₂₁ s is obtained, the condition of equation (23) is used, and for simplification, gmdZ ₀ = 1 and R ₁ = 2Z ₀ , Therefore, by changing the susceptance Y of the susceptance element 50 from + ∞ to −∞, the forward transfer coefficient S ₂₁ s
And S ₂₁ d can be set to an arbitrary phase relationship. Therefore, set the two bias settings of MESFET Q ₀ to switch 60a,
By switching using 60b, the phase difference Δθ of an arbitrary signal can be set between the input / output terminals 10 and 11 of the phase shifter.

As described above, the phase shifter of the circuit of FIG. 2 in which the two MESFET circuits 3 and 2 are cascade-connected is capable of performing impedance matching on the input side and electrical separation between input and output. Can be realized as a container.

Third Embodiment FIG. 3 is a circuit diagram of a phase shifter including a microwave monolithic integrated circuit according to a third embodiment of the present invention.
In FIG. 3, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

This phase shifter differs from the first embodiment shown in FIG.
The second stage of SFET2, that is, capacitor 21 and output terminal 11
That is, the MESFET circuit 4 having the drain-grounded MESFET Q ₂ is inserted between and. Hereinafter, the difference will be described in detail.

The gate electrode of the MESFET Q ₂ is connected to one end of the capacitor 21 and is also connected to the ground via the gain adjusting resistor 37 having the resistance value R ₂ . The drain electrode of MESFET Q ₂ is connected to the ground, and the source electrode is connected to the output terminal 11. With this resistor 37 and MESFET Q ₂ , the impedance matching MESFET circuit 4 between the microwave line connected to the output terminal 11 and the circuit 2 can be constructed.

The bias terminal 29 is connected to the variable voltage source 61 as described above, and the bias terminals 30 and 31 are the switches 60a,
It is connected to variable voltage sources 62 to 65 via 60b.

In the phase shifter configured as above, the input terminal 10
The microwave signal input to is input to MESFET Q ₁ whose gate is grounded through capacitor 20 and is amplified and impedance-converted.
Output to SFET Q ₂ . The microwave signal input to MESFET Q ₂ is output to output terminal 11 after being subjected to amplification and impedance conversion processing.

For this phase shifter, MESFET Q ₀ and
Analysis is performed under the condition that Q ₂ is an ideal FET.
Here, the transconductance of the drain-grounded MESFET Q ₂ is gmdd.

(1) When the susceptance element 50 is not connected (Y =
0) (a) When the first bias is set (V ₁ > V ₂ > Vg) S ₁₁ s = 1 (26) S ₁₂ s = 0 (27) S ₂₂ s = (1-gmddZ ₀ ) / (1 + gmddZ ₀ ) …… (29) (b) When the second bias is set (V ₁ > V ₂ > Vg) S ₁₁ d = 1 …… (30) S ₁₂ d = 0 …… (31) _{S 22 d = (1-gmddZ} 0) / (1 + gmddZ 0) than ...... (33) above (27) and (31) below, similarly to the first embodiment of FIG. 1, the reverse transfer coefficient S _{Since 12} s and S ₁₂ d are zero, the input / output terminals 10 and 11 can be electrically separated.

If gmddZ ₀ = 1 (34), the output end reflection coefficients S ₂₂ s and S ₂₂ d become zero,
Impedance matching can be achieved at the output terminal 11. Furthermore, if gms = gmd / (1 + gmdR ₂ ) ... (35), then S ₂₁ s = −S ₂₁ d ...... (36), which is the forward transfer coefficient S ₂₁ s in the first and second bias settings. And S ₂₁ d have the same absolute value and opposite signs, and by switching the two bias settings using switches 60a and 60b, the phase shifter of the circuit of FIG. It can be operated as a 180 degree phase shifter.

(2) When the susceptance element 50 is connected (Y ≠ 0) The forward transfer coefficient S of the S parameter of the phase shifter of FIG.
₂₁ d, S ₂₁ s is obtained, the condition of the equation (35) is used, and for simplification, if gmdR ₂ = 1 and R ₂ = 2Z ₀ , Therefore, by changing the susceptance Y of the susceptance element 50 from + ∞ to −∞, the forward transfer coefficient S ₂₁ s
And S ₂₁ d can be set to an arbitrary phase relationship. Therefore, set the two bias settings of MESFET Q ₀ to switch 60a,
By switching using 60b, it is possible to set an arbitrary phase difference Δθ between signals between the input / output terminals 10 and 11 of the phase shifter.

As described above, in the phase shifter of FIG. 3 in which the MESFET circuits 2 and 4 are connected in cascade, a phase shifter capable of impedance matching on the output side and electrically separating input and output can be realized.

Embodiment of FIG. 4 FIG. 4 is a circuit diagram of a phase shifter including a microwave monolithic integrated circuit according to a fourth embodiment of the present invention.
In FIG. 4, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

This phase shifter differs from the first embodiment shown in FIG.
Front side of SFET2, that is, input terminal 10 and capacitor 20
Having a second gate-grounded MESFET Q ₁ between and
The circuit 3 is inserted, and the MESFET circuit 4 having the drain-grounded MESFET Q ₂ in FIG. 3 is inserted after the MESFET circuit 2, that is, between the output terminal 11 and the capacitor 21.

The bias terminal 29 is connected to the variable voltage source 61 as described above, and the bias terminals 30 and 31 are the switches 60a,
It is connected to the variable voltage sources 26 to 65 via 60b.

In the phase shifter configured as above, the input terminal 10
The microwave signal input to is the gate grounded MESFET Q ₁
Input to the MESFET Q ₀ via the capacitor 20 after being subjected to amplification and impedance conversion processing. The microwave signal input to MESFET Q ₀ is processed for amplification and impedance conversion, and then the capacitor.
Output to MESFET Q ₂ via 21. Furthermore, MESFET
The microwave signal input to Q ₂ is amplified and impedance-converted, and then output to the output terminal 11.
Similar to the above, the following analysis is performed on this phase shifter under the condition that MESFETs Q ₀ , Q ₁ and Q ₂ are ideal FETs.

(1) When the susceptance element 50 is not connected (Y =
0) (a) When the first bias is set, (V ₁ > V ₂ > Vg) S ₁₁ s = (1-gmgZ ₀ ) / (1 + gmgZ ₀ ) …… (38) S ₁₂ s = 0 …… ( 39) S ₂₂ s = (1-gmddZ ₀ ) / (1 + gmddZ ₀ ) ... (41) (b) When the second bias is set (V ₂ > V ₁ > Vg) S ₁₁ d = (1-gmgZ ₀ ) / (1 + gmgZ ₀ ) …… (42) S ₁₂ d = 0 …… (43) S ₂₂ d = (1-gmddZ ₀ ) / (1 + gmddZ ₀ ) ... (45) From the above equations (39) and (43), the reverse transfer coefficient S ₁₂ is the same as in the first embodiment of FIG. Since s and S ₁₂ d are zero, the input / output terminals 10 and 11 can be electrically separated. If gmgZ ₀ = gmddZ ₀ = 1 (46), the input end reflection coefficient S ₁₁ s, S ₁₁ d and the output end reflection coefficient S ₂₂ s, S ₂₂ d become zero, and the input / output terminal 10 Impedance matching can be obtained at 11 and 11, respectively. Further, as in the case of the third embodiment of FIG. 3, if gms = gmd / (1 + gmdR ₂ ) (47), then S ₂₁ s = −S ₂₁ d (48). In the first and second bias settings, the forward transfer coefficients S ₂₁ s and S ₂₁ d have the same absolute value and opposite signs, and by switching the two bias settings using the switches 60a and 60b, The phase shifter of the circuit shown in FIG. 4 can be operated as a phase shifter with a phase difference Δθ = 180 degrees of signals.

(2) When the susceptance element 50 is connected (Y ≠ 0) The forward transfer coefficient S of the S parameter of the phase shifter in FIG.
₂₁ d, S ₂₁ s is obtained, the condition of equation (47) is used, and for simplification, if gmdR ₂ = 1 and R ₂ = 2Z ₀ , Therefore, by changing the susceptance Y of the susceptance element 50 from + ∞ to −∞, the forward transfer coefficient S ₂₁ s
And S ₂₁ d can be set to an arbitrary phase relationship. Therefore, set the two bias settings of MESFET Q ₀ to switch 60a,
By switching using 60b, it is possible to set an arbitrary phase difference Δθ between signals between the phase-shifted input / output terminals 10 and 11.

As described above, in the phase shifter of FIG. 4 in which the MESFET circuits 3, 2 and 4 are connected in cascade, it is possible to perform impedance matching on the input side and the output side and electrical isolation between the input side and the output side. Can be realized.

Experimental Example According to an experiment by the present inventor, in the circuit of the second embodiment of FIG. 2 when the susceptance element 50 is not connected, the signal frequency is changed in the range from 1 GHz to 26 GHz, and the above two bias settings are made. Input / output terminals by switching
The phase difference between 10 and 11 is shown in Table 1. Therefore,
By using the circuit of the phase shifter used in this experiment at a frequency of 1 GHz, it can be used as a 180 degree phase shifter.

Other Embodiments MESFETs Q ₀ , Q ₁ , and Q ₂ are used in the above embodiments, but the present invention is not limited to this, and other types of FETs may be used.
Further, although the microwave band phase shifter is described in the above embodiments, the present invention is not limited to this, and phase shifters in other frequency bands can be similarly realized. Furthermore, although the variable voltage sources 61 to 65 are used in the above embodiments, the present invention is not limited to this, and batteries may be used.

As described above, the phase shifter that does not use the line length difference can be realized with a simple circuit configuration, and thus, the size can be significantly reduced as compared with the conventional example. Further, as shown in FIG. 4, when the gate-grounded and drain-grounded MESFET circuits 3 and 4 are inserted on the input side and the output side of the MESFET circuit 2 and the susceptance element 50 is not connected, the input / output impedance matching is performed. It is possible to realize a phase shifter which is excellent in electrical isolation between input and output.

As described above in detail, according to the present invention, the first electrode, which is a gate electrode, is connected to the signal input terminal, the second electrode is AC-grounded to the ground, and the third electrode is Is a field effect transistor connected to a signal output terminal, the bias voltage of the third electrode is higher than the bias voltage of the second electrode, and the bias voltage of the second electrode is the bias voltage of the gate electrode. A higher first bias state, a bias voltage of the second electrode is higher than a bias voltage of the third electrode, and a bias voltage of the third electrode is higher than a bias voltage of the gate electrode. By selectively switching the bias state of No. 2, the field effect transistor can be operated as a source-grounded and drain-grounded field effect transistor. By selectively switching between the two bias states, it is possible to realize a phase shifter capable of changing the phase difference of signals between the signal input terminal and the signal output terminal from 0 degree to 180 degrees. Moreover, the phase shifter having good electrical isolation between the input and the output can be achieved by the electrical isolation between the electrodes of the field effect transistor. Further, as described above, since the transporter that does not use the line length difference can be realized with a simple circuit configuration, there is an advantage that the size can be reduced as compared with the conventional example.

In addition to the above configuration, a susceptance element connected between the third electrodes of the gate electrode of the field effect transistor is provided, and the susceptance value of the susceptance element is set to an arbitrary value to set the two bias states. By selectively switching, it is possible to realize a phase shifter capable of arbitrarily changing the phase difference of signals between the signal input terminal and the signal output terminal.

[Brief description of drawings]

1 to 4 are circuit diagrams of phase shifters according to first to fourth embodiments of the present invention, and FIG. 5 is a circuit diagram of a conventional phase shifter. 2,3,4 …… Schottky gate type field effect transistor circuit (MESFET circuit), 10 …… input terminal, 11 …… output terminal, 50 …… susceptance element, Q ₀ , Q ₁ , Q ₂ …… Schottky Gate type field effect transistor (MESFET).

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masayoshi Aikawa No. 5 Mihiraya, Seika-cho, Seika-cho, Soraku-gun, Kyoto A.R.

Claims (2)

(57) [Claims] 1. A field effect transistor in which a first electrode, which is a gate electrode, is connected to a signal input terminal, a second electrode is AC grounded to earth, and a third electrode is connected to a signal output terminal. A first bias state in which the bias voltage of the third electrode is higher than the bias voltage of the second electrode and the bias voltage of the second electrode is higher than the bias voltage of the gate electrode; The bias voltage of the second electrode is the third above
Of the signal input terminal and the signal output terminal by selectively switching a second bias state in which the bias voltage of the third electrode is higher than the bias voltage of the third electrode and the bias voltage of the third electrode is higher than the bias voltage of the gate electrode. A phase shifter characterized by changing the phase difference of signals between the two. 2. A field effect transistor in which a first electrode, which is a gate electrode, is connected to a signal input terminal, a second electrode is AC-grounded to earth, and a third electrode is connected to a signal output terminal. A susceptance element connected between the gate electrode and the third electrode, wherein the bias voltage of the third electrode is higher than the bias voltage of the second electrode and the bias voltage of the second electrode is The first bias state, which is higher than the bias voltage of the gate electrode, and the bias voltage of the second electrode, are set to the third bias state.
Of the signal input terminal and the signal output terminal by selectively switching a second bias state in which the bias voltage of the third electrode is higher than the bias voltage of the third electrode and the bias voltage of the third electrode is higher than the bias voltage of the gate electrode. A phase shifter characterized by changing the phase difference of signals between the two.