JPH0570967B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to field effect transistors (hereinafter referred to as field effect transistors).
This study relates to the miniaturization of semiconductor phase shifters that use FETs (abbreviated as FETs) as control elements.

[Conventional technology]

Figure 4 shows, for example, the IEEE MMIC Symposium
(1984) P11-13 is an equivalent circuit diagram showing the configuration of a conventional semiconductor phase shifter. In the figure, input terminal 1 is connected to a capacitor 2 via capacitor 2.
The source electrode of the first FET 3 is connected, and the source electrode of the second FET 5 is also connected via the inductor 4. Here, since the distinction between the drain electrode and the source electrode in the FET is not important, for convenience, the electrode closer to the input/output terminal will be referred to as the source electrode, and the same will apply in the following description. 1st FET
The source electrodes of the third FET 6 and the fourth FET 7 are connected to the drain electrode of the fourth FET 7 , the drain electrode of the third FET 6 is grounded, and the drain electrode of the fourth FET 7 is connected to the output terminal 8 via the capacitor 2 .

In addition, the drain electrode of the second FET5 is connected to the fifth FET5.
9. The source electrode of the sixth FET 10 is connected and
The drain electrode of 5FET9 is grounded, and the drain electrode of 6th FET1
The drain electrode of 0 is connected to the output terminal via an inductor 4.

In addition, an inductor 11 is connected in parallel between the source electrode and drain electrode of the third FET 6, and the second FET
5. An inductor 12 is connected in parallel between the source electrode and drain electrode of the fifth FET 9.

In addition to this, a circuit is required to apply a bias to the gate electrode of each FET, but it is not shown here.

A conventional semiconductor phase shifter is configured as described above,
A digital type semiconductor phase shifter is obtained by applying a bias to the gate electrode of the FET described below.

Figure 5 is an equivalent circuit of the FET when the bias applied to the gate electrode is changed.
is the case when the gate electrode is at ground potential, and
This is called the FET ON state. Figure 5b shows the case where a pinch-off voltage is applied to the gate electrode of the FET.
This is called the OFF state. When the FET is in the ON state,
FET becomes a low resistance element. On the other hand, when the FET is in the OFF state, the FET becomes a capacitor.

Utilizing these FET characteristics, the OFF state
By using FETs as part of the filter circuit, this type of semiconductor phase shifter has a High Pass-Low
Operates as a pass type phase shifter. Below, we will discuss changes in the semiconductor phase shifter equivalent circuit and phase changes when the bias applied to the gate electrode of the FET is changed.

Figure 6a shows the first FET in the circuit shown in Figure 4.
3. Apply a pinch-off voltage to each gate electrode of the 4th FET 7 and 5th FET 9 to turn them off, and the 2nd FET
4. This is an equivalent circuit when the gate electrodes of the third FET 6 and the sixth FET 10 are set to the ground potential and turned on. In this case, the first FET3 and fourth FET7 serve as capacitor _C2 , and the fifth FET9 serves as capacitor _C3.
2nd FET4, 3rd FET6, 3rd FET6,
Each of the 6FETs 10 is represented by a resistance r.

Here, considering that the value of the resistance r is sufficiently smaller than the impedance exhibited by the inductors 11 and 12, FIG. 6a can be rewritten as shown in FIG. 6b. The equivalent circuit shown in FIG. 6b represents a low-pass filter, and the passing phase is delayed compared to the case of direct connection.

On the other hand, Fig. 7a shows 2nd FET4, 3rd FET6,
This is an equivalent circuit when a pinch-off voltage is applied to each gate electrode of the 6FET 10 to turn the FET into an OFF state, and the gate electrodes of other FETs are set to ground potential to turn the FET into an ON state. In this case, the second FET4,
6FET10 can be used as capacitor _C5 and also as 3rd FET
6 is represented as capacitor _C4 . Also other
FET is represented by resistance r. Considering that the value of the resistance r is sufficiently smaller than the impedance exhibited by the capacitor 12 and the inductor 4, FIG. 7a can be rewritten as shown in FIG. 7b.

In the equivalent circuit of FIG. 7b, inductor 12
and capacitor C ₅ , inductor 11 and capacitor
For frequencies lower than the parallel resonant frequency of C ₄ ,
This indicates that it is a high-pass filter.
Then, the passing phase becomes an advanced phase compared to the case of direct connection.

That is, in this type of semiconductor phase shifter,
Bias applied to each gate electrode of 1st FET 3, 4th FET 7, 5th FET 9 and 2nd FET 4, 3rd FET
6. By alternately switching the bias applied to each gate electrode of the 6th FET 10 between 0V and the pinch-off voltage, the passing phase can be changed to lead or lag, and as a result, a digital phase shifter can be realized. Become.

[Problem that the invention seeks to solve]

However, in the above conventional semiconductor phase shifter,
Six FETs, five inductors, and two capacitors are required, and the circuit configuration is complex and has many circuit elements, making it difficult to miniaturize.

This invention was made in order to solve such problems, and it simplifies the circuit configuration and
The purpose is to reduce the number of FETs and inductors used and to obtain a compact semiconductor phase shifter.

[Means for solving problems]

Therefore, in the semiconductor phase shifter according to the present invention, the FETs connected to the same line share a common source electrode, thereby reducing the size of the phase shifter.

[Effect]

Therefore, in the semiconductor phase shifter according to the present invention, a low-pass filter and a high-pass filter are realized using four FETs and three inductances, and a desired amount of phase shift can be obtained. As a result, the overall size is extremely small.

[Embodiment] FIG. 1 is a perspective view showing an embodiment of a semiconductor phase shifter according to the present invention. In the figure, 13 is a semiconductor substrate, and a ground conductor 14 is provided on the lower surface side of the semiconductor substrate.
is provided. Reference numeral 15 denotes an input line, and a first FET 16 and a second FET 17 formed on the semiconductor substrate 13 are connected to this input line 15, sharing their respective source electrodes. Also, the 1st FET
One end of the first loop inductor 18 is connected to the drain electrode of the third FET 16, and the other end of the first loop inductor 18 is connected to the drain electrode of the third FET 19. The source electrode of the third FET 19 is connected to the output line 21, and the fourth FET 20 is connected to share the source electrode with the third FET 19. No.
One end of a second loop inductor 22 is connected to the drain electrodes of the second FET 17 and the fourth FET 20, respectively. Further, the other end of the second loop inductor 22 is grounded via a ground terminal 23 and a through hole 24. A bias circuit 27 consisting of a high impedance line 25 and a capacitor 26 is connected to the gate electrode of each FET.

In the semiconductor phase shifter configured in this way,
FIG. 2a shows an equivalent circuit when the gate electrodes of the first FET 16 and the third FET 19 are set to the ground potential, and a pinch-off voltage is applied to the gate electrodes of the second FET 17 and the fourth FET 20. Here, the second FET17,
4FET20 serves as the capacitor C _b and also as the 1st FET
16. The third FET 19 is represented as a resistor r. Further, the first inductor line 18 and the second inductor line 22 are represented as an inductor L _a and an inductor L _b , respectively. At frequencies lower than the series resonance frequency of capacitor C _b and inductor L _b , the circuit shown in Figure 2a
The result is a low-pass filter shown in Figure b. The passing phase in this case is expressed by the following equation.

θ _L = −tan ^-1 (X ₁ +2B ₁ −B ₁ ² X ₁ /2−2X ₁ B ₁ ) In addition, X ₁ is the normalized reactance value exhibited by L _a ,
B ₁ is the normalized susceptance value exhibited by the series circuit of C _b and L _b . X ₁ and B ₁ are standardized by the characteristic impedance Z ₀ of the input/output line.

Here, an inductor L _a in which X ₁ is 1 at a required frequency can be realized. Also, for the inductor L _b determined by the conditions described later, B ₁ X _1/2
A capacitor C _b can be realized.

Therefore, both the numerator and denominator of the above equation are positive, and θ _L
is a delayed phase.

On the other hand, a pinch-off voltage is applied to the gate electrodes of the first FET 16 and the third FET 19.
An equivalent circuit when the gate electrode of the 4FET 20 is set to the ground potential is shown in FIG. 3a. Here, the first FET1
6. The third FET 19 is represented by a capacitor C _a , and the second FET 17 and fourth FET 20 are represented by a resistor r.

At frequencies lower than the series resonance frequency of L _a and C _a , the equivalent circuit of FIG. 3a can be expressed as shown in FIG. 3b. FIG. 3b shows a high-pass filter, and the passing phase is expressed by the following equation.

_{θ H} = −tan ⁻¹ (X ₂ +2B _{2 −B 2} ² X ₂ / _{2−2X 2} B ₂ ) In the above equation, B ₂ is the normalized susceptance value exhibited by the inductor L _b .

Here, by using the inductor L _a previously determined to have X ₁ 1, a capacitor C _a having X ₂ -1 can be realized.

Also, the inductor L _b , which is B ₂ X _2/2 , is B ₁
This can be achieved by setting X _1/2 .

Therefore, the numerator of the above equation is negative, the denominator is positive, and θ _H has a leading phase.

Therefore, the first FET16, the third FET19 and the
By switching the bias applied to the gate electrodes of the 2nd FET 17 and the 4th FET 20 between the ground potential and the pinch-off voltage, the phase can be switched between delayed and advanced, and the phase shift amount θ _S : θ _S = θ _H − θ _L is digital. A phase shifter is realized.

By the way, in the above explanation, the inductors L _a , L _b
Although a case has been described in which a loop inductor is used as a means for realizing this, it goes without saying that the present invention is not limited to this, and a spiral inductor or an inductor line can be used.

〔Effect of the invention〕

As explained above, this invention uses four FETs.
This reduces the number of components by using three inductors, an OFF FET as part of the filter circuit, and a common drain for the two FETs connected to the same line. This has an excellent effect in that the semiconductor phase shifter can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing an embodiment of the semiconductor phase shifter according to the present invention, and FIGS. 2 and 3 are equivalent circuit diagrams for explaining the operation of the semiconductor phase shifter according to the present invention shown in FIG. , Fig. 4 is an equivalent circuit diagram showing the configuration of a conventional semiconductor phase shifter, Fig. 5 is an equivalent circuit diagram of a field effect transistor, and Figs. 6 and 7 explain the operation of the conventional semiconductor phase shifter. FIG. 13 is a semiconductor substrate, 14 is a ground conductor, 15 is an input line, and 16 is a
1FET, 17 is the second FET, 18 is the first loop inductor, 19 is the third FET, 20 is the fourth FET, 21
is the output line, 22 is the second loop inductor, 23
is a ground terminal, 24 is a through hole, 25 is a high impedance line, 26 is a capacitor, and 27 is a bias circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first field-effect transistor and a first field-effect transistor formed by sharing an input line and an output line formed on a semiconductor substrate, each consisting of a microstrip line, and a source electrode connected to the input line on the semiconductor substrate. two field-effect transistors, a third field-effect transistor and a fourth field-effect transistor formed by sharing a source electrode connected to the output line on the semiconductor substrate; a first inductance element connected between the drain electrode of the first field effect transistor and the drain electrode of the third field effect transistor; and the drain electrode of the second field effect transistor and the fourth field effect transistor formed on the semiconductor substrate. and a second inductance element connected between the first to fourth field effect transistors, and a bias voltage is applied to the gate electrodes of the first to fourth field effect transistors.