JP3830663B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device having a liquid crystal driving device.
[0002]
[Prior art]
FIG. 8 is a wiring diagram of clock signals used in a conventional liquid crystal display device.
In the figure, 1 is a timing control unit, 2 is a horizontal driver unit, 3 is a liquid crystal driving device constituting the horizontal driver unit 2, 4 is a bus line for transmitting a clock signal and the like, and 5 is an image digital signal and a control signal. Bus line.
[0003]
FIG. 9 is a diagram illustrating a clock signal in a conventional liquid crystal display device.
In a large-screen, high-definition liquid crystal display device, the frequency of the sampling clock signal (hereinafter, clock signal) of the image digital signal of the liquid crystal driving device is high. In addition, due to demands such as narrowing the frame of the display area and controlling costs, the bus line 4 for transmitting the clock signal from the timing control unit 1 to the liquid crystal driving device 3 of the horizontal driver unit 2 and the image digital signal and control. Since the printed circuit board having the bus line 5 for transmitting the signal becomes elongated, the bus line 4 for the clock signal performs one main route wiring as shown in FIG.
[0004]
[Problems to be solved by the invention]
When the main route wiring is performed, the transmission distance of the clock signal, the image digital signal, and the control signal is long, and the reflection noise of the clock signal, the image digital signal, and the control signal becomes large. In addition, when the resolution becomes higher than that of SXGA (Super Extended Graphics Array), the number of inputs connected to one bus line increases to 10 or more, and the capacitive load increases or multiple reflection occurs.
In this way, in the large-screen, high-definition liquid crystal display device, the edge of the clock signal may become dirty as shown in FIG. 9, and the Hi / Low fixed period of the clock signal may be reduced. Deviating from the standard causes jitter failure and malfunction of the liquid crystal driving device. Conventionally, a termination resistor is inserted in order to suppress reflection noise, but this is not preferable because a direct current flows to the power supply and GND, and power consumption increases.
[0005]
The present invention has been made to solve the above-described problems, and ensures a clock signal edge and a Hi / Low fixed period, and can prevent a jitter failure and a malfunction of a liquid crystal driving device. The primary purpose is to obtain
A second object is to obtain a liquid crystal display device having clock lines that do not intersect.
It is a third object of the present invention to obtain a liquid crystal display device capable of securing a setup / hold period of an image signal and preventing a jitter failure and an operation failure of the liquid crystal driving device.
[0006]
[Means for Solving the Problems]
In the liquid crystal display device according to the present invention, a liquid crystal display LCD control system which is divided into a plurality of blocks and supplies a drive signal for displaying video on the panel, the control unit supplies a clock signal to the liquid crystal driving device The liquid crystal driving device includes an input buffer for inputting a clock signal and an output buffer for outputting the clock signal. The clock signal is supplied from the control unit to the liquid crystal driving device by a clock wiring, and the clock wiring is connected to each block. A wiring connected to sequentially supply a clock signal, and a wiring connected to supply a clock signal in common to each liquid crystal driving device in each block from this wiring, and each block sequentially receives a clock signal. Between the wiring blocks connected to supply the liquid crystal, the output of the liquid crystal driving device arranged at the final position of each block Via the buffer in which the clock signal is supplied.
[0007]
Further, the liquid crystal driving device has an input / output buffer and switching means for switching input and output of the input / output buffer, and the input buffer and output buffer of the liquid crystal driving device are input / output switched to the input of the liquid crystal driving device. This is an input / output buffer switched to the output of the buffer and the liquid crystal driving device .
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a schematic diagram illustrating a circuit configuration of the liquid crystal driving device according to the first embodiment.
In the figure, 6 is an image digital signal and control signal input buffer, 7 is a clock signal input buffer, 8 is a drive circuit unit having a shift register, latch circuit, digital / analog conversion circuit, output amplifier, etc., and 9 is a clock signal. In this output buffer, the liquid crystal driving device 3 is composed of 6 to 9. The output buffer 9 is configured as an output buffer of a liquid crystal driving device such as a driver IC formed by a silicon wafer process or a liquid crystal panel integrated driver circuit formed by the same process as the liquid crystal panel.
[0010]
FIG. 2 is a circuit diagram showing the liquid crystal display device according to the first embodiment.
In the figure, 1 is a timing control unit, 2 is a horizontal driver unit, and 3 is a liquid crystal driving device constituting the horizontal driver unit 2 and is divided into blocks every n units. Signals and control signals are provided. Reference numeral 5 denotes a bus line for transmitting an image digital signal and a control signal. 10 is a vertical driver unit, 11 is a liquid crystal display panel unit to which signals are supplied by the horizontal driver unit 2 and the vertical driver unit 10, 12 is a clock wiring in cascade connection every n, and an output buffer 9 is provided between the blocks. The liquid crystal driving devices in the block are connected in common.
FIG. 3 is a diagram showing clock signals of the liquid crystal display device according to Embodiment 1 of the present invention.
[0011]
Next, the operation will be described.
The clock signal, the image digital signal, and the control signal from the signal source are changed to signals for driving the liquid crystal by the timing control unit 1 and transmitted to the vertical driver unit 10 and the horizontal driver unit 2. The vertical driver unit 10 and the horizontal driver unit 2 perform level conversion, digital / analog conversion, and the like as necessary, and transmit signals to the liquid crystal display panel unit 11 to drive the liquid crystal. Clock wirings 12 from the timing control unit 1 to the liquid crystal driving device 3 of the horizontal driver unit 2 are connected in cascades every n. First, a signal output from the output buffer of the timing control unit 1 is transmitted to n liquid crystal driving devices 3. The n-th (last) liquid crystal driving device 3 immediately outputs the input clock signal from the output buffer 9, and this clock signal is transmitted to the n + 1 to 2n-th liquid crystal driving devices 3. In this way, every n clock signals are transmitted, and the clock signals are transmitted to all the liquid crystal driving devices 3.
As shown in FIG. 3, the clock signal is reduced only in the clock edge like the clock signal in one conventional main route wiring and reflection noise. As a result, a clock edge and a Hi / Low fixed period are ensured to prevent a jitter failure and a malfunction of the liquid crystal driving device 3.
[0012]
Embodiment 2. FIG.
FIG. 4 is a circuit diagram showing a liquid crystal display device according to Embodiment 2 of the present invention.
In the figure, 1-3, 5, and 10-12 are the same as those in FIG. Reference numeral 13 denotes an output buffer connected to the outside of the liquid crystal driving device 3.
[0013]
Next, the operation will be described.
Clock wirings 12 from the timing control unit 1 to the liquid crystal driving device 3 of the horizontal driver unit 2 are cascaded every n pieces, and an output buffer 13 is connected to the outside of the liquid crystal driving device 3 every n pieces. . The output buffer 13 is an output buffer composed of TFTs formed by the same process as the standard logic IC and liquid crystal display panel formed by the silicon wafer process. First, the clock signal output from the output buffer of the timing control unit 1 is transmitted to the n liquid crystal driving devices 3. The output buffer 13 outside the nth liquid crystal driving device 3 immediately outputs the inputted clock signal, and this clock signal is transmitted to the n liquid crystal driving devices 3 from the (n + 1) th to the 2nth. In this way, every n clock signals are transmitted, and the clock signals are transmitted to all the liquid crystal driving devices 3.
As in the first embodiment, the clock signal is reduced only in the clock edge and the reflection noise like the clock signal in one conventional main route wiring. As a result, a clock edge and a Hi / Low fixed period are ensured to prevent a jitter failure and a malfunction of the liquid crystal driving device 3.
[0014]
Embodiment 3 FIG.
FIG. 5 is a circuit configuration diagram showing a liquid crystal driving device according to Embodiment 3 of the present invention.
In the figure, 3, 8, and 6 are the same as those in FIG. Reference numeral 14 denotes an input / output buffer for a clock signal provided in the liquid crystal driving device 3, and reference numeral 15 denotes a shift direction setting terminal for switching input or output of the input / output buffer 14.
[0015]
Next, the operation will be described.
The liquid crystal driving device 3 having the input buffer 6 for image digital signals, etc. is provided with a clock signal input / output buffer 14 and a shift direction setting terminal 15, and the clock direction input / output buffer 14 is set by setting the shift direction setting terminal 15. One of them functions as an input buffer and the other functions as an output buffer, so that the wirings in cascade connection can be made without crossing the wirings regardless of the shift direction. Cascading every n clock wirings prevents jitter and malfunction of the liquid crystal driving device 3, and enables cascade connection where the wirings do not intersect regardless of the shift direction, thereby reducing the number and area of the substrate layers. .
[0016]
Embodiment 4 FIG.
FIG. 6 is a circuit configuration diagram showing a liquid crystal drive device according to Embodiment 4 of the present invention.
In the figure, 3, 6 to 9 are the same as those in FIG. Reference numeral 16 denotes an output buffer for image digital signals and control signals, which is provided in the liquid crystal driving device 3.
FIG. 7 is a diagram showing a clock signal, an image digital signal, and a control signal of the liquid crystal display device according to Embodiment 4 of the present invention.
[0017]
Next, the operation will be described.
In the fourth embodiment, in addition to the configuration of the first embodiment, an output buffer 16 for image digital signals and control signals is provided. By using the liquid crystal driving device 3, not only a clock signal but also an image digital signal and a control signal can be cascade-connected, so that edge fringing and reflection noise are reduced. A clock edge and a Hi / Low fixed period are secured to prevent jitter and malfunction of the liquid crystal driving device 3, and as shown in FIG. 7, the phase difference between the clock signal due to the delay of the output buffer, the image digital signal, and the control signal Therefore, the setup / hold period of the image digital signal and the control signal can be secured, and the jitter failure and the malfunction of the liquid crystal driving device 3 can be prevented.
[0018]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
LCD panel liquid crystal driving device which is divided into a plurality of blocks and supplies a drive signal for displaying an image on, a controller for supplying a clock signal to the liquid crystal driving device, a liquid crystal driving device, a clock signal It has an input buffer for input and an output buffer for output of a clock signal. The clock signal is supplied from the control unit to the liquid crystal driving device through a clock wiring, and the clock wiring is connected so as to sequentially supply the clock signal to each block. Wiring connected to supply a clock signal in common to each liquid crystal driving device in each block from the wiring, and connected to sequentially supply a clock signal to each block. Between the blocks, a clock signal is supplied via the output buffer of the liquid crystal drive device arranged at the final position of each block. Since that, to secure the edges or Hi / Low fixed period of the clock signal to prevent malfunction of the jitter failure and a liquid crystal driving device.
[0019]
Further, the liquid crystal driving device has an input / output buffer and switching means for switching input and output of the input / output buffer, and the input buffer and output buffer of the liquid crystal driving device are input / output switched to the input of the liquid crystal driving device. Since the input / output buffer is switched to the buffer and the output of the liquid crystal drive device, the clock signal edge and Hi / Low fixed period are ensured, and the jitter and liquid crystal drive device malfunction are prevented, and the clock wiring that does not intersect is provided. It can be carried out.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a circuit configuration of a liquid crystal driving device according to Embodiment 1 of the present invention.
FIG. 2 is a circuit diagram showing a liquid crystal display device according to Embodiment 1 of the present invention.
FIG. 3 is a diagram showing a clock signal of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing a liquid crystal display device according to a second embodiment of the present invention.
FIG. 5 is a schematic diagram showing a circuit configuration of a liquid crystal driving device according to Embodiment 3 of the present invention.
FIG. 6 is a schematic diagram showing a circuit configuration of a liquid crystal driving device according to Embodiment 4 of the present invention.
FIG. 7 is a diagram showing a clock signal, an image digital signal, and a control signal of a liquid crystal display device according to Embodiment 4 of the present invention.
FIG. 8 is a wiring diagram of clock signals used in a conventional liquid crystal display device.
FIG. 9 is a diagram illustrating a clock signal used in a conventional liquid crystal display device.
[Explanation of symbols]
1 timing control unit, 2 horizontal driver unit, 3 liquid crystal driving device,
4 Bus line of clock signal,
5 Image digital signal and control signal bus lines,
6 Image digital signal and control signal input buffer,
7 Input buffer for clock signal, 8 Drive circuit section,
9 clock signal output buffer, 10 vertical driver section,
11 Liquid crystal display panel, 12 Clock wiring,
13 Clock signal output buffer,
14 clock signal input / output buffer, 15 shift direction setting terminal,
16 Image digital signal and control signal input buffer.

Claims (2)

LCD panel liquid crystal driving device which is divided into a plurality of blocks and supplies a drive signal for displaying an image on, a controller for supplying a clock signal to the liquid crystal driving device, the liquid crystal driving device, the clock An input buffer for inputting a signal; and an output buffer for outputting the clock signal. The clock signal is supplied from the control unit to the liquid crystal driving device through a clock wiring, and the clock wiring is sequentially supplied to each block. A wiring connected so as to supply a signal, and a wiring connected so as to supply the clock signal in common to each liquid crystal driving device in each block from the wiring. Between the blocks of wiring connected to supply signals, the liquid crystal arranged at the final position of each block The liquid crystal display device in which the clock signal via the output buffer of the braking system is characterized in that it is supplied. The liquid crystal driving device includes an input / output buffer and switching means for switching input and output of the input / output buffer, and the input buffer and output buffer of the liquid crystal driving device are input / output switched to the input of the liquid crystal driving device. 2. The liquid crystal display device according to claim 1, wherein the buffer is an input / output buffer switched to an output of the liquid crystal driving device.

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