JP2000028982A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of preventing a jitter defect or an operation defect of a liquid crystal driving device by securing the edge or the high/low fixed period of a clock signal. SOLUTION: A liquid crystal driving device 3 which supplies a driving signal corresponding to a picture digital signal to a liquid crystal display panel is divided into plural blocks, and the clock supplies from a timing control part to the liquid crystal driving device 3 is supplied by clock wiring which connects blocks of the liquid crystal driving device 3 in series through an output buffer 9 of the liquid crystal driving device and connects liquid crystal driving device 3 in individual block in common.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device having a liquid crystal driving device.

[0002]

2. Description of the Related Art FIG. 8 is a wiring diagram of a clock signal used in a conventional liquid crystal display device. In the figure, 1 is a timing control unit, 2 is a horizontal driver unit, 3 is a liquid crystal driving device constituting the horizontal driver unit 2, 4 is a bus line for transmitting a clock signal and the like, 5 is a digital image signal and a control signal. It is a bus line.

FIG. 9 is a diagram showing a clock signal in a conventional liquid crystal display device. In a large-screen, high-definition liquid crystal display device, the frequency of a sampling clock signal (hereinafter, a clock signal) of an image digital signal of a liquid crystal driving device is high. In addition, due to demands for narrowing the frame of the display area and reducing costs, the bus line 4 for transmitting a clock signal from the timing control unit 1 to the liquid crystal driving device 3 of the horizontal driver unit 2 and the image digital signal and control signal Since the printed circuit board having the bus line 5 for transmitting the signal becomes elongated, the bus line 4 for the clock signal performs one main route wiring as shown in FIG.

[0004]

When the main route wiring is performed, the transmission distance between the clock signal, the image digital signal, and the control signal is long, and the reflection noise of the clock signal, the image digital signal, and the control signal increases. Also, S
XGA (Super Extended Graphi
When the resolution becomes higher than (cs Array), the number of inputs connected to one bus line also increases to 10 or more, which increases the capacitive load and causes multiple reflection. As described above, in the large-screen, high-definition liquid crystal display device, the edge of the clock signal becomes dirty as shown in FIG.
In some cases, the / Low fixed period is reduced, which deviates from the operation standard of the liquid crystal driving device, resulting in jitter failure and operation failure of the liquid crystal driving device. Conventionally, a terminating resistor was inserted to suppress reflection noise.
This is not preferable because it flows to the ND and power consumption increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been made in consideration of the edge of a clock signal and Hi /
A first object is to obtain a liquid crystal display device that can secure a Low fixed period and prevent a jitter defect and an operation defect of a liquid crystal driving device. It is a second object of the present invention to obtain a liquid crystal display device having clock lines that do not intersect.
It is a third object of the present invention to provide a liquid crystal display device capable of securing a setup / hold period of an image signal and preventing a jitter failure and a malfunction of a liquid crystal driving device.

[0006]

In a liquid crystal display device according to the present invention, a liquid crystal drive device divided into a plurality of blocks for supplying a drive signal corresponding to an image signal to a liquid crystal display panel; A control unit that supplies a clock signal and an image signal is provided, and the clock signal is supplied by a clock wiring that connects the blocks via an output buffer and commonly connects a liquid crystal driving device in each block.

Further, the liquid crystal driving device has an input buffer for inputting a clock signal and an output buffer for outputting a clock signal, and the output buffer connecting between the blocks is an output buffer of the liquid crystal driving device.

Further, the liquid crystal driving device has an input / output buffer and switching means for switching the input and output of the input / output buffer, and the output buffer connecting between the blocks has the input / output switched to the output of the liquid crystal driving device. What is a buffer. In addition, image signals are supplied by data wiring that connects the blocks via a data output buffer and commonly connects the liquid crystal driving devices in each block. In addition, the liquid crystal driving device has a data input buffer for inputting an image signal and a data output buffer for outputting the image signal, and the data output buffer connecting between the blocks is a data output buffer of the liquid crystal driving device. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a schematic diagram showing a circuit configuration of the liquid crystal driving device according to the first embodiment. In the figure, 6 is an input buffer for image digital signals and control signals, 7 is an input buffer for clock signals, 8 is a drive circuit section having a shift register, a latch circuit, a digital / analog conversion circuit, an output amplifier, etc., and 9 is a clock signal The liquid crystal driving device 3 is composed of 6 to 9 output buffers. The output buffer 9 is configured as an output buffer of a liquid crystal driving device such as a driver IC formed by a silicon wafer process or a liquid crystal panel integrated driver circuit formed by the same process as a liquid crystal panel.

FIG. 2 is a circuit diagram showing a liquid crystal display device according to the first embodiment. In the figure, 1 is a timing control unit, 2 is a horizontal driver unit, 3 is a liquid crystal driving device constituting the horizontal driver unit 2, divided into blocks every n units,
A clock signal, an image digital signal, and a control signal are supplied from the timing control unit 1. Reference numeral 5 denotes a bus line for transmitting image digital signals and control signals. Reference numeral 10 denotes a vertical driver unit, 11 denotes a liquid crystal display panel unit to which signals are supplied by the horizontal driver unit 2 and the vertical driver unit 10, 12 denotes clock wirings in cascade connection every n units, and an output buffer 9 between blocks. And the liquid crystal driving devices in the block are commonly connected. FIG. 3 is a diagram showing a clock signal of the liquid crystal display device according to the first embodiment of the present invention.

Next, the operation will be described. The clock signal, the image digital signal, and the control signal from the signal source are changed into signals for driving the liquid crystal by the timing control unit 1,
The signal is transmitted to the vertical driver unit 10 and the horizontal driver unit 2.
The vertical driver section 10 and the horizontal driver section 2 perform level conversion, digital / analog conversion, and the like as necessary, transmit signals to the liquid crystal display panel section 11, and drive the liquid crystal. Clock wirings 12 from the timing control unit 1 to the liquid crystal driving device 3 of the horizontal driver unit 2 are cascade-connected every nth clock. First, a signal output from the output buffer of the timing controller 1 is transmitted to the n liquid crystal driving devices 3. n-th (last) liquid crystal driving device 3
Outputs the input clock signal from the output buffer 9 immediately, and this clock signal is transmitted to the (n + 1) th to 2nth n liquid crystal driving devices 3. In this way, every nth clock signal is transmitted, and the clock signal is transmitted to all the liquid crystal driving devices 3. As shown in FIG. 3, as for the clock signal, only the clock edge like the clock signal in the conventional one main route wiring is reduced, and the reflection noise is reduced. As a result, the clock edge and Hi /
A Low fixed period is secured to prevent jitter failure and operation failure of the liquid crystal driving device 3.

Embodiment 2 FIG. FIG. 4 is a circuit diagram showing a liquid crystal display device according to Embodiment 2 of the present invention. In the figure, 1 to 3, 5 and 10 to 12 are the same as those in FIG. Reference numeral 13 denotes an output buffer connected to the outside of the liquid crystal driving device 3.

Next, the operation will be described. Clock wirings 12 from the timing control unit 1 to the liquid crystal driving device 3 of the horizontal driver unit 2 are cascade-connected every nth device, and an output buffer 13 is provided outside the liquid crystal driving device 3 every nth device.
Is connected. The output buffer 13 is an output buffer composed of a standard logic IC formed by a silicon wafer process and a TFT formed by the same process as a liquid crystal display panel. First, the clock signal output from the output buffer of the timing controller 1 is transmitted to the n liquid crystal driving devices 3. The output buffer 13 outside the n-th liquid crystal driving device 3 immediately outputs the input clock signal, and this clock signal is transmitted to the n + 1-th to 2n-th n liquid crystal driving devices 3. In this way, every nth clock signal is transmitted, and the clock signal is transmitted to all the liquid crystal driving devices 3. As in the first embodiment, the clock signal has reduced clock edge droop and reflection noise like a clock signal in one conventional main route wiring. As a result, the clock edge and Hi
A / Low fixed period is secured to prevent jitter failure and operation failure of the liquid crystal driving device 3.

Embodiment 3 FIG. 5 is a circuit configuration diagram showing a liquid crystal driving device according to Embodiment 3 of the present invention. In the figure, 3, 8, and 6 are the same as those in FIG. Reference numeral 14 denotes a clock signal input / output buffer provided in the liquid crystal driving device 3, and reference numeral 15 denotes a shift direction setting terminal for switching input or output of the input / output buffer 14.

Next, the operation will be described. Liquid crystal driving device 3 having input buffer 6 for image digital signals and the like
A clock signal input / output buffer 14 and a shift direction setting terminal 15 are provided. According to the setting of the shift direction setting terminal 15, one of the clock signal input / output buffers 14 functions as an input buffer and the other functions as an output buffer. By doing so, cascaded wiring can be performed without crossing wiring regardless of the shift direction. Clock wiring is n
By performing cascade connection every other unit, jitter failure and operation failure of the liquid crystal driving device 3 can be prevented, and cascade connection in which wirings do not intersect regardless of the shift direction becomes possible, and the number and area of substrate layers can be reduced.

Embodiment 4 FIG. 6 is a circuit diagram showing a liquid crystal driving device according to Embodiment 4 of the present invention. In the figure, 3, 6 to 9 are the same as those in FIG. Reference numeral 16 denotes an output buffer for an image digital signal and a control signal, which is provided in the liquid crystal driving device 3. FIG.
FIG. 14 is a diagram showing a clock signal, an image digital signal, and a control signal of the liquid crystal display device according to Embodiment 4 of the present invention.

Next, the operation will be described. Embodiment 4
Has an image digital signal and control signal output buffer 16 in addition to the configuration of the first embodiment. By using the liquid crystal driving device 3, cascade connection can be performed not only for a clock signal but also for an image digital signal and a control signal, thereby reducing edge blurring and reflection noise. A clock edge and a Hi / Low fixed period are secured to prevent a jitter failure and a malfunction of the liquid crystal driving device 3, and a phase difference between the clock signal, the image digital signal, and the control signal due to the delay of the output buffer as shown in FIG. Does not occur, the setup / hold period of the image digital signal and the control signal can be secured, and the jitter failure and the operation failure of the liquid crystal driving device 3 are prevented.

[0018]

Since the present invention is configured as described above, it has the following effects. A liquid crystal driving device divided into a plurality of blocks for supplying a driving signal according to an image signal to the liquid crystal display panel, and a control unit for supplying a clock signal and an image signal to the liquid crystal driving device, and an output buffer is provided between the blocks The clock signal is supplied by the clock wiring which is connected through the common line and also connects the liquid crystal driving devices in each block in common. Therefore, the edge of the clock signal and the fixed Hi / Low period are secured, and the jitter failure and the liquid crystal driving device Prevent malfunction.

Further, the liquid crystal driving device has an input buffer for inputting a clock signal and an output buffer for outputting a clock signal. Since the output buffer connecting the blocks is the output buffer of the liquid crystal driving device, An edge or a fixed Hi / Low period is secured to prevent a jitter failure and a malfunction of the liquid crystal driving device.

Further, the liquid crystal driving device has an input / output buffer and switching means for switching the input and output of the input / output buffer, and the output buffer connecting between the blocks has the input / output buffer switched to the output of the liquid crystal driving device. Since the buffer is used, the edge of the clock signal and the fixed period of Hi / Low are secured, the jitter failure and the operation failure of the liquid crystal driving device are prevented, and the clock wiring that does not intersect can be performed. Further, since the image signal is supplied by the data wiring which connects the blocks via the data output buffer and commonly connects the liquid crystal driving devices in each block, the setup / hold period of the image signal is secured, and the jitter is reduced. It prevents defects and operation failures of the liquid crystal driving device.

In addition, the liquid crystal driving device has a data input buffer for inputting an image signal and a data output buffer for outputting an image signal, and the data output buffer connecting the blocks is a data output buffer of the liquid crystal driving device. So, secure the setup / hold period of the image signal,
Prevents jitter failure and operation failure of the liquid crystal driving device.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a circuit configuration of a liquid crystal driving device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a clock signal of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram showing a circuit configuration of a liquid crystal driving device according to a third embodiment of the present invention.

FIG. 6 is a schematic diagram showing a circuit configuration of a liquid crystal driving device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a clock signal, an image digital signal, and a control signal of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 8 is a wiring diagram of a clock signal used in a conventional liquid crystal display device.

FIG. 9 is a diagram showing a clock signal used in a conventional liquid crystal display device.

[Explanation of symbols]

1 timing control unit, 2 horizontal driver unit, 3
LCD drive device, 4 clock signal bus line, 5 image digital signal and control signal bus line, 6 image digital signal and control signal input buffer, 7 clock signal input buffer, 8 drive circuit section, 9 clock signal output Buffer, 10 vertical driver, 1
1 liquid crystal display panel, 12 clock wiring, 13
Clock signal output buffer, 14 Clock signal input / output buffer, 15 Shift direction setting terminal, 16 Image digital signal and control signal input buffer.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tsutomu Takabayashi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Hiroshi Shinohara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F term in Mitsubishi Electric Corporation (reference) 2H093 NA16 NC16 NC21 NC22 NC34 ND34 ND36 ND39 ND40

Claims (5)

[Claims] 1. A liquid crystal driving device divided into a plurality of blocks for supplying a driving signal according to an image signal to a liquid crystal display panel, a control unit for supplying a clock signal and an image signal to the liquid crystal driving device, A liquid crystal display device characterized in that the clock signal is supplied by a clock wiring that connects between them via an output buffer and commonly connects a liquid crystal driving device in each block. 2. The liquid crystal driving device has an input buffer for inputting a clock signal and an output buffer for outputting a clock signal, and the output buffer connecting between the blocks is the output buffer of the liquid crystal driving device. The liquid crystal display device according to claim 1. 3. The liquid crystal driving device has an input / output buffer and switching means for switching the input and output of the input / output buffer, and the output buffer connecting between the blocks has an input buffer switched to the output of the liquid crystal driving device. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is an output buffer. 4. An image signal is supplied by data wiring which connects the blocks via a data output buffer and commonly connects a liquid crystal drive device in each block. 4. The liquid crystal display device according to claim 3. 5. A liquid crystal driving device has a data input buffer for inputting an image signal and a data output buffer for outputting an image signal, and the data output buffer connecting between the blocks is a data output buffer of the liquid crystal driving device. The liquid crystal display device according to claim 4, wherein: