JP3825353B2 - Ceramic substrate for multiple chip resistors - Google Patents

Description

【００３１】
この結果、表１により判るように、ダミー孔を持たない従来の多連チップ抵抗器用セラミック基板３１は、最外に位置する貫通孔３５ａの長短差は最大で０．０２８ｍｍもあった。
【００３２】
これに対し、本発明の多連チップ抵抗器用セラミック基板１はダミー孔７を形成するようにしたことにより、従来の多連チップ抵抗器用セラミック基板３１と比較して最外に位置する貫通孔５ａの長短差を小さくできることが判る。
【００３３】
また、製品部４の隣り合う分割溝２上の貫通孔５間の間隔Ｗを１とした時の最外の貫通孔５ａからダミー孔７までの最短距離Ｌを０．８〜１．２とすることにより、最外に位置する貫通孔５ａの長短差の最大値を０．０１ｍｍ以下とすることができ、特に優れていた。
【００３４】
【発明の効果】
以上のように、本発明によれば、セラミック基板の少なくとも一方の主面に縦横に形成された分割溝と、上記縦方向又は横方向のいずれか一方の分割溝上に等間隔で穿孔された複数の貫通孔を備え、最外に位置する縦横の分割溝で仕切られた領域を製品部、最外に位置する縦横の分割溝からセラミック基板の外辺までの領域をダミー部とした多連チップ抵抗器用セラミック基板において、最外に位置する分割溝上の貫通孔の一部がかかるダミー部に、最外に位置する分割溝上の貫通孔と同等の間隔で複数のダミー孔を設けたことによって、最外に位置する分割溝上の貫通孔の変形を抑え、他の貫通孔と同程度の寸法精度に保つことができる。特に、上記ダミー孔と最外に位置する分割溝上の貫通孔との最短距離を、製品部の隣り合う分割溝上に形成された貫通孔間の間隔と同等とすることで、最外に位置する分割溝上の貫通孔の寸法をより安定させることができる。
【００３５】
その為、多連チップ抵抗器用セラミック基板を用いれば、不良品を発生させることがなく、製品部より良品の多連チップ抵抗器を取り出すことができる。
【図面の簡単な説明】
【図１】本発明の多連チップ抵抗器用セラミック基板の一例を示す平面図である。
【図２】（ａ）（ｂ）は本発明の多連チップ抵抗器用セラミック基板の製造工程を説明するための断面図である。
【図３】本発明の多連チップ抵抗器用セラミック基板の最外に位置する分割溝上に形成された貫通孔を拡大した平面図である。
【図４】一般的な多連チップ抵抗器を示す斜視図である。
【図５】従来の多連チップ抵抗器用セラミック基板の一例を示す平面図である。
【図６】（ａ）（ｂ）は従来の多連チップ抵抗器用セラミック基板の製造工程を説明するための断面図である。
【図７】従来の多連チップ抵抗器用セラミック基板の最外に位置する分割溝上に形成された貫通孔を拡大した平面図である。
【符号の説明】
１：多連チップ抵抗器用セラミック基板
２：横方向の分割溝
２ａ：最外に位置する横方向の分割溝
３：縦方向の分割溝
３ａ：最外に位置する縦方向の分割溝
４：製品部
５：貫通孔
５ａ：最外に位置する分割溝上の貫通孔
６：ダミー部
６ａ：最外に位置する分割溝上の貫通孔の一部がかかるダミー部
７：ダミー孔
９：セラミックグリーンシート
１０：多連チップ抵抗器
１１：セラミック基板
１２：凹部
１３：抵抗体膜
１４：保護膜
１５：端面電極膜
２０：下パンチ
２０ａ：孔
２１：金型
２２，２３：打ち抜きパンチ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ceramic substrate for a multiple chip resistor used for forming a multiple chip resistor made of ceramic.
[0002]
[Prior art]
FIG. 4 is a perspective view showing a general multiple chip resistor. This multiple chip resistor 10 is provided with a resistor film 13 between opposing concave portions 12 on a long ceramic substrate 11 having both side surfaces formed with irregularities, and each resistor film 13 has both ends thereof. In addition to being electrically connected to the end face electrode films 15 deposited on the recesses 12, they were covered with the protective film 14.
[0003]
Further, in order to form such a multiple chip resistor 10, vertical and horizontal dividing grooves 32 and 33 as shown in FIG. 5 and, for example, a plurality of through holes formed at equal intervals on the horizontal dividing groove 32 are used. A region provided with a hole 35 and partitioned by vertical and horizontal dividing grooves 32a and 33a located at the outermost part extends from the product portion 34, vertical and horizontal dividing grooves 32a and 33a to the outer sides 31a and 31b of the ceramic substrate 31. A ceramic substrate 31 for a multiple chip resistor having a dummy portion 36 as a region is used. First, the end face electrode film 15 is printed and baked around the inner wall surface and the opening of the through hole 35 of the ceramic substrate 31, and then the ceramic substrate After the resistor film 13 is printed and baked on one main surface side of 31, and the resistance value of the resistor film 13 is set by laser trimming, the protective film 14 is printed and baked on the resistor film 13, After the primary break along the horizontal dividing groove 32, the multiple chip resistor 10 as shown in FIG. 4 is manufactured by performing a secondary break along the vertical dividing groove 33. It was.
[0004]
By the way, in order to manufacture the ceramic substrate 31 for the multiple chip resistors, first, a ceramic green sheet is prepared and, as shown in FIG. 6A, the ceramic green placed on the lower punch 40 having a plurality of holes 40a. After forming the vertical and horizontal divided grooves 32 and 33 on the surface of the sheet 39 by pressing a mold 41 having a cutting edge portion having a V-shaped cross section, as shown in FIG. A predetermined position on the dividing groove 32 is punched with a punching pin 42 having a cylindrical shape with a flat tip surface, and a plurality of through holes 35 are punched, and then the ceramic green sheet 39 is fired. (See JP-A-10-156821).
[0005]
[Problems to be solved by the invention]
By the way, when the through hole 35 is punched on the dividing groove 32 by the punching pin 42, tensile stress is generated in the ceramic green sheet 39 in the direction in which the through hole 35 expands, but tensile stress generated in the extending direction of the dividing groove 32. Since the density is increased by the formation of the dividing groove 32, the shape of the through hole 35 is hardly affected, and the tensile stress generated in the direction perpendicular to the dividing groove 32 is adjacent. Since it works so as to cancel each other by the stress generated when the through holes 35 are formed on the matching divided grooves 35, the shape of the through holes 35 is hardly affected.
[0006]
However, since a tensile stress does not act on the through-hole 35a on the outermost division groove 32a from the side of the dummy portion where a part of the through-hole 35a is applied, the through-hole formed on the outermost division groove 32a. Only the shape of the hole 35a has a problem of being deformed into an elliptical shape as shown in FIG.
[0007]
Therefore, when the end face electrode film 15 is formed later, the end face electrode film 15 having a uniform film thickness cannot be formed in the through hole 35 on the outermost divided groove 32a. Since it is a defective product when it is severe, there is a problem that the yield cannot be improved.
[0008]
[Means for Solving the Problems]
Therefore, in view of the above problems, the present invention provides a plurality of divided grooves formed vertically and horizontally on at least one main surface of the ceramic substrate, and a plurality of holes formed at equal intervals on either the vertically or horizontally divided grooves. Multiple chip resistors with through-holes, with the product area as the area partitioned by the outermost vertical and horizontal dividing grooves and the dummy area from the outermost vertical and horizontal dividing grooves to the outer edge of the ceramic substrate The ceramic ceramic substrate is characterized in that a plurality of dummy holes are provided on the outer side of the outermost divided groove where the through holes are formed at the same interval as the through holes on the outermost divided grooves. To do.
[0009]
The shortest distance between the dummy hole and the through hole on the outermost divided groove is preferably equal to the interval between the through holes formed on the adjacent divided grooves of the product portion.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0011]
FIG. 1 is a plan view showing an example of a ceramic substrate for multiple chip resistors of the present invention.
[0012]
This multiple chip resistor ceramic substrate 1 has a horizontal dividing groove 2 and a vertical dividing groove 3 on at least one main surface of the ceramic substrate 1, and is equidistantly arranged on the horizontal dividing groove 2. A plurality of perforated through holes 5 are provided, and the region partitioned by the outermost vertical and horizontal dividing grooves 2a and 3a is defined as the product portion 4, and the outermost vertical and horizontal dividing grooves 2a and 3a A region up to the outer sides 1a and 1b is a dummy portion 6.
[0013]
The ceramic forming the ceramic substrate 1 for the multiple chip resistor is not particularly limited, and a ceramic sintered body mainly composed of alumina, zirconia, mullite, silicon nitride, aluminum nitride, or the like can be used. The sectional shape of each of the dividing grooves 2 and 3 is V-shaped, and the planar shape of the through hole 5 is circular.
[0014]
And in the ceramic substrate 1 for multiple chip resistors of this invention, it penetrates on the outer side of the dividing groove 2a located on the outermost side where the through-hole 5a is formed, that is, on the lateral dividing groove 2a located on the outermost side. A plurality of dummy holes 7 are perforated in the dummy portion 6a to which a part of the hole 5a is applied at the same interval as the through hole 5a on the outermost division groove 2a.
[0015]
That is, in order to manufacture the multiple chip resistor ceramic substrate 1 shown in FIG. 1, first, a ceramic green sheet is prepared and, as shown in FIG. 2A, on the lower punch 20 having a plurality of holes 20a. After forming the vertical and horizontal divided grooves on the surface of the placed ceramic green sheet 9 by pressing a mold 21 having a V-shaped cutting edge portion to form a vertical and horizontal divided groove, as shown in FIG. A plurality of through holes 5 are perforated by punching a predetermined position on the divided groove 2 with a punching pin 22 having a flat tip end and a cylindrical shape. By punching a plurality of dummy portions 7 at the same interval as the through holes 5a on the outermost divided grooves 2a by the punching pins 23, the dummy portions 6a to which a part of the through holes 5a formed on 2a are also applied. , The outermost dividing groove 2 Since the tensile stress in the direction perpendicular to the dividing groove 2a can be applied to the upper through-hole 5a from both sides, the through-hole 5a is prevented from being deformed, and as shown in FIG. The planar shape can be circular.
[0016]
Therefore, the dimensional accuracy of all the through holes 5 formed in the product part 4 can be stabilized by firing the ceramic green sheet 9 in which the divided grooves 2 and 3 and the through holes 5 are formed at a predetermined temperature. Therefore, it is possible to prevent film formation failure during the formation of the end face electrode film and eliminate the occurrence of defective products, thereby improving the yield.
[0017]
By the way, in order to achieve such an effect, the shortest distance L between the dummy hole 7 formed in the dummy portion 6a and the through hole 5a formed in the laterally divided groove 2a located on the outermost side is set to the product portion 4 Are preferably close to the interval W between the through holes 5 formed on the adjacent divided grooves 2, and preferably equal to each other.
[0018]
This is because if the shortest distance L between the dummy hole 7 and the through hole 5a becomes larger or smaller than the interval W between the through holes 5 formed on the adjacent divided grooves 2 of the product portion 4, the punching pin 22 When the through hole 5a is drilled on the laterally divided groove 2a located at the outermost position, there is a difference between the tensile stress acting from the product side and the tensile stress acting from the dummy side. Since the dimensions of the through holes 5a formed on the outermost laterally divided grooves 2a cannot be stabilized, the shortest distance L between the dummy holes 7 and the through holes 5a cannot be offset. By making it equal to the interval W between the through holes 5 formed on the adjacent divided grooves 2 of the product part 4, the tensile stress acting from the product part side is equal to the tensile stress acting from the dummy part side. And pull each other It is possible to offset the force, the size of the through holes 5a to be formed in the lateral direction of the dividing groove 2a on which is located outermost can be stabilized.
[0019]
In the present invention, the shortest distance L between the dummy hole 7 and the through hole 5a is equivalent to the interval W between the through holes 5 formed on the adjacent divided grooves 2 of the product part 4. When the interval W between 5 is 1, the shortest distance L is in the range of 0.8 to 1.2 with respect to the interval W.
[0020]
The embodiment of the present invention has been described above, but the present invention is not limited to the above-described embodiment. For example, the planar shape of the through hole 5 is not limited to a circular shape, but an oval shape, A rectangular shape such as a rhombus or a square may be used, and a dummy dividing groove may be formed in the dummy portion 6 in consideration of the dividing property.
[0021]
In this manner, it goes without saying that the present invention can be applied to an improved or changed version as long as it does not depart from the gist of the present invention.
[0022]
【Example】
Here, 20 each of the multi-chip resistor ceramic substrate 1 of the present invention shown in FIG. 1 and the conventional multi-chip resistor ceramic substrate 31 shown in FIG. An experiment was conducted to compare the dimensional accuracy of the through holes 5a and 35a formed on the divided grooves 2a and 32a.
[0023]
In the ceramic substrate 1 for a multiple chip resistor of the present invention, the shortest distance L from the through hole 5a formed on the outermost lateral dividing groove 2a to the dummy hole 7 formed in the dummy portion 6a is set. Different things were prepared and the experiment was conducted in the same way.
[0024]
The ceramic substrates 1 and 31 for multiple chip resistors used in this experiment are both made of alumina ceramics having an alumina content of 96% by weight, the outer dimension is 60.0 × 51.2 mm, and the plate thickness is 0. A 37 mm plate-shaped body was obtained.
[0025]
Then, the multiple chip resistors taken out by division are made into four series, and the outer dimension is 2.0 mm × 1.0 mm, and 46 rows are formed in the long side direction of the plate-like body and 16 rows are formed in the short side direction. The vertical and horizontal dividing grooves 2, 3, 32, 33 are formed in this manner, and a total of 3008 through holes 5, 35 are drilled on the horizontal dividing grooves 2, 32. A ceramic substrate 31 for chip resistors was manufactured.
[0026]
Further, in the ceramic substrate 1 for a multiple chip resistor of the present invention, a part of the through hole 5a formed on the laterally divided groove 2a located on the outermost side is placed on the dummy portion 6a on the outermost side. A plurality of dummy holes 7 were formed by drilling at the same interval as the through holes 5a on the divided grooves 2a.
[0027]
However, in all cases, the planar shapes of the through holes 5 and 35 and the dummy hole 7 were circular, and the hole diameter was 0.14 mm.
[0028]
As shown in FIGS. 3 and 7, the diameter (X) in the extending direction of the through holes 5a, 35a on the laterally divided grooves 2a, 32a located at the outermost position is perpendicular to the through holes 5a, 35a. The roundness of the through-holes 5a and 35a was evaluated by measuring the diameter (Y) in the direction and calculating the difference between the lengths.
[0029]
The results are as shown in Table 1.
[0030]
[Table 1]

[0031]
As a result, as can be seen from Table 1, in the conventional multiple chip resistor ceramic substrate 31 having no dummy holes, the length difference between the outermost through holes 35a was 0.028 mm at the maximum.
[0032]
On the other hand, the multi-chip resistor ceramic substrate 1 of the present invention is formed with the dummy holes 7 so that the through-hole 5a located at the outermost position as compared with the conventional multi-chip resistor ceramic substrate 31 is provided. It can be seen that the difference in length can be reduced.
[0033]
Further, the shortest distance L from the outermost through hole 5a to the dummy hole 7 when the interval W between the through holes 5 on the adjacent divided grooves 2 of the product part 4 is 1 is 0.8 to 1.2. By doing so, the maximum value of the length difference of the outermost through-hole 5a can be made 0.01 mm or less, which is particularly excellent.
[0034]
【The invention's effect】
As described above, according to the present invention, the divided grooves formed vertically and horizontally on at least one main surface of the ceramic substrate and the plurality of holes formed at equal intervals on either the vertically or horizontally divided grooves. A multiple chip with a through-hole, the product section as the area partitioned by the vertical and horizontal dividing grooves located at the outermost part, and the dummy area as the area from the vertical and horizontal dividing grooves located at the outermost position to the outer side of the ceramic substrate In the ceramic substrate for resistors, by providing a plurality of dummy holes at the same interval as the through holes on the outermost divided grooves in the dummy part where a part of the through holes on the outermost divided grooves is provided, It is possible to suppress the deformation of the through hole on the outermost division groove and maintain the same dimensional accuracy as other through holes. In particular, the shortest distance between the dummy hole and the through hole on the outermost divided groove is equal to the interval between the through holes formed on the adjacent divided grooves of the product part, so that it is located on the outermost side. The dimension of the through hole on the dividing groove can be further stabilized.
[0035]
Therefore, if a ceramic substrate for multiple chip resistors is used, a defective multiple chip resistor can be taken out from the product section without generating defective products.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of a ceramic substrate for multiple chip resistors of the present invention.
2A and 2B are cross-sectional views for explaining a manufacturing process of a ceramic substrate for a multiple chip resistor according to the present invention.
FIG. 3 is an enlarged plan view of a through hole formed on a dividing groove located on the outermost side of the ceramic substrate for a multiple chip resistor of the present invention.
FIG. 4 is a perspective view showing a general multiple chip resistor.
FIG. 5 is a plan view showing an example of a conventional ceramic substrate for multiple chip resistors.
6A and 6B are cross-sectional views for explaining a manufacturing process of a conventional ceramic substrate for multiple chip resistors.
FIG. 7 is an enlarged plan view of a through hole formed on a dividing groove located on the outermost side of a conventional ceramic substrate for multiple chip resistors.
[Explanation of symbols]
1: Ceramic substrate 2 for multiple chip resistors: Horizontal dividing groove 2a: Outermost horizontal dividing groove 3: Vertical dividing groove 3a: Outermost vertical dividing groove 4: Product Part 5: Through hole 5a: Through hole on the outermost division groove 6: Dummy part 6a: Dummy part on which a part of the through hole on the outermost division groove is applied 7: Dummy hole 9: Ceramic green sheet 10 : Multiple chip resistor 11: Ceramic substrate 12: Recess 13: Resistor film 14: Protective film 15: End face electrode film 20: Lower punch 20 a: Hole 21: Die 22, 23: Punching punch

Claims (2)

It is provided with division grooves formed vertically and horizontally on at least one main surface of the ceramic substrate, and a plurality of through holes drilled at equal intervals on one of the division grooves in the vertical direction or the horizontal direction, and is located at the outermost position. Through holes are formed in the ceramic substrate for multiple chip resistors, where the area partitioned by the vertical and horizontal dividing grooves is the product part, and the area from the outermost vertical and horizontal dividing grooves to the outer side of the ceramic substrate is the dummy part. A ceramic substrate for a multiple chip resistor, wherein a plurality of dummy holes are provided on the outer side of the outermost divided groove at intervals equal to the through holes on the outermost divided groove. The shortest distance between the dummy hole and the through hole on the outermost divided groove is equal to the interval between the through holes formed on the adjacent divided grooves of the product portion. Ceramic substrate for multiple chip resistors.

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