JP2003297616A - Ceramic substrate for multiple-chip resistor - Google Patents

Ceramic substrate for multiple-chip resistor

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Publication number
JP2003297616A
JP2003297616A JP2002092547A JP2002092547A JP2003297616A JP 2003297616 A JP2003297616 A JP 2003297616A JP 2002092547 A JP2002092547 A JP 2002092547A JP 2002092547 A JP2002092547 A JP 2002092547A JP 2003297616 A JP2003297616 A JP 2003297616A
Authority
JP
Japan
Prior art keywords
outermost
holes
hole
ceramic substrate
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002092547A
Other languages
Japanese (ja)
Other versions
JP3825353B2 (en
Inventor
Osuke Hirano
央介 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
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Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002092547A priority Critical patent/JP3825353B2/en
Publication of JP2003297616A publication Critical patent/JP2003297616A/en
Application granted granted Critical
Publication of JP3825353B2 publication Critical patent/JP3825353B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic substrate for multiple-chip resistor, that is provided with longitudinal and transverse dividing grooves and through-holes which are formed at regular intervals on either the longitudinal or the transverse dividing grooves, is divided into a product section partitioned by the outermost longitudinal and transverse dividing grooves and a dummy section between the outermost longitudinal and transverse dividing grooves and the outer periphery of the substrate, and is reduced in the occurrence of defective products by stabilizing the dimensions the and shapes of the outermost through-holes. <P>SOLUTION: In the dummy section 6a including parts of the through-holes 5a formed on the outermost dividing grooves 2a, a plurality of dummy through- holes 7 is formed at intervals equal to those of the through-holes 5a formed on the dividing grooves 2a. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、セラミック製の多
連チップ抵抗器を形成するのに用いる多連チップ抵抗器
用セラミック基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate for a multiple chip resistor used for forming a multiple chip resistor made of ceramic.

【0002】[0002]

【従来の技術】図4は一般的な多連チップ抵抗器を示す
斜視図である。この多連チップ抵抗器10は、両側面が
凹凸に形成された長尺状のセラミック基板11上の対向
する凹部12間に抵抗体膜13を備えたもので、各抵抗
体膜13はその両端の凹部12に被着された端面電極膜
15とそれぞれ電気的に接続されるとともに、保護膜1
4によって被覆されるようになっていた。
2. Description of the Related Art FIG. 4 is a perspective view showing a general multiple chip resistor. This multiple chip resistor 10 is provided with a resistor film 13 between opposed recesses 12 on a long ceramic substrate 11 having both sides formed to be uneven, and each resistor film 13 has both ends thereof. Of the protective film 1 while being electrically connected to the end face electrode films 15 adhered to the concave portions 12 of the respective
4 was to be covered.

【0003】また、このような多連チップ抵抗器10を
形成するには、図5に示すような縦横の分割溝32,3
3と、例えば横方向の分割溝32上に等間隔で形成され
た複数の貫通孔35を備え、最外に位置する縦横の分割
溝32a,33aで仕切られた領域を製品部34、最外
に位置する縦横の分割溝32a,33aからセラミック
基板31の外辺31a,31bまでの領域をダミー部3
6とした多連チップ抵抗器用セラミック基板31が用い
られ、まず、セラミック基板31の貫通孔35の内壁面
及び開口部周辺に端面電極膜15を印刷、焼き付けした
後、セラミック基板31の一方の主面側に抵抗体膜13
を印刷、焼き付けし、次にレーザートリミングにより抵
抗体膜13の抵抗値を設定した後、抵抗体膜13上に保
護膜14を印刷、焼き付けし、次いで横方向の分割溝3
2に沿って一次ブレイクした後、縦方向の分割溝33に
沿って二次ブレイクすることにより、図4に示すような
多連チップ抵抗器10を製造するようになっていた。
Further, in order to form such a multiple chip resistor 10, vertical and horizontal dividing grooves 32 and 3 as shown in FIG.
3 and, for example, a plurality of through holes 35 formed at equal intervals on the horizontal dividing groove 32, and the region partitioned by the vertical and horizontal dividing grooves 32a, 33a located at the outermost side is the product portion 34, the outermost portion. The region from the vertical and horizontal dividing grooves 32a and 33a located at the outer side to the outer sides 31a and 31b of the ceramic substrate 31 is defined as the dummy portion 3
6, the ceramic substrate 31 for multiple chip resistors is used. First, after the end face electrode film 15 is printed and baked on the inner wall surface of the through hole 35 of the ceramic substrate 31 and around the opening, one main surface of the ceramic substrate 31 is printed. Resistor film 13 on the surface side
Is printed and baked, and then the resistance value of the resistor film 13 is set by laser trimming. Then, the protective film 14 is printed and baked on the resistor film 13, and then the lateral dividing groove 3 is formed.
After performing the primary break along 2 and the secondary break along the vertical dividing groove 33, the multiple chip resistor 10 as shown in FIG. 4 was manufactured.

【0004】ところで、多連チップ抵抗器用セラミック
基板31を製造するには、まず、セラミックグリーンシ
ートを用意し、図6(a)に示すように、複数の孔40
aを有する下パンチ40上に載せたセラミックグリーン
シート39の表面に、断面形状がV字状をした刃先部を
有する金型41を押し当てて縦横の分割溝32、33を
形成した後、図6(b)に示すように、横方向の分割溝
32上の所定位置を、先端面が平坦な円柱状をした打ち
抜きピン42で打ち抜いて複数の貫通孔35を穿孔した
後、セラミックグリーンシート39を焼成することによ
り製造するようになっていた(特開平10−15682
1号公報参照)。
In order to manufacture the ceramic substrate 31 for multiple chip resistors, first, a ceramic green sheet is prepared and a plurality of holes 40 are formed as shown in FIG. 6 (a).
After forming a vertical and horizontal dividing groove 32, 33 by pressing a metal mold 41 having a V-shaped cross-section on the surface of the ceramic green sheet 39 mounted on the lower punch 40 having a, As shown in FIG. 6B, the ceramic green sheet 39 is punched at a predetermined position on the divided groove 32 in the lateral direction with a punching pin 42 having a cylindrical tip surface to form a plurality of through holes 35, and then a ceramic green sheet 39. Was manufactured by firing (Japanese Patent Laid-Open No. 10-15682).
(See Japanese Patent Publication No. 1).

【0005】[0005]

【発明が解決しようとする課題】ところで、打ち抜きピ
ン42により分割溝32上に貫通孔35を打ち抜く際、
セラミックグリーンシート39には貫通孔35が広がる
方向に引っ張り応力が発生するが、分割溝32の延設方
向に発生する引っ張り応力については、分割溝32の形
成によって密度が高くなっているため、貫通孔35の形
状に殆ど影響を及ぼすことがなく、また、分割溝32に
対して垂直方向に発生する引っ張り応力については、隣
り合う分割溝35上に貫通孔35を形成する際に生じる
応力によって互いに打ち消し合うように働くため、貫通
孔35の形状に殆ど影響を及ぼすことがない。
By the way, when the through hole 35 is punched on the dividing groove 32 by the punching pin 42,
A tensile stress is generated in the ceramic green sheet 39 in the direction in which the through hole 35 expands, but the tensile stress generated in the extending direction of the dividing groove 32 is high due to the formation of the dividing groove 32. There is almost no influence on the shape of the holes 35, and the tensile stresses generated in the vertical direction with respect to the division grooves 32 are mutually different due to the stress generated when the through holes 35 are formed on the adjacent division grooves 35. Since they work so as to cancel each other, the shape of the through hole 35 is hardly affected.

【0006】しかしながら、最外に位置する分割溝32
a上の貫通孔35aには、貫通孔35aの一部がかかる
ダミー部側より引っ張り応力が作用しないため、最外に
位置する分割溝32a上に形成する貫通孔35aの形状
だけ図7に示すような楕円状に変形するといった課題が
あった。
However, the outermost dividing groove 32 is provided.
Since the tensile stress does not act on the through hole 35a on the a side from the dummy portion side on which a part of the through hole 35a is applied, only the shape of the through hole 35a formed on the outermost dividing groove 32a is shown in FIG. There was a problem that it was transformed into such an elliptical shape.

【0007】その為、この後の端面電極膜15の形成時
において、最外に位置する分割溝32a上の貫通孔35
には、均一な膜厚を持った端面電極膜15を形成するこ
とができず、酷い時には不良品となるため、歩留りを向
上させることができないといった課題があった。
Therefore, when the end face electrode film 15 is formed thereafter, the through hole 35 on the outermost dividing groove 32a is formed.
However, the end face electrode film 15 having a uniform film thickness cannot be formed, and in a severe case, the end face electrode film 15 becomes a defective product, so that the yield cannot be improved.

【0008】[0008]

【課題を解決するための手段】そこで、本発明は上記課
題に鑑み、セラミック基板の少なくとも一方の主面に縦
横に形成された分割溝と、上記縦方向又は横方向のいず
れか一方の分割溝上に等間隔で穿孔された複数の貫通孔
を備え、最外に位置する縦横の分割溝で仕切られた領域
を製品部、最外に位置する縦横の分割溝からセラミック
基板の外辺までの領域をダミー部とした多連チップ抵抗
器用セラミック基板において、貫通孔が形成されている
最外に位置する分割溝の外側に、上記最外に位置する分
割溝上の貫通孔と同等の間隔で複数のダミー孔を設けた
ことを特徴とする。
SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a dividing groove vertically and horizontally formed on at least one main surface of a ceramic substrate and a dividing groove on either the vertical direction or the horizontal direction. The product part is an area partitioned by vertical and horizontal dividing grooves located at the outermost side, and a region from the outermost vertical and horizontal dividing grooves to the outer edge of the ceramic substrate. In a ceramic substrate for multiple chip resistors having a dummy portion, a plurality of through holes are formed outside the outermost dividing groove in which the through hole is formed, at intervals equal to those of the through hole on the outermost dividing groove. It is characterized in that a dummy hole is provided.

【0009】なお、上記ダミー孔と最外に位置する分割
溝上の貫通孔との最短距離は、製品部の隣り合う分割溝
上に形成された貫通孔間の間隔と同等とすることが好ま
しい。
The shortest distance between the dummy hole and the through hole on the outermost dividing groove is preferably equal to the distance between the through holes formed on the adjacent dividing grooves of the product portion.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施形態について
説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

【0011】図1は本発明の多連チップ抵抗器用セラミ
ック基板の一例を示す平面図である。
FIG. 1 is a plan view showing an example of a ceramic substrate for multiple chip resistors according to the present invention.

【0012】この多連チップ抵抗器用セラミック基板1
は、セラミック基板1の少なくとも一方の主面に横方向
の分割溝2と縦方向の分割溝3を有し、上記横方向の分
割溝2上に等間隔で穿孔された複数の貫通孔5を備え、
最外に位置する縦横の分割溝2a,3aで仕切られた領
域を製品部4、最外に位置する縦横の分割溝2a,3a
からセラミック基板1の外辺1a,1bまでの領域をダ
ミー部6としてある。
This ceramic substrate 1 for multiple chip resistors
Has a horizontal dividing groove 2 and a vertical dividing groove 3 on at least one main surface of the ceramic substrate 1, and has a plurality of through holes 5 formed on the horizontal dividing groove 2 at equal intervals. Prepare,
The area partitioned by the outermost vertical and horizontal dividing grooves 2a and 3a is the product portion 4, and the outermost vertical and horizontal dividing grooves 2a and 3a.
To the outer edges 1a and 1b of the ceramic substrate 1 are used as the dummy portion 6.

【0013】多連チップ抵抗器用セラミック基板1を形
成するセラミックスとしては、特に限定するものではな
く、アルミナ、ジルコニア、ムライト、窒化珪素、窒化
アルミニウム等を主成分とするセラミック焼結体を用い
ることができる。なお、各分割溝2,3の断面形状はV
字状としてあり、また、貫通孔5の平面形状は円形とし
てある。
The ceramic forming the ceramic substrate 1 for multiple chip resistors is not particularly limited, and a ceramic sintered body containing alumina, zirconia, mullite, silicon nitride, aluminum nitride or the like as a main component is used. it can. The sectional shape of each of the dividing grooves 2 and 3 is V
The through hole 5 has a circular shape in plan view.

【0014】そして、本発明の多連チップ抵抗器用セラ
ミック基板1では、貫通孔5aが形成されている最外に
位置する分割溝2aの外側に、即ち最外に位置する横方
向の分割溝2a上の貫通孔5aの一部がかかるダミー部
6aに、最外に位置する分割溝2a上の貫通孔5aと同
等の間隔で複数のダミー孔7を穿孔したことを特徴とす
る。
In the ceramic substrate 1 for multiple chip resistors of the present invention, the lateral dividing groove 2a is located outside the outermost dividing groove 2a in which the through hole 5a is formed, that is, the outermost dividing groove 2a. A plurality of dummy holes 7 are formed in the dummy portion 6a, which covers a part of the upper through hole 5a, at intervals equal to those of the through hole 5a on the outermost dividing groove 2a.

【0015】即ち、図1に示す多連チップ抵抗器用セラ
ミック基板1を製造するには、まず、セラミックグリー
ンシートを用意し、図2(a)に示すように、複数の孔
20aを有する下パンチ20上に載せたセラミックグリ
ーンシート9の表面に、断面形状がV字状をした刃先部
を有する金型21を押し当てて縦横の分割溝を形成した
後、図2(b)に示すように、横方向の分割溝2上の所
定位置を、先端面が平坦な円柱状をした打ち抜きピン2
2で打ち抜いて複数の貫通孔5を穿孔するのであるが、
この時、最外に位置する横方向の分割溝2a上に形成す
る貫通孔5aの一部がかかるダミー部6aにも打ち抜き
ピン23によって最外に位置する分割溝2a上の貫通孔
5aと同等の間隔で複数のダミー部7を穿孔することに
より、最外に位置する分割溝2a上の貫通孔5aに対
し、分割溝2aに垂直な方向の引っ張り応力を両側から
作用させることができるため、貫通孔5aの変形を防
ぎ、図3に示すように、他の貫通孔5と同様に平面形状
を円形とすることができる。
That is, in order to manufacture the ceramic substrate 1 for multiple chip resistors shown in FIG. 1, first, a ceramic green sheet is prepared and, as shown in FIG. 2 (a), a lower punch having a plurality of holes 20a. After the die 21 having a V-shaped cross-section is pressed against the surface of the ceramic green sheet 9 placed on 20 to form vertical and horizontal dividing grooves, as shown in FIG. A punching pin 2 having a cylindrical shape with a flat tip surface at a predetermined position on the lateral dividing groove 2.
2 is punched out to form a plurality of through holes 5,
At this time, the punching pin 23 is equivalent to the through hole 5a on the outermost dividing groove 2a by the punching pin 23 even on a part of the through hole 5a formed on the outermost lateral dividing groove 2a. By punching the plurality of dummy portions 7 at intervals of, the tensile stress in the direction perpendicular to the dividing groove 2a can be applied from both sides to the through hole 5a on the dividing groove 2a located on the outermost side. The deformation of the through hole 5a can be prevented, and as shown in FIG. 3, the planar shape can be made circular like the other through holes 5.

【0016】その為、分割溝2,3と貫通孔5を形成し
たセラミックグリーンシート9を所定の温度で焼成する
ことにより、製品部4に形成される全ての貫通孔5の寸
法精度を安定させることができるため、端面電極膜の形
成時における成膜不良を防ぎ、不良品の発生をなくすこ
とができることから、歩留りを向上させることができ
る。
Therefore, by firing the ceramic green sheet 9 having the division grooves 2 and 3 and the through holes 5 at a predetermined temperature, the dimensional accuracy of all the through holes 5 formed in the product portion 4 is stabilized. Therefore, it is possible to prevent film formation defects during the formation of the end face electrode film and eliminate the generation of defective products, so that the yield can be improved.

【0017】ところで、このような効果を奏するために
は、ダミー部6aに形成するダミー孔7と最外に位置す
る横方向の分割溝2a上に形成する貫通孔5aとの最短
距離Lは、製品部4の隣り合う分割溝2上に形成された
貫通孔5間の間隔Wに近づけることが好ましく、望まし
くは同等とすることが好ましい。
In order to achieve such an effect, the shortest distance L between the dummy hole 7 formed in the dummy portion 6a and the through hole 5a formed on the outermost lateral dividing groove 2a is: It is preferable that the distance W between the through holes 5 formed on the adjacent division grooves 2 of the product portion 4 is close to, and preferably equal to each other.

【0018】なぜなら、ダミー孔7と貫通孔5aとの最
短距離Lが、製品部4の隣り合う分割溝2上に形成され
た貫通孔5間の間隔Wより大きくなったり、小さくなり
過ぎると、打ち抜きピン22により最外に位置する横方
向の分割溝2a上に貫通孔5aを穿孔する際、製品部側
から作用する引っ張り応力とダミー部側から作用する引
っ張り応力の大きさに差があるため、相互に相殺させる
ことができず、最外に位置する横方向の分割溝2a上に
形成する貫通孔5aの寸法を安定させることができない
からで、ダミー孔7と貫通孔5aとの最短距離Lを、製
品部4の隣り合う分割溝2上に形成された貫通孔5間の
間隔Wと同等とすることで、製品部側から作用する引っ
張り応力とダミー部側から作用する引っ張り応力の大き
さを等しくし、互いの引っ張り応力を相殺することがで
きるため、最外に位置する横方向の分割溝2a上に形成
する貫通孔5aの寸法を安定させることができる。
This is because if the shortest distance L between the dummy hole 7 and the through hole 5a becomes larger or smaller than the interval W between the through holes 5 formed on the adjacent dividing grooves 2 of the product portion 4, it becomes too small. When punching the through hole 5a on the outermost lateral dividing groove 2a by the punching pin 22, there is a difference between the tensile stress acting from the product part side and the tensile stress acting from the dummy part side. , The dimensions of the through holes 5a formed on the outermost lateral dividing grooves 2a cannot be stabilized, and thus the shortest distance between the dummy holes 7 and the through holes 5a. By setting L to be equal to the interval W between the through holes 5 formed on the adjacent division grooves 2 of the product portion 4, the tensile stress acting from the product portion side and the tensile stress acting from the dummy portion side are large. Equality and mutual It is possible to offset the tensile stress, the dimensions of the through holes 5a to be formed in the lateral direction of the dividing groove 2a on which is located outermost can be stabilized.

【0019】なお、本発明において、ダミー孔7と貫通
孔5aとの最短距離Lが、製品部4の隣り合う分割溝2
上に形成された貫通孔5間の間隔Wと同等であるとは、
貫通孔5間の間隔Wを1とした時、最短距離Lが間隔W
に対して0.8〜1.2の範囲内にある場合を言う。
In the present invention, the shortest distance L between the dummy hole 7 and the through hole 5a is determined by the adjacent division grooves 2 of the product portion 4.
The same as the distance W between the through holes 5 formed above means that
When the distance W between the through holes 5 is 1, the shortest distance L is the distance W.
To 0.8 to 1.2.

【0020】以上、本発明の実施形態について示した
が、本発明は上述した実施形態だけに限定されるもので
はなく、例えば、貫通孔5の平面形状としては円形をし
たものだけに限らず、楕円形、菱形や正方形等の四角形
をしたものでも良く、また、分割性を考慮してダミー部
6にダミーの分割溝を形成してもかまわない。
Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and for example, the planar shape of the through hole 5 is not limited to the circular shape. The shape may be an ellipse, a rhombus, a quadrangle such as a square, or a dummy dividing groove may be formed in the dummy portion 6 in consideration of the dividing property.

【0021】このように、本発明の要旨を逸脱しない範
囲であれば、改良や変更したものにも適用できることは
言う迄もない。
As described above, it goes without saying that the invention can be applied to the modified and modified ones without departing from the scope of the invention.

【0022】[0022]

【実施例】ここで、図1に示す本発明の多連チップ抵抗
器用セラミック基板1と、図5に示す従来の多連チップ
抵抗器用セラミック基板31を各々20枚ずつ製作し、
最外に位置する横方向の分割溝2a,32a上に形成す
る貫通孔5a,35aの寸法精度について比較する実験
を行った。
EXAMPLES Here, 20 ceramic chip substrates for multiple chip resistors 1 of the present invention shown in FIG. 1 and 20 ceramic substrate chips for conventional multiple chip resistors shown in FIG.
An experiment was conducted to compare the dimensional accuracy of the through holes 5a and 35a formed on the outermost lateral dividing grooves 2a and 32a.

【0023】また、本発明の多連チップ抵抗器用セラミ
ック基板1においては、最外に位置する横方向の分割溝
2a上に形成する貫通孔5aからダミー部6aに形成す
るダミー孔7までの最短距離Lを異ならせたものも用意
し、同様に実験を行った。
Further, in the ceramic substrate 1 for multiple chip resistors of the present invention, the shortest distance from the through hole 5a formed on the outermost lateral dividing groove 2a to the dummy hole 7 formed on the dummy portion 6a. The same experiment was conducted by preparing those having different distances L.

【0024】本実験に用いる多連チップ抵抗器用セラミ
ック基板1,31は、いずれもアルミナ含有量が96重
量%のアルミナセラミックスにより形成し、その外辺寸
法が60.0×51.2mm、板厚が0.37mmの板
状体とした。
Each of the ceramic substrates 1 and 31 for multiple chip resistors used in this experiment was made of alumina ceramics having an alumina content of 96% by weight, and the outer side dimension was 60.0 × 51.2 mm and the plate thickness was Was 0.37 mm.

【0025】そして、分割により取り出す多連チップ抵
抗器は4連とするとともに、その外辺寸法を2.0mm
×1.0mmとし、板状体の長辺方向に46列、短辺方
向に16列形成されるように縦横の分割溝2,3,3
2,33を形成するとともに、横方向の分割溝2,32
上には合計で3008個の貫通孔5,35を穿孔するよ
うにして従来の多連チップ抵抗器用セラミック基板31
を製作した。
The multiple chip resistors taken out by division are four in series, and the outside dimension is 2.0 mm.
× 1.0 mm, and the vertical and horizontal dividing grooves 2, 3, 3 are formed so that 46 rows are formed in the long side direction and 16 rows are formed in the short side direction of the plate-shaped body.
2 and 33 are formed, and lateral division grooves 2 and 32 are formed.
A total of 3008 through holes 5 and 35 are formed on the upper surface of the conventional ceramic substrate 31 for a multiple chip resistor.
Was produced.

【0026】また、本発明の多連チップ抵抗器用セラミ
ック基板1にあっては、最外に位置する横方向の分割溝
2a上に形成される貫通孔5aの一部がかかるダミー部
6aに、最外に位置する分割溝2a上の貫通孔5aと同
等の間隔で複数のダミー孔7を穿孔して形成した。
Further, in the ceramic substrate 1 for multiple chip resistors of the present invention, the dummy portion 6a to which a part of the through hole 5a formed on the outermost lateral dividing groove 2a is applied, A plurality of dummy holes 7 are formed at the same intervals as the through holes 5a on the outermost divided groove 2a.

【0027】ただし、いずれも貫通孔5,35及びダミ
ー孔7の平面形状を円形とし、その穴径は0.14mm
とした。
However, in both cases, the through holes 5, 35 and the dummy hole 7 have a circular plane shape, and the hole diameter is 0.14 mm.
And

【0028】そして、図3及び図7に示すように、最外
に位置する横方向の分割溝2a,32a上の貫通孔5
a,35aの延設方向における径(X)と貫通孔5a,
35aに垂直な方向における径(Y)とを測定し、長短
差を算出することにより貫通孔5a,35aの真円度を
評価するようにした。
Then, as shown in FIGS. 3 and 7, the through hole 5 on the outermost lateral dividing grooves 2a and 32a is formed.
a, 35a diameter (X) in the extending direction and through hole 5a,
The diameter (Y) in the direction perpendicular to 35a is measured, and the roundness of the through holes 5a and 35a is evaluated by calculating the length difference.

【0029】結果は表1に示す通りである。The results are shown in Table 1.

【0030】[0030]

【表1】 [Table 1]

【0031】この結果、表1により判るように、ダミー
孔を持たない従来の多連チップ抵抗器用セラミック基板
31は、最外に位置する貫通孔35aの長短差は最大で
0.028mmもあった。
As a result, as can be seen from Table 1, in the conventional ceramic substrate 31 for multiple chip resistors having no dummy hole, the maximum difference in length of the through hole 35a located at the outermost side was 0.028 mm. .

【0032】これに対し、本発明の多連チップ抵抗器用
セラミック基板1はダミー孔7を形成するようにしたこ
とにより、従来の多連チップ抵抗器用セラミック基板3
1と比較して最外に位置する貫通孔5aの長短差を小さ
くできることが判る。
On the other hand, in the ceramic substrate for multiple chip resistors 1 of the present invention, the dummy holes 7 are formed, so that the conventional ceramic substrate for multiple chip resistors 3 is formed.
It can be seen that the difference in length between the outermost through holes 5a can be made smaller than that of No. 1.

【0033】また、製品部4の隣り合う分割溝2上の貫
通孔5間の間隔Wを1とした時の最外の貫通孔5aから
ダミー孔7までの最短距離Lを0.8〜1.2とするこ
とにより、最外に位置する貫通孔5aの長短差の最大値
を0.01mm以下とすることができ、特に優れてい
た。
When the distance W between the through holes 5 on the adjacent dividing grooves 2 of the product portion 4 is 1, the shortest distance L from the outermost through hole 5a to the dummy hole 7 is 0.8 to 1. The maximum value of the difference in length of the through holes 5a located at the outermost part can be set to 0.01 mm or less by setting to be 0.2, which was particularly excellent.

【0034】[0034]

【発明の効果】以上のように、本発明によれば、セラミ
ック基板の少なくとも一方の主面に縦横に形成された分
割溝と、上記縦方向又は横方向のいずれか一方の分割溝
上に等間隔で穿孔された複数の貫通孔を備え、最外に位
置する縦横の分割溝で仕切られた領域を製品部、最外に
位置する縦横の分割溝からセラミック基板の外辺までの
領域をダミー部とした多連チップ抵抗器用セラミック基
板において、最外に位置する分割溝上の貫通孔の一部が
かかるダミー部に、最外に位置する分割溝上の貫通孔と
同等の間隔で複数のダミー孔を設けたことによって、最
外に位置する分割溝上の貫通孔の変形を抑え、他の貫通
孔と同程度の寸法精度に保つことができる。特に、上記
ダミー孔と最外に位置する分割溝上の貫通孔との最短距
離を、製品部の隣り合う分割溝上に形成された貫通孔間
の間隔と同等とすることで、最外に位置する分割溝上の
貫通孔の寸法をより安定させることができる。
As described above, according to the present invention, the dividing grooves formed in the vertical and horizontal directions on at least one main surface of the ceramic substrate and the equal intervals on the dividing grooves in either the vertical direction or the horizontal direction. It has a plurality of through holes perforated with the product. In the multiple chip resistor ceramic substrate described above, a plurality of dummy holes are provided at the same interval as the through holes on the outermost divided groove in the dummy part where a part of the through hole on the outermost divided groove is applied. By providing the through holes, it is possible to suppress the deformation of the through holes on the outermost dividing grooves and maintain the dimensional accuracy to the same level as that of the other through holes. In particular, by positioning the shortest distance between the dummy hole and the through hole on the outermost dividing groove to be the same as the distance between the through holes formed on the adjacent dividing grooves of the product part, the outermost portion is positioned. The size of the through hole on the dividing groove can be made more stable.

【0035】その為、多連チップ抵抗器用セラミック基
板を用いれば、不良品を発生させることがなく、製品部
より良品の多連チップ抵抗器を取り出すことができる。
Therefore, if the ceramic substrate for multiple chip resistors is used, it is possible to take out good multiple chip resistors from the product section without generating defective products.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の多連チップ抵抗器用セラミック基板の
一例を示す平面図である。
FIG. 1 is a plan view showing an example of a ceramic substrate for multiple chip resistors according to the present invention.

【図2】(a)(b)は本発明の多連チップ抵抗器用セ
ラミック基板の製造工程を説明するための断面図であ
る。
2A and 2B are cross-sectional views for explaining a manufacturing process of the ceramic substrate for multiple chip resistors of the present invention.

【図3】本発明の多連チップ抵抗器用セラミック基板の
最外に位置する分割溝上に形成された貫通孔を拡大した
平面図である。
FIG. 3 is an enlarged plan view of a through hole formed on the outermost dividing groove of the ceramic substrate for multiple chip resistors of the present invention.

【図4】一般的な多連チップ抵抗器を示す斜視図であ
る。
FIG. 4 is a perspective view showing a general multiple chip resistor.

【図5】従来の多連チップ抵抗器用セラミック基板の一
例を示す平面図である。
FIG. 5 is a plan view showing an example of a conventional ceramic substrate for multiple chip resistors.

【図6】(a)(b)は従来の多連チップ抵抗器用セラ
ミック基板の製造工程を説明するための断面図である。
6A and 6B are cross-sectional views for explaining a manufacturing process of a conventional ceramic substrate for multiple chip resistors.

【図7】従来の多連チップ抵抗器用セラミック基板の最
外に位置する分割溝上に形成された貫通孔を拡大した平
面図である。
FIG. 7 is an enlarged plan view of a through hole formed on an outermost division groove of a conventional ceramic substrate for multiple chip resistors.

【符号の説明】[Explanation of symbols]

1:多連チップ抵抗器用セラミック基板 2:横方向の分割溝 2a:最外に位置する横方向の分割溝 3:縦方向の分割溝 3a:最外に位置する縦方向の分割溝 4:製品部 5:貫通孔 5a:最外に位置する分割溝上の貫通孔 6:ダミー部 6a:最外に位置する分割溝上の貫通孔の一部がかかる
ダミー部 7:ダミー孔 9:セラミックグリーンシート 10:多連チップ抵抗器 11:セラミック基板 12:凹部 13:抵抗体膜 14:保護膜 15:端面電極膜 20:下パンチ 20a:孔 21:金型 22,23:打ち抜きパンチ
1: Ceramic substrate for multiple chip resistors 2: Lateral dividing groove 2a: Outermost lateral dividing groove 3: Vertical dividing groove 3a: Outermost vertical dividing groove 4: Product Part 5: Through hole 5a: Through hole on the outermost dividing groove 6: Dummy part 6a: Part of the through hole on the outermost dividing groove is applied Dummy part 7: Dummy hole 9: Ceramic green sheet 10 : Multiple chip resistor 11: Ceramic substrate 12: Recessed portion 13: Resistor film 14: Protective film 15: End face electrode film 20: Lower punch 20a: Hole 21: Die 22, 23: Punch punch

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】セラミック基板の少なくとも一方の主面に
縦横に形成された分割溝と、上記縦方向又は横方向のい
ずれか一方の分割溝上に等間隔で穿孔された複数の貫通
孔を備え、最外に位置する縦横の分割溝で仕切られた領
域を製品部、最外に位置する縦横の分割溝からセラミッ
ク基板の外辺までの領域をダミー部とした多連チップ抵
抗器用セラミック基板において、貫通孔が形成されてい
る最外に位置する分割溝の外側に、上記最外に位置する
分割溝上の貫通孔と同等の間隔で複数のダミー孔を設け
たことを特徴とする多連チップ抵抗器用セラミック基
板。
1. A ceramic substrate is provided with dividing grooves formed in at least one main surface in a vertical and horizontal direction, and a plurality of through holes formed in the dividing groove in either the vertical direction or the horizontal direction at equal intervals. In the ceramic board for multiple chip resistors, the area partitioned by the vertical and horizontal dividing grooves located at the outermost is the product section, and the area from the outermost vertical and horizontal dividing grooves to the outer side of the ceramic board is the dummy section. A multiple chip resistor characterized in that a plurality of dummy holes are provided outside the outermost dividing groove in which the through hole is formed, at the same intervals as the through holes on the outermost dividing groove. Ceramic substrate.
【請求項2】上記ダミー孔と最外に位置する分割溝上の
貫通孔との最短距離が、製品部の隣り合う分割溝上に形
成された貫通孔間の間隔と同等であることを特徴とする
請求項1に記載の多連チップ抵抗器用セラミック基板。
2. The shortest distance between the dummy hole and the through hole on the outermost divided groove is equal to the distance between the through holes formed on the adjacent divided grooves of the product portion. The ceramic substrate for multiple chip resistors according to claim 1.
JP2002092547A 2002-03-28 2002-03-28 Ceramic substrate for multiple chip resistors Expired - Fee Related JP3825353B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002092547A JP3825353B2 (en) 2002-03-28 2002-03-28 Ceramic substrate for multiple chip resistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002092547A JP3825353B2 (en) 2002-03-28 2002-03-28 Ceramic substrate for multiple chip resistors

Publications (2)

Publication Number Publication Date
JP2003297616A true JP2003297616A (en) 2003-10-17
JP3825353B2 JP3825353B2 (en) 2006-09-27

Family

ID=29386668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002092547A Expired - Fee Related JP3825353B2 (en) 2002-03-28 2002-03-28 Ceramic substrate for multiple chip resistors

Country Status (1)

Country Link
JP (1) JP3825353B2 (en)

Also Published As

Publication number Publication date
JP3825353B2 (en) 2006-09-27

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