JP2000286511A - Ceramic substrate for electronic component - Google Patents

Ceramic substrate for electronic component

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Publication number
JP2000286511A
JP2000286511A JP11090756A JP9075699A JP2000286511A JP 2000286511 A JP2000286511 A JP 2000286511A JP 11090756 A JP11090756 A JP 11090756A JP 9075699 A JP9075699 A JP 9075699A JP 2000286511 A JP2000286511 A JP 2000286511A
Authority
JP
Japan
Prior art keywords
slit
depth
primary
ceramic substrate
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11090756A
Other languages
Japanese (ja)
Other versions
JP3838810B2 (en
Inventor
Toshiaki Muto
利彰 武藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP09075699A priority Critical patent/JP3838810B2/en
Publication of JP2000286511A publication Critical patent/JP2000286511A/en
Application granted granted Critical
Publication of JP3838810B2 publication Critical patent/JP3838810B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To prevent such division failure as burr from occurring easily and to improve a yield by forming the depth of a site that crosses a primary slit in a secondary slit relatively shallower than the other parts. SOLUTION: A ceramic substrate 1 is provided with a plurality of primary and secondary slits 2 and 3 that orthogonally cross each other as a divided groove, and the depth of the secondary slit 3 being divided later is formed to be shallower at a site that crosses the primary slit 2, namely at a site corresponding to the end part of a simple substance after division, and is relatively deeper at the other parts. Therefore, when the ceramic substrate 1 is to be divided in a rod shape along the primary slit 2, the depth of the secondary slit 3 at a site that crosses the primary slit 2 is formed to be relatively shallower than the depth of the other secondary slit 3, thus preventing a bar bending failure where the secondary slit 3 is divided from occurring easily and improving a yield.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップ状電子部品
の絶縁基板を多数個取りするための分割溝が形成された
電子部品用セラミック基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate for an electronic component in which a dividing groove for forming a large number of insulating substrates for a chip-shaped electronic component is formed.

【0002】[0002]

【従来の技術】現在、チップ抵抗器等のチップ状電子部
品を製造する場合、絶縁材料としてセラミック基板が多
く使用されている。これらの基板には、図3(a)に示
すように、縦横に互いに直交する複数本の分割溝の一次
スリット2並びに二次スリット3が形成されている。こ
の一次スリット2並びに二次スリット3は、図3(b)
に示すように、セラミック基板1の各部において各々の
深さは均一である。
2. Description of the Related Art At present, when manufacturing chip-shaped electronic components such as chip resistors, ceramic substrates are often used as insulating materials. As shown in FIG. 3A, a primary slit 2 and a secondary slit 3 of a plurality of divided grooves which are orthogonal to each other vertically and horizontally are formed on these substrates. The primary slit 2 and the secondary slit 3 are shown in FIG.
As shown in (1), the depth of each part of the ceramic substrate 1 is uniform.

【0003】電子部品の製造工程においては、まず分割
前のセラミック基板1に抵抗体、導体、保護層等を形成
したあと、図4に示すように、直交する分割溝の一次ス
リット2に沿って棒状に分割し、その後、分割されたセ
ラミック基板1の端面に導体を形成し、図5に示すよう
に、セラミック基板1を二次スリット3に沿って単体に
分割することにより、チップ状電子部品となる。
In the manufacturing process of an electronic component, first, a resistor, a conductor, a protective layer, and the like are formed on a ceramic substrate 1 before division, and then, as shown in FIG. A chip-shaped electronic component is formed by dividing the ceramic substrate 1 into rods and then forming a conductor on the end surface of the divided ceramic substrate 1 and dividing the ceramic substrate 1 along the secondary slit 3 as shown in FIG. Becomes

【0004】従来より、一次スリット2の分割の際の分
割不良低減のため、これらの互いに直交する一次スリッ
ト2と二次スリット3の深さは、先に分割する一次スリ
ット2の深さを深くし、後で分割する二次スリット3の
深さは相対的に浅く形成することが行われている。(特
開平3−16704号、特公平5−54241号公報参
照)
Conventionally, the primary slit 2 and the secondary slit 3 which are orthogonal to each other have a greater depth than that of the primary slit 2 which is divided first, in order to reduce the division failure when the primary slit 2 is divided. The secondary slit 3 to be divided later is formed to be relatively shallow. (See JP-A-3-16704 and JP-B-5-54241)

【0005】[0005]

【発明が解決しようとする課題】ところが従来の分割溝
は、一次スリット2および二次スリット3のそれぞれの
深さは、セラミック基板1の各部で均一であり、一次ス
リット2を棒状に分割する際の分割不良を低減するため
に一次スリット2を深く形成すると、セラミック基板1
の製造工程において、一次スリット2のクラックや割れ
により歩留まりの低下となり、またその後の電子部品製
造工程においても割れを生じやすく歩留まりの低下の原
因となっていた。 また、二次スリット3の深さが深すぎると、一次スリッ
ト2の棒状への分割の際に二次スリット3まで分割され
るバー折れ不良という不具合が発生し、反対に二次スリ
ット3の深さが浅いと、二次スリット3の分割の際に綺
麗に分割されずバリ等が発生する原因となっていた。
However, in the conventional dividing groove, the depth of each of the primary slit 2 and the secondary slit 3 is uniform in each part of the ceramic substrate 1, and when the primary slit 2 is divided into a rod shape. When the primary slit 2 is formed deeply to reduce the division failure of the ceramic substrate 1,
In the manufacturing process of (1), cracks and cracks in the primary slit 2 lower the yield, and in the subsequent electronic component manufacturing process, cracks are likely to occur, causing a reduction in the yield. Further, if the depth of the secondary slit 3 is too deep, there occurs a defect that the primary slit 2 is broken into bars when the primary slit 2 is divided into rods. If it is shallow, the secondary slit 3 is not divided neatly when divided, causing burrs and the like.

【0006】[0006]

【課題を解決するための手段】本発明は、これらに鑑み
て行われたもので、縦横に互いに直交する複数本の分割
溝が形成されたチップ状電子部品の絶縁基板を多数個取
りするセラミック基板において、先に分割するための一
次スリットと後で分割するための二次スリットを有し、
該二次スリットに於ける一次スリットと交わる部位の深
さが他の部分よりも相対的に浅く形成されていることを
特徴とするものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has been made in consideration of the above-mentioned problems, and has been made in consideration of the above problem. The substrate has a primary slit for splitting first and a secondary slit for splitting later,
The secondary slit is characterized in that a portion of the secondary slit that intersects with the primary slit is formed relatively shallower than other portions.

【0007】[0007]

【発明の実施の形態】以下に本発明の実施形態について
詳述する。 図1に示すように、本発明のセラミック基板1は、分割
溝として互いに直交する複数の一次スリット2と二次ス
リット3を有しており、これら一次スリット2および二
次スリット3のうち、後で分割される二次スリット3の
深さが一次スリット2と交わる部位、即ち分割後の単体
の端部に相当する部位付近で浅く、他の部分で相対的に
深くなるように形成されている。 このことにより、セラミック基板1を一次スリット2に
沿って棒状に分割する際には、一次スリット2と交わる
部位の二次スリット3の深さが、他の二次スリット3の
深さより相対的に浅く形成されているため二次スリット
3が分割されてしまうバー折れ不良が発生しにくく歩留
まりが向上する。 また、最終的に二次スリット3に沿って単体に分割する
工程においては、二次スリット3の単体の端部付近の深
さは浅いが、他の部分で相対的に深く形成されているた
め、バリ等の分割不良が発生しにくく歩留まりが向上す
る。 一次スリット2並びに二次スリット3の深さの好ましい
範囲は、図2(a)で説明すると、セラミック基板1の
厚みT、一次スリット2の深さD1、二次スリット3の
最深部の深さD2、二次スリット3の最浅部の深さD3
としたとき、 D1=0.25T〜0.55T、D2<D
1、D2=0.15T〜0.45T、D3<D2、D3
=0.08T〜0.25Tである。 これは、一次スリット2の深さD1が0.55Tより大
きいと、セラミック基板1の製造工程並びに電子部品の
分割前までの工程においてクラックや割れが発生しやす
く、またD1が0. 25Tより小さいと、一次スリット
2の分割の際に容易に分割出来ないため、D1=0.2
5T〜0. 55Tの範囲が好ましい。これに対し、二次
スリット3の最深部の深さD2は、一次スリット2の分
割の際に二次スリット3まで分割されるバー折れ不良を
防止するために、D2<D1とし、0.45Tより大き
いとバー折れ不良となりやすくまた、0.15Tより小
さいと単体の端部へバリが発生するため、 D2=0. 1
5T〜0. 45Tが好ましい範囲である。また二次スリ
ット3の最浅部の深さD3は、 D3<D2とし、 0.2
5Tより深いとバー折れ不良となりやすく、 0. 08T
より小さいと単体の端部へバリが発生しやすいため、D
3=0. 08T〜0. 25Tの範囲とすることが好まし
い。また、二次スリット3の形状は図2(a)に示すよ
うに逆放物線状に深くなることが好ましいが、図2
(b)に示すように矩形状に深くなる形状、もしくは、
図2(c)に示すように一次スリット2と交わる部位か
らC面状に深くなる形状でも良い。この場合に於いて
は、一次スリット2間のピッチL、矩形状の二次スリッ
ト3の最浅部の長さL1、 C面状の二次スリット3の最
浅部からのC面の長さL2としたとき、L1=L2=
0. 1L〜0. 2Lで最大値は2.0mm以下であるこ
とが好ましい。
Embodiments of the present invention will be described below in detail. As shown in FIG. 1, the ceramic substrate 1 of the present invention has a plurality of primary slits 2 and secondary slits 3 orthogonal to each other as division grooves. The secondary slit 3 is formed so that the depth of the secondary slit 3 is shallow near the part where the primary slit 2 intersects with the primary slit 2, that is, near the part corresponding to the end of the single body after division, and relatively deep in other parts. . Accordingly, when the ceramic substrate 1 is divided into rods along the primary slits 2, the depth of the secondary slits 3 at the portion intersecting with the primary slits 2 is relatively larger than the depths of the other secondary slits 3. Since the secondary slit 3 is formed to be shallow, bar breakage failure in which the secondary slit 3 is divided hardly occurs, and the yield is improved. In addition, in the step of finally dividing the single body along the secondary slit 3, the depth near the end of the single body of the secondary slit 3 is shallow, but is relatively deep in other portions. In addition, a division failure such as burrs does not easily occur, and the yield is improved. The preferred ranges of the depths of the primary slit 2 and the secondary slit 3 are, as described with reference to FIG. 2A, the thickness T of the ceramic substrate 1, the depth D1 of the primary slit 2, and the depth of the deepest part of the secondary slit 3. D2, the depth D3 of the shallowest part of the secondary slit 3
D1 = 0.25T to 0.55T, D2 <D
1, D2 = 0.15T to 0.45T, D3 <D2, D3
= 0.08T to 0.25T. This is because if the depth D1 of the primary slit 2 is larger than 0.55T, cracks and cracks are likely to occur in the steps of manufacturing the ceramic substrate 1 and the steps before dividing the electronic component, and D1 is smaller than 0.25T. D1 = 0.2 because the primary slit 2 cannot be easily divided at the time of division.
A range of 5T to 0.55T is preferred. On the other hand, the depth D2 of the deepest part of the secondary slit 3 is set to D2 <D1 and 0.45T in order to prevent a bar break defect that is divided up to the secondary slit 3 when the primary slit 2 is divided. If it is larger, the bar is likely to be broken, and if it is smaller than 0.15T, burrs will be generated at the end of the single body. D2 = 0.1
5T to 0.45T is a preferable range. The depth D3 of the shallowest part of the secondary slit 3 is D3 <D2, and 0.2
If it is deeper than 5T, it is easy for the bar to be broken.
If it is smaller, burrs are likely to be generated at the end of the single unit.
It is preferable that 3 = 0.08T to 0.25T. Also, the shape of the secondary slit 3 is preferably deep in a reverse parabolic shape as shown in FIG.
A shape that becomes deeper in a rectangular shape as shown in (b), or
As shown in FIG. 2 (c), a shape that is deeper in a C plane shape from a portion intersecting with the primary slit 2 may be used. In this case, the pitch L between the primary slits 2, the length L1 of the shallowest portion of the rectangular secondary slit 3, the length of the C surface from the shallowest portion of the C-shaped secondary slit 3 When L2, L1 = L2 =
It is preferable that the maximum value is 0.1 mm to 0.2 L and the maximum value is 2.0 mm or less.

【0008】これは、矩形状の二次スリット3の最浅部
の長さL1または、C面状の二次スリット3の最浅部か
らのC面の長さL2が0.1Lより小さいと、一次スリ
ット2の分割の際に二次スリット3まで分割されるバー
折れ不良となりやすく、反対に0. 2Lより大きいと単
体に分割する二次スリット3の分割の際に、バリ等が発
生し分割不良となるためである。 以上のように本発明では一次スリット2の深さD1は、
セラミック基板1の製造工程並びに電子部品の分割前迄
の工程で、クラックや割れが発生しない範囲で深めの設
定とし、セラミック基板1のどの箇所でも一次スリット
2の深さD1は均一としている。二次スリット3の最深
部の深さD2は、一次スリット2の深さD1に比較し僅
かに浅めとし、単体に分割する際の分割性を落とさず単
体の端部へのバリ発生を防止しうる値としている。また
二次スリット3の最浅部の深さD3並びに、二次スリッ
ト3の矩形状における二次スリット3の最浅部の長さL
1および、二次スリット3のC面状の形状における二次
スリット3の最浅部からのC面の長さL2は、一次スリ
ット2の分割の際に二次スリット3迄分割されるバー折
れ不良と、単体に分割する二次スリット3の分割の際に
単体端部へのバリ等の発生を防止しうる値としている。 また一次スリット2、二次スリット3の先端角は30〜
60°の範囲としておくことが好ましい。
This is because when the length L1 of the shallowest portion of the rectangular secondary slit 3 or the length L2 of the C-plane from the shallowest portion of the C-shaped secondary slit 3 is smaller than 0.1L. However, when the primary slit 2 is divided, the bar that is divided into the secondary slits 3 is liable to be broken. Conversely, when it is larger than 0.2 L, burrs are generated when the secondary slit 3 is divided into single pieces. This is because division failure occurs. As described above, in the present invention, the depth D1 of the primary slit 2 is
In the manufacturing process of the ceramic substrate 1 and the process before the division of the electronic components, the depth is set to be deep as long as cracks and cracks do not occur, and the depth D1 of the primary slit 2 is uniform at any part of the ceramic substrate 1. The depth D2 of the deepest part of the secondary slit 3 is made slightly shallower than the depth D1 of the primary slit 2 to prevent the occurrence of burrs at the end of the single unit without lowering the dividability at the time of dividing the unit. Value. Also, the depth D3 of the shallowest part of the secondary slit 3 and the length L of the shallowest part of the secondary slit 3 in the rectangular shape of the secondary slit 3
1 and the length L2 of the C-plane from the shallowest part of the secondary slit 3 in the C-plane shape of the secondary slit 3 is a bar break that is divided up to the secondary slit 3 when the primary slit 2 is divided. It is set to a value that can prevent the occurrence of burrs and the like at the end of the single unit when the secondary slit 3 is divided into the unit and the defective unit. The tip angles of the primary slit 2 and the secondary slit 3 are 30 to
It is preferable to set the range to 60 °.

【0009】本発明のセラミック基板1の材質は、アル
ミナの外、窒化アルミニウム、炭化珪素などを主成分と
するセラミックス、またはガラスセラミック等に適用で
き、その製造方法は、金型に備えられた刃をセラミック
グリーンシートに押し当てて一次スリット2並びに二次
スリット3を形成し、その後所定の温度で焼成し製造さ
れる。該二次スリット3の逆放物線状または矩形状また
はC面状の形状は、二次スリット3用の刃をその形状に
加工したものを使用する。 本発明のセラミック基板1は、所定のパターンで導体な
どを印刷し分割することによって、最終的にチップ抵抗
器等の電子部品を製造することができる。
The material of the ceramic substrate 1 of the present invention can be applied not only to alumina but also to ceramics mainly composed of aluminum nitride, silicon carbide or the like, or glass ceramics. Is pressed against a ceramic green sheet to form a primary slit 2 and a secondary slit 3, and then fired at a predetermined temperature to manufacture. As the inverted parabolic, rectangular, or C-plane shape of the secondary slit 3, a blade obtained by processing a blade for the secondary slit 3 into the shape is used. The ceramic substrate 1 of the present invention can finally produce an electronic component such as a chip resistor by printing and dividing a conductor or the like in a predetermined pattern.

【0010】[0010]

【実施例】Al2 3 含有率96%のセラミックグリー
ンシートに、金型に備えられた刃を押し当てて分割溝を
形成しその後所定の温度で焼成することによりセラミッ
ク基板1を作製した。本発明実施例および従来品比較例
のセラミック基板1について、それぞれ一次スリット2
並びに二次スリット3の深さと、セラミック基板1の製
造工程に於けるクラック、割れ不良、一次スリット2並
びに二次スリット3の分割不良について調べた結果を表
1に示す。 尚、本発明実施例並びに従来品比較例共、焼成後のセラ
ミック基板1の厚みは0.4mmで、一次スリット2間
のピッチLは2. 0mmである。またスリットの深さの
測定はマジック(登録商標)インクにてスリットに着色
浸透後分割し、工具顕微鏡でその分割断面の着色部分の
深さを測定した。このスリットの深さは各所において
0. 01mm程度のバラツキがあるため、任意の10箇
所の測定値の平均値で表記した。また、クラック、割れ
不良並びに一次スリット2並びに二次スリット3の分割
不良の評価は、各各200シートの試料における従来品
比較例の最も悪い不良率を×とし、この不良率に対し低
減出来たものの半減を超えるものを△とし、半減以下と
なった良好なものを○と評価した。
EXAMPLES] Al 2 O 3 content of 96% of the ceramic green sheets to prepare a ceramic substrate 1 by subsequently forming the dividing grooves by pressing a blade provided in the mold fired at a predetermined temperature. With respect to the ceramic substrates 1 of the embodiment of the present invention and the comparative example of the prior art,
Table 1 shows the depth of the secondary slit 3, cracks and cracks in the manufacturing process of the ceramic substrate 1, and the division of the primary slit 2 and the secondary slit 3. The thickness of the fired ceramic substrate 1 is 0.4 mm, and the pitch L between the primary slits 2 is 2.0 mm in both the present invention example and the conventional product comparative example. Further, the depth of the slit was measured by coloring the slit with Magic (registered trademark) ink, penetrating the slit, dividing the slit, and measuring the depth of the colored portion of the divided cross section with a tool microscope. Since the depth of the slit has a variation of about 0.01 mm in each place, it is represented by an average value of measured values at arbitrary 10 places. In addition, the evaluation of cracking, cracking failure, and division failure of the primary slit 2 and the secondary slit 3 was evaluated as x with the worst defective rate of the comparative example of the conventional product in each 200 sheet sample, and could be reduced with respect to this defective rate. Those that exceeded half of the product were evaluated as Δ, and those that were less than half the evaluation were evaluated as O.

【0011】[0011]

【表1】 [Table 1]

【0012】比較例である従来品のセラミック基板1
は、通常設定する一次スリット2並びに二次スリット3
の深さの範囲内でそれぞれ変化させたものを作製し評価
した。従来品Aは、一次スリット2の深さD1を0.
19mm、二次スリット3の最深部の深さD2を0. 0
7mmとし、いずれも各部における深さは均一としたも
ので、セラミック基板1の製造工程におけるクラックや
割れの発生並びに一次スリット2の分割不良はなかった
ものの、二次スリット3の分割の際に単体端部へのバリ
の発生がみられた。また、従来品Bは、一次スリット2
の深さD1を0. 19mm 、二次スリット3の最深部の
深さD2を0. 11mmとし、各部における深さは均一
としたものであるが、一次スリット2の分割の際に二次
スリット3まで分割されるバー折れ不良が多発した。従
来品Cは、一次スリット2の深さD1を0. 23mm、
二次スリット3の最深部の深さD2を0. 11mmとし
各部における深さは均一としたものであるが、セラミッ
ク基板1の製造工程において一次スリット2のクラック
や割れが多発した。尚、一次スリット2並びに二次スリ
ット3の分割不良は発生しなかった。
Conventional ceramic substrate 1 as a comparative example
Is a primary slit 2 and a secondary slit 3 which are usually set.
Each of them was manufactured and evaluated within the range of the depth. In the conventional product A, the depth D1 of the primary slit 2 is set to 0.
19 mm, the depth D2 of the deepest part of the secondary slit 3 is set to 0.0.
7 mm, the depth of each part was uniform, and no cracks or cracks occurred in the manufacturing process of the ceramic substrate 1 and no division failure of the primary slit 2 occurred. Burrs were found on the edges. The conventional product B has a primary slit 2
The depth D1 is 0.19 mm, the depth D2 of the deepest part of the secondary slit 3 is 0.11 mm, and the depth in each part is uniform. There were many broken bars broken down to three. Conventional product C has a depth D1 of primary slit 2 of 0.23 mm,
Although the depth D2 at the deepest portion of the secondary slit 3 was 0.11 mm and the depth at each portion was uniform, cracks and cracks in the primary slit 2 occurred frequently in the manufacturing process of the ceramic substrate 1. In addition, the division failure of the primary slit 2 and the secondary slit 3 did not occur.

【0013】本発明実施例は、二次スリット3の形状が
図2(a)に示す逆放物線状と、図2(b)に示す矩形
状と、図2(c)に示すC面形状の3形状で、一次スリ
ット2の深さD1を、0.09、0.10、0.19、
0.22、0.23mmの5段階とし、二次スリット3
の最深部の深さD2をそれぞれ一次スリット2の深さD
1の順に対応し、0.05、0.06、0.11、0.
18、0.19mmの5段階とし、二次スリット3の最
浅部の深さD3も同様に一次スリット2の深さD1の順
に対応し、0.030、0.032、0.07、0.1
0、0.11mmの5投階とし、各浅いものAから深い
ものE迄の5段階を、二次スリット3の形状が逆放物線
状と矩形状とC面形状の3形状について各各作製した。
尚、二次スリット3の形状が矩形状とC面形状の2種の
二次スリット3の最浅部の長さL1並びに二次スリット
3の最浅部からのC面の長さL2は、一次スリット2の
深さD1の順に対応し、0.41、0.40、0.2
5、0.20、0.19mmの5段階とした。
In the embodiment of the present invention, the secondary slit 3 has a reverse parabolic shape as shown in FIG. 2A, a rectangular shape as shown in FIG. 2B, and a C-plane shape as shown in FIG. In three shapes, the depth D1 of the primary slit 2 is set to 0.09, 0.10, 0.19,
0.22, 0.23mm in 5 steps, secondary slit 3
Is the depth D2 of the primary slit 2
1, 0.05, 0.06, 0.11, 0.
18 and 0.19 mm, and the depth D3 of the shallowest part of the secondary slit 3 also corresponds to the depth D1 of the primary slit 2 in the same manner, and 0.030, 0.032, 0.07, 0 .1
Five steps of 0 and 0.11 mm were made, and five steps from each shallow one A to deep one E were made for each of the three shapes of the secondary slit 3 having a reverse parabolic shape, a rectangular shape, and a C-plane shape. .
In addition, the length L1 of the shallowest part of the two types of secondary slits 3 in which the shape of the secondary slit 3 is rectangular and the C-plane shape and the length L2 of the C-plane from the shallowest part of the secondary slit 3 are as follows: Corresponding to the order of the depth D1 of the primary slit 2, 0.41, 0.40, 0.2
5, 0.20, and 0.19 mm.

【0014】本発明実施例の結果は、二次スリット3の
形状が逆放物線状、矩形状、C面形状とも、本発明実施
例Aつまり、一次スリット2の深さD1が0.09m
m、二次スリット3の最深部の深さD2が0.05m
m、二次スリット3の最浅部の深さD3が0.030m
m、矩形状の二次スリット3の最浅部の長さL1並びに
C面形状の二次スリット3の最浅部からのC面の長さL
2が0.41mmのものは、セラミック基板1の製造工
程中でのクラックや割れ不良はなかったものの、一次ス
リット2および二次スリット3の分割の際に端部にバリ
発生のあるものがあり、 従来品比較例に対し、一次スリ
ット2並びに二次スリット3の分割不良率を半減以下に
することは出来なかった。
The results of the embodiment of the present invention show that the secondary slit 3 has a reverse parabolic shape, a rectangular shape, and a C-plane shape, and the depth D1 of the primary slit 2 is 0.09 m.
m, the depth D2 of the deepest part of the secondary slit 3 is 0.05 m
m, the depth D3 of the shallowest part of the secondary slit 3 is 0.030 m
m, the length L1 of the shallowest portion of the rectangular secondary slit 3 and the length L of the C-plane from the shallowest portion of the C-shaped secondary slit 3
In the case of 2 having a diameter of 0.41 mm, there were no cracks and cracks during the manufacturing process of the ceramic substrate 1, but there was a case in which burrs were generated at the ends when the primary slit 2 and the secondary slit 3 were divided. As compared with the comparative example of the conventional product, the division failure rate of the primary slit 2 and the secondary slit 3 could not be reduced to less than half.

【0015】本発明実施例Eつまり、一次スリット2の
深さD1が0.23mm、二次スリット3の最深部の深
さD2が0.19mm、二次スリット3の最浅部の深さ
D3が0.11mm、矩形状の二次スリット3の最浅部
の長さL1並びにC面形状の二次スリット3の最浅部か
らのC面の長さL2が0.19mmのものは、セラミッ
ク基板1の製造工程中で一次スリット2のクラックや割
れ不良が発生し、従来品比較例に対しクラック、割れの
不良率を半減以下にすることは出来なかった。また一次
スリット2の分割の際に二次スリット3まで分割される
バー折れ不良も一部発生し、従来品比較例に対し一次ス
リット2の分割不良率も半減以下にすることは出来なか
った。しかし、正常に分割されたものには端部へのバリ
の発生はなかった。
Embodiment E of the present invention, that is, the depth D1 of the primary slit 2 is 0.23 mm, the depth D2 of the deepest part of the secondary slit 3 is 0.19 mm, and the depth D3 of the secondary slit 3 is the deepest part. Is 0.11 mm, the length L1 of the shallowest portion of the rectangular secondary slit 3 and the length L2 of the C-plane from the shallowest portion of the C-shaped secondary slit 3 are 0.19 mm. Cracks and cracking of the primary slit 2 occurred during the manufacturing process of the substrate 1, and the crack and cracking failure rate could not be reduced to half or less of the conventional product comparative example. In addition, when the primary slit 2 was divided, some of the bar breakage failures, which were divided up to the secondary slits 3, also occurred, and the failure rate of the primary slits 2 could not be reduced to less than half that of the comparative example. However, there was no burr at the end of the normally divided one.

【0016】本発明実施例B、C、Dつまり、二次スリ
ット3の形状が逆放物線状、矩形状、C面形状とも、一
次スリット2の深さD1が0.10、0.19、0.2
2mm、二次スリット3の最深部の深さD2が0.0
6、0.11、0.18mm、二次スリット3の最浅部
の深さD3が0.032、0.07、0.10mm、矩
形状の二次スリット3の最浅部の長さL1並びにC面形
状の二次スリット3の最浅部からのC面の長さL2が
0.40、0.25、0.20mmのものは、セラミッ
ク基板1の製造工程中で一次スリット2のクラックや割
れの不良率は従来品比較例に対し半減以下となり、また
一次スリット2の分割の際に二次スリット3まで分割さ
れるバー折れ不良並びに一次スリット2並びに二次スリ
ット3の分割の際の端部へのバリ発生のいずれの不良率
も従来品比較例に対し半減以下となった。また、これら
のことより電子部品の分割前までの工程における割れ等
の発生も著しく低減出来るといえる。
Embodiments B, C and D of the present invention, that is, the secondary slit 3 has a reverse parabolic shape, a rectangular shape and a C-plane shape, and the depth D1 of the primary slit 2 is 0.10, 0.19, 0 .2
2 mm, the depth D2 of the deepest part of the secondary slit 3 is 0.0
6, 0.11, 0.18 mm, the depth D3 of the shallowest part of the secondary slit 3 is 0.032, 0.07, 0.10 mm, and the length L1 of the shallowest part of the rectangular secondary slit 3 In the case where the length L2 of the C-plane from the shallowest part of the secondary slit 3 having the C-plane shape is 0.40, 0.25, and 0.20 mm, cracks in the primary slit 2 during the manufacturing process of the ceramic substrate 1 The defect rate of cracks and cracks is less than half that of the comparative example of the conventional product. Also, when the primary slit 2 is divided, the broken bar divided up to the secondary slit 3 and when the primary slit 2 and the secondary slit 3 are divided. Any defective rate of generation of burrs on the edge was less than half that of the conventional product. From these facts, it can be said that the occurrence of cracks and the like in the steps before the division of the electronic component can be significantly reduced.

【0017】[0017]

【発明の効果】本発明によれば、チップ状電子部品の絶
縁基板を多数個取りするセラミック基板において、先に
分割するための一次スリットと、後で分割すめための二
次スリットを有し、該二次スリットにおける一次スリッ
トと交わる部位の深さを他の部分よりも相対的に浅く形
成することにより、セラミック基板の製造工程並びにそ
の後の電子部品の分割前までの工程において、クラック
や割れの発生を防止でき、 また電子部品の製造工程にお
ける一次スリットの分割不良や二次スリットの分割不良
の発生も防止でき、分割後のバリの発生も防止できるな
ど歩留まりの向上並びに生産性の向上が図れる。
According to the present invention, a ceramic substrate for taking a large number of insulating substrates for chip-shaped electronic components has a primary slit for dividing first and a secondary slit for dividing later. By forming the depth of the portion of the secondary slit that intersects with the primary slit relatively shallower than other portions, cracks and cracks are caused in the process of manufacturing the ceramic substrate and the subsequent process before dividing the electronic component. In addition, it is possible to prevent the occurrence of defective primary slits and secondary slits in the electronic component manufacturing process, and to prevent the occurrence of burrs after division, thereby improving yield and improving productivity. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電子部品用セラミック基板の分割溝の
断面図である。
FIG. 1 is a sectional view of a dividing groove of a ceramic substrate for electronic components of the present invention.

【図2】(a)(b)(c)は本発明の電子部品用セラ
ミック基板の分割溝の断面図である。
FIGS. 2A, 2B, and 2C are cross-sectional views of a dividing groove of a ceramic substrate for an electronic component of the present invention.

【図3】(a)は分割溝が形成された電子部品用セラミ
ック基板の斜視図で、(b)は従来の分割溝の断面図で
ある。
FIG. 3A is a perspective view of a ceramic substrate for an electronic component in which a dividing groove is formed, and FIG. 3B is a cross-sectional view of a conventional dividing groove.

【図4】棒状に分割されたセラミック基板の斜視図であ
る。
FIG. 4 is a perspective view of a ceramic substrate divided into rod shapes.

【図5】単体に分割されたセラミック基板の斜視図であ
る。
FIG. 5 is a perspective view of a ceramic substrate divided into single pieces.

【符号の説明】[Explanation of symbols]

. 1、セラミック基板 2、一次スリット 3、二次スリット T、セラミック基板の厚み D1、一次スリットの深さ D2、二次スリットの最深部の深さ D3、二次スリットの最浅部の深さ L、一次スリット間のピッチ L1、二次スリットの最浅部の長さ L2、二次スリットの最浅部からのC面の長さ 1, ceramic substrate 2, primary slit 3, secondary slit T, thickness of ceramic substrate D1, depth of primary slit D2, depth of secondary slit deepest D3, depth of secondary slit shallowest L, pitch between primary slits L1, length of shallowest part of secondary slit L2, length of C plane from shallowest part of secondary slit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】チップ状電子部品の絶縁基板を多数個取り
するセラミック基板において、先に分割するための一次
スリットと後で分割するための二次スリットを有し、該
二次スリットに於ける一次スリットと交わる部位の深さ
が他の部分よりも相対的に浅く形成されていることを特
徴とする電子部品用セラミック基板。
1. A ceramic substrate for taking a large number of insulating substrates of a chip-shaped electronic component, comprising a primary slit for dividing first and a secondary slit for dividing later. A ceramic substrate for an electronic component, wherein a depth of a portion intersecting with a primary slit is formed relatively shallower than other portions.
JP09075699A 1999-03-31 1999-03-31 Ceramic substrate for electronic parts Expired - Fee Related JP3838810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09075699A JP3838810B2 (en) 1999-03-31 1999-03-31 Ceramic substrate for electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09075699A JP3838810B2 (en) 1999-03-31 1999-03-31 Ceramic substrate for electronic parts

Publications (2)

Publication Number Publication Date
JP2000286511A true JP2000286511A (en) 2000-10-13
JP3838810B2 JP3838810B2 (en) 2006-10-25

Family

ID=14007462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09075699A Expired - Fee Related JP3838810B2 (en) 1999-03-31 1999-03-31 Ceramic substrate for electronic parts

Country Status (1)

Country Link
JP (1) JP3838810B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353573A (en) * 2001-05-28 2002-12-06 Kyocera Corp Ceramic wiring board of multiple allocation
WO2009154295A1 (en) * 2008-06-20 2009-12-23 日立金属株式会社 Collective ceramic substrate, manufacturing method for the substrate, ceramic substrate, and ceramic circuit substrate
WO2014173391A1 (en) * 2013-04-22 2014-10-30 Rogers Germany Gmbh Base substrate, metal-ceramic substrate produced from a base substrate and process for producing a base substrate
WO2021095845A1 (en) * 2019-11-15 2021-05-20 デンカ株式会社 Ceramic substrate, composite substrate, circuit board, ceramic substrate production method, composite substrate production method, circuit board production method, and method for producing multiple circuit boards

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353573A (en) * 2001-05-28 2002-12-06 Kyocera Corp Ceramic wiring board of multiple allocation
WO2009154295A1 (en) * 2008-06-20 2009-12-23 日立金属株式会社 Collective ceramic substrate, manufacturing method for the substrate, ceramic substrate, and ceramic circuit substrate
WO2014173391A1 (en) * 2013-04-22 2014-10-30 Rogers Germany Gmbh Base substrate, metal-ceramic substrate produced from a base substrate and process for producing a base substrate
WO2021095845A1 (en) * 2019-11-15 2021-05-20 デンカ株式会社 Ceramic substrate, composite substrate, circuit board, ceramic substrate production method, composite substrate production method, circuit board production method, and method for producing multiple circuit boards

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