JP3813292B2 - Differential amplifier circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential amplifier circuit. More specifically, the present invention compares the magnitude of an input signal applied to one input terminal with a reference voltage applied to the other input terminal, and has a logic corresponding to the comparison result. The present invention relates to a differential amplifier circuit that outputs a pair of complementary signals.
Such a differential amplifier circuit is used for an input buffer of a semiconductor integrated circuit, for example, because of its feature of being capable of high-speed operation and being resistant to fluctuations in the level of the input signal. In order to achieve higher-speed operation, a pair of complementary signals is used. It is necessary to accurately match the frequency characteristics of the.
[0002]
[Prior art]
(1) First Conventional Example FIG. 20 is a basic configuration diagram of the differential amplifier circuit, and an input signal Di equivalently shown by a signal source 1 and a bias source 2 constitutes a differential transistor section 3. A pair of complementary signals Q and XQ having a logic (H level or L level) applied to one gate of a pair of FETs 4 and 5 and having a magnitude comparison result with a reference voltage Vref applied to the other gate. Are output from the sources of the pair of FETs 7 and 8 constituting the source follower 6. 9 and 10 are load resistors, 11 to 13 are constant current sources, and VDD is a power source.
(2) Second Conventional Example In addition to the configuration of FIG. 20, the present applicant has proposed a differential amplifier circuit in which a capacitor 14 is inserted between the drain of the FET 4 and Vref as shown in FIG. (See JP-A-2-39709).
[0003]
[Problems to be solved by the invention]
The disadvantage of the first conventional example is that, as described in Japanese Patent Laid-Open No. 2-39709, the FET 4 on the Di input side is equivalent among the pair of FETs 4 and 5 constituting the differential transistor section 3. Since the FET 5 on the Vref side operates equivalently with a grounded gate circuit (with a constant gate potential), while operating with a common source circuit (with a constant source potential), the frequency characteristics of the pair of complementary signals Q and XQ This means that there is a difference in amplitude. That is, if the frequency band of the source grounded circuit (XQ side) is represented by Δf_XQ and the frequency band of the gate grounded circuit (Q side) is represented by Δf_Q, then Δf_XQ> Δf_Q. As a result, as shown in FIG. There is a drawback in that they do not match and a difference occurs between the Q and XQ amplitudes as shown in FIG.
[0004]
On the other hand, the second conventional example pays attention to the disadvantages of the first conventional example and is advantageous in that the frequency band Δf_Q of the gate grounding circuit (Q side) can be expanded, but the frequency band of the source grounding circuit (XQ side). There is a drawback that Δf_XQ becomes narrow. That is, as shown in FIG. 24, in the second conventional example, the frequency characteristic of Q can be shifted to the high frequency side (see arrow A) by the capacitor 14 placed between the drain of the FET 4 and Vref. There is a drawback that the characteristic shifts to the low frequency side (see arrow B). This is because the substantial load of the FET 4 is given by the impedance Z (Z = R / {1 + jωCR}) in parallel between the resistor 9 (R) and the capacitor 14 (C). Where ω is the required bandwidth of the differential transistor section.
[0005]
Therefore, an object of the present invention is to accurately match the frequency characteristics of a pair of complementary signals.
[0006]
[Means for Solving the Problems]
According to the first aspect of the present invention, a pair of logic having a logic corresponding to a comparison result of a differential transistor unit that compares the magnitude of an input signal applied to one input terminal and a reference voltage applied to the other input terminal. in differential amplifier circuit you output complementary signals, put the first inductor to the load side of the transistor where the input signal is applied, a value smaller than the first inductor to the load side of the transistor where the reference voltage is applied And a capacitor is inserted between the load side terminal of the transistor to which the input signal is applied and the input terminal of the transistor to which the reference voltage is applied, and the first and second inductors are connected. The frequency characteristics of the pair of complementary signals are matched by the value and the value of the capacitor .
The invention according to claim 2 is characterized in that, in the invention according to claim 1, the second inductor has a value of 0 henry or a minute value close thereto.
According to a third aspect of the present invention, in the first or second aspect of the present invention, a source follower unit that outputs a pair of complementary signals having a logic corresponding to a comparison result of the differential transistor unit is provided.
According to a fourth aspect of the present invention, in the third aspect of the invention, a third transistor is connected to a load side of a transistor having the same logic as that of the transistor to which the input signal is applied, of the pair of transistors constituting the source follower unit. An inductor is inserted, a fourth inductor having a value smaller than that of the third inductor is inserted on the load side of the transistor having the same logic as that of the transistor to which the reference voltage is applied, the values of the first and second inductors, The frequency characteristics of a pair of complementary signals output from the source follower unit are matched with each other by a value of the third and fourth inductors and a value of the capacitor.
According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the fourth inductor has 0 henry or a minute value close thereto.
According to the sixth aspect of the present invention, there is provided a differential transistor unit for comparing the magnitude of an input signal applied to one input terminal and a reference voltage applied to the other input terminal, and a comparison result of the differential transistor unit. In a differential amplifier circuit having a source follower unit that outputs a pair of complementary signals having a corresponding logic, the transistor has the same logic as that of the transistor to which the input signal is applied, out of a pair of transistors constituting the source follower unit. A first inductor is placed on the load side of the transistor, a second inductor having a smaller value than the first inductor is placed on the load side of the transistor having the same logic as the transistor to which the reference voltage is applied, and the input signal is Put a capacitor between the load side terminal of the transistor to be applied and the input terminal of the transistor to which the reference voltage is applied, The first and second inductor value and the capacitor value, characterized in that to match the frequency characteristics of the pair of complementary signals.
A seventh aspect of the invention is characterized in that, in the sixth aspect of the invention, the second inductor has a value of 0 henry or a value close thereto.
The invention according to claim 8 is the invention according to any one of claims 1 to 7, wherein the transistor is an FET, the load side terminal is a drain, and the input terminal is a gate. To do.
[0007]
In the present invention, the frequency characteristics of the pair of complementary signals output from the source follower unit are accurately matched by adjusting the value of the inductor inserted in the differential transistor unit or the source follower unit.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(1) Figures 1-10 are views showing a first embodiment of a differential amplifier circuit according to the present invention.
In FIG. 1, 3a is a differential transistor part that is partially different from the conventional example (FIG. 20 or FIG. 21), and 6 is a source follower part similar to the conventional example. If the same reference numerals are given to the elements common to the conventional example and the description thereof is omitted, the characteristic matter of this embodiment is that the inductor 15, the drain load of the pair of FETs 4 and 5 constituting the differential transistor section, 16 and the frequency characteristics of the pair of complementary signals Q and XQ output from the source follower unit 6 are matched by adjusting the values of the inductors 15 and 16. .
[0009]
If the inductors 15 and 16 are removed from the configuration of FIG. 1, the configuration of the first conventional example is obtained. However, this first conventional example has a drawback that Δf_XQ> Δf_Q. The values (inductances) of the inductors 15 and 16 should be adjusted so that Δf_XQ = Δf_Q as desired. In the first conventional example, “XQ amplitude”> “Q amplitude” (see FIG. 23). Therefore, in short, it is sufficient that the “Q amplitude” is increased, and for this purpose, the value of the Q-side inductor 16 is made larger than the value of the XQ-side inductor 15.
[0010]
According to this, by making the value of the inductor 16 on the Q side larger than the value of the inductor 15 on the XQ side, preferable characteristics as shown in FIGS. 2 and 3 can be obtained. That is, the Q characteristics can be shifted to the high frequency side without shifting the XQ characteristics to the low frequency side as shown in FIG. 2, and the two characteristics can be matched, as shown in FIG. Can be combined.
[0011]
As shown in FIG. 4, the inductor 15 on the XQ side may not be substantial (more precisely, it may be an inductor of 0 henry or a minute value close thereto). This is because the value of the inductor 16 on the Q side is larger than the value of the inductor 15 on the XQ side when viewed equivalently. Alternatively, as shown in FIG. 5, the above-described inductor value relationship may be applied to the source follower unit 6a, and specifically, between the drains of the pair of FETs 7 and 8 of the source follower unit 6a and VDD. The inductors 17 and 18 may be inserted, respectively, and the value of the Q-side inductor 17 may be larger than the value of the XQ-side inductor 18. In this case, as shown in FIG. 6, the inductor 18 on the XQ side may not be substantial (more precisely, it may be an inductor of 0 henry or a minute value close thereto).
[0012]
Alternatively, as shown in FIG. 7, inductors 15, 16, 17, and 18 may be inserted in both the differential transistor unit 3 a and the source follower unit 6 a, and the respective values may be set as described above, or As shown in FIG. 10, the value of one of the inductors may be zero (exactly 0 henry or a minute value close thereto).
(2) 11 to 19 are views showing a second embodiment of a differential amplifier circuit according to the present invention. The difference from the first embodiment (FIGS. 1 to 10) is that a capacitor 14 is inserted between the drain of one FET 4 of the differential transistor section and Vref. This solves the defect of the example (shift of the XQ characteristic toward the low frequency side). That is, also in this embodiment, as shown in FIG. 11, the inductors 15 and 16 are inserted into the load of the pair of FETs 4 and 5 of the differential transistor section 3a ′, but at the same time the drain of one FET 4 of the differential transistor section 3a ′. 14 and Vref, and by appropriately adjusting the values of the inductors 15 and 16 and the value of the capacitor 14, the QQ and XQ are not shifted to the low frequency side without incurring a shift to the low frequency side. These frequency characteristics are matched with each other (see the characteristic diagram of FIG. 12).
[0013]
In this embodiment, there are various variations as in the first embodiment. For example, as shown in FIG. 13, the value of the inductor 16 on the Q side is set to zero (exactly 0 henry or a minute value close thereto), or as shown in FIG. 14, the inductors 17 and 18 are provided in the source follower section 6a. As shown in FIG. 15, the value of the inductor 17 on the Q side is set to zero (exactly 0 henry or a minute value close thereto), or as shown in FIG. 16, the differential transistor section 3a ′ and the source follower section Inductors 15 to 18 are provided on both sides of 6a, or as shown in FIG. 17, the value of inductor 16 on the Q side of differential transistor section 3a ′ is set to zero (exactly 0 henry or a small value close thereto) As shown in FIG. 18, the value of the inductor 17 on the Q side of the source follower section 6a is set to zero (exactly 0 henry or a small value close thereto), or As shown, it may be or the value of the differential transistor portion 3a 'and the source follower unit 6a together Q side inductor 16 and 17 to zero (0 Henry or small value close to it exactly).
[0014]
In this embodiment, the relationship between the values of the inductors 15 and 16 (or 17, 18) is reversed from that of the first embodiment by inserting the capacitor 14. That is, the value of the XQ-side inductor 15 (or 18) is larger than the value of the Q-side inductor 16 (or 17).
In the configuration of FIG. 11, the value of the inductor 15 is L15, the value of the inductor 16 is L16, the value of the resistor 9 is R9, the value of the resistor 10 is R10, the value of the capacitor 14 is C14, and ω is a required value of the differential transistor section. In the case of the band, the substantial load of the left FET 4 of the differential transistor section 3a ′ is {(R9 + jωL15) / 1/1 / jωC14)}, and the substantial load of the right FET 5 of the differential transistor section 3a ′ is { (R10 + jωL16)}, the values of the inductors 15 and 16 may be adjusted so that the two expressions are equal.
[0015]
Alternatively, in the configuration of FIG. 14, the gate-drain capacitance of the FET 7 is Cgd7, the gate-drain capacitance of the FET 8 is Cgd8, the value of the inductor 17 is L17, the value of the inductor 18 is L18, and the value of the capacitor 14 is C14. If the gate resistance and drain resistance are ignored, the input impedance of the source follower unit 6a viewed from the left FET 4 of the differential transistor unit 3 ′ is {(1 / jωCgd8 + jωL18) // jωC14)}, and the differential transistor unit 3 Since the input impedance of the source follower section 6a viewed from the right-side FET 5 is {(1 / jωCgd7 + jωL17)}, the values of the inductors 17 and 18 may be adjusted so that the two equations are equal.
[0016]
【The invention's effect】
According to the present invention, it is possible to accurately match the frequency characteristics of a pair of complementary signals output from the source follower unit by adjusting the value of the inductor placed in the differential transistor unit or the source follower unit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a first embodiment.
FIG. 2 is a frequency characteristic diagram of the first embodiment.
FIG. 3 is an amplitude characteristic diagram of the first embodiment.
FIG. 4 is a modified configuration diagram (part 1) of the first embodiment;
FIG. 5 is a modified configuration diagram (No. 2) of the first embodiment;
FIG. 6 is a modified configuration diagram (No. 3) of the first embodiment;
FIG. 7 is a modified configuration diagram (No. 4) of the first embodiment;
FIG. 8 is a modified configuration diagram (No. 5) of the first embodiment;
FIG. 9 is a modified configuration diagram (No. 6) of the first embodiment;
FIG. 10 is a modified configuration diagram (No. 7) of the first embodiment;
FIG. 11 is a configuration diagram of a second embodiment.
FIG. 12 is a frequency characteristic diagram of the second embodiment.
FIG. 13 is a modified configuration diagram (No. 1) of the second embodiment;
FIG. 14 is a modified configuration diagram (No. 2) of the second embodiment;
FIG. 15 is a modified configuration diagram (No. 3) of the second embodiment;
FIG. 16 is a modified configuration diagram (part 4) of the second embodiment;
FIG. 17 is a modified configuration diagram (No. 5) of the second embodiment;
FIG. 18 is a modified configuration diagram (No. 6) of the second embodiment;
FIG. 19 is a modified configuration diagram (No. 7) of the second embodiment;
FIG. 20 is a configuration diagram of a first conventional example.
FIG. 21 is a configuration diagram of a second conventional example.
FIG. 22 is a frequency characteristic diagram of the first conventional example.
FIG. 23 is an amplitude characteristic diagram of the first conventional example.
FIG. 24 is a frequency characteristic diagram of a second conventional example.
[Explanation of symbols]
Di: Input signal FET
Q, XQ: complementary signal Vref: reference voltage 3a, 3a ′: differential transistor section 6a: source follower sections 15-18: inductor 14: capacitor

Claims (8)

Differential you outputs a pair of complementary signals with a logic in accordance with the comparison result of the differential transistor unit that compares the magnitude of the reference voltage applied to the input signal applied to one input terminal and the other input terminal In the amplifier circuit,
A first inductor is placed on the load side of the transistor to which the input signal is applied, a second inductor having a smaller value than the first inductor is placed on the load side of the transistor to which the reference voltage is applied, and the input signal A capacitor is inserted between the load side terminal of the transistor to which the reference voltage is applied and the input terminal of the transistor to which the reference voltage is applied, and the pair of complementary signals is determined by the values of the first and second inductors and the value of the capacitor. A differential amplifier circuit characterized by matching the frequency characteristics of. 2. The differential amplifier circuit according to claim 1, wherein the second inductor has a very small value of 0 henry or a value close thereto. 3. The differential amplifier circuit according to claim 1, further comprising a source follower unit that outputs a pair of complementary signals having logic according to a comparison result of the differential transistor unit. A third inductor is inserted on the load side of a transistor having the same logic as that of the transistor to which the input signal is applied, out of a pair of transistors constituting the source follower unit, and the same logic as that of the transistor to which the reference voltage is applied. A fourth inductor having a value smaller than that of the third inductor is placed on the load side of the transistor having the first and second inductors, the third and fourth inductor values, and the capacitor value. 4. The differential amplifier circuit according to claim 3, wherein frequency characteristics of a pair of complementary signals output from the source follower unit are matched. 5. The differential amplifier circuit according to claim 4, wherein the fourth inductor has a small value of 0 henry or a value close thereto. A differential transistor section that compares the magnitude of an input signal applied to one input terminal and a reference voltage applied to the other input terminal, and a pair of complementary circuits having logic according to the comparison result of the differential transistor section In a differential amplifier circuit having a source follower section for outputting a signal,
A first inductor is inserted on the load side of a transistor having the same logic as that of the transistor to which the input signal is applied, and the same logic as that of the transistor to which the reference voltage is applied. A second inductor having a value smaller than that of the first inductor is placed on the load side of the transistor, and further between the load side terminal of the transistor to which the input signal is applied and the input terminal of the transistor to which the reference voltage is applied A differential amplifier circuit, wherein a capacitor is inserted to match the frequency characteristics of the pair of complementary signals according to the values of the first and second inductors and the value of the capacitor. The differential amplifier circuit according to claim 6, wherein the second inductor has a very small value of 0 henry or a value close thereto. 8. The differential amplifier circuit according to claim 1, wherein the transistor is an FET, the load side terminal is a drain, and the input terminal is a gate.

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