JP3224340B2 - Source follower circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a source follower circuit, and more particularly, to a source follower circuit that operates on a differential signal.

[0002]

2. Description of the Related Art In recent years, various digital circuits used for high-speed optical communication have been developed. However, when a small signal output is amplified and given to a next-stage logic circuit, a source follower circuit is widely used. You. An example of this type of source follower circuit is disclosed in the following document.

[0003] Matsuo, Seshita, Wakimoto, Kitaura, Terada, "SCF
Study of High-speed T-FF by L Circuit "(1993 IEICE Spring Conference, 1993, pp. 5-167) FIG. 2 shows an example of such a conventional differentially operated source follower circuit. FIG. This source follower circuit has four n-type depletion type field effect transistors FET1, FET2, FET3 and FET4, and two resistors 5 and 6. Where IN is FE
A positive-phase signal supplied to the input terminal 11 connected to the gate of T1, INB is a negative-phase signal supplied to the input terminal 12 connected to the gate of FET2, and OUT is connected to the source of FET1 and the drain of FET3. OUTB, which is output from the output terminal 13, is connected between the source of the FET 2 and F
This is a reverse-phase signal output from the output terminal 14 connected to the drain of ET4. The drain of FET1 and the drain of FET2 are connected to a power supply terminal 15, the gate of FET3 and the gate of FET4 are connected to a bias terminal 16,
The source of ET3 is connected to one terminal of resistor 5, the other terminal of resistor 5 is grounded, and the source of FET 4 is
, And the other terminal of the resistor 6 is grounded.

In this source follower circuit, FET1 and FET2 have the same characteristics, while FET3 and FET3
4 have the same characteristics, and the resistors 5 and 6 have the same resistance value. The bias terminal 16 is assumed a constant voltage V _G is applied.

The FET 1 and the FET 2 operate as a common drain circuit, and the FET 3 and the resistor 5 and the FET 4 and the resistor 6
Operates as a current source. The positive-phase signal IN is applied to the input terminal 11.
Is input to the input terminal 12 and the negative-phase signal INB is input to the input terminal 12, the positive-phase signal OUT,
An out-of-phase signal OUTB is output. Therefore, the circuit of FIG. 2 is used as a source follower circuit that operates with a differential signal.

[0006]

However, when the source follower circuit having the above configuration operates with a differential signal, the drain voltages of the FETs 3 and 4 operating as current sources change the output terminals 13 and 14. here,
For example, the drain conductance g of FET3 or FET4
If d is 0, the gain of the source follower circuit becomes 1, and the amplitude change of the input terminals 11 and 12 is transmitted to the output terminals 13 and 14 as it is. However, in practice, since the drain conductance gd cannot be 0, the output signal amplitude decreases with respect to the input signal amplitude. That is, a change in the drain currents I ₁ and I ₂ with respect to a change in the drain voltage results in a loss of the source follower circuit, and there is a problem that the gain of the source follower circuit decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a source follower circuit having a small gain reduction rate.

[0008]

In the source follower circuit according to the present invention, a first field effect transistor (hereinafter, referred to as FET) to which a positive-phase signal is supplied to a gate and a negative-phase signal to be supplied to a gate. A second FET, and the first F
A third FET having a drain connected to the source of ET;
A fourth FET having a drain connected to a source of the second FET;
And a power supply connected to the drain of the first FET and the drain of the second FET;
And a second output terminal for outputting a negative-phase signal from the connection point between the second and fourth FETs. In the source follower circuit, the source of the third FET is connected to one terminal of a first resistor and the gate of the fourth FET, and the source of the fourth FET is connected to one terminal of a second resistor. Connected to the gate of the third FET;
The other terminal of the second resistor is grounded.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described.

FIG. 1 is a diagram showing a source follower circuit according to the present invention. This source follower circuit has four n-type depletion type field effect transistors FET1, FET2, FET3, and FET4, and two resistors 5 and 6 like the conventional source follower circuit.
Here, the in-phase signal I at the terminals 11 to 14, respectively.
N, negative-phase signal INB, positive-phase signal 0UT, and negative-phase signal 0
UTB is similar to the conventional one. 2 in that the source of FET3 is connected not only to one terminal of resistor 5 but also to the gate of FET4, and the source of FET4 is connected not only to one terminal of resistor 6 but also to the gate of FET3. Is also connected.

In this source follower circuit, FET1 and FΕT2 have the same characteristics, and FET3 and FET
4 have the same characteristics, and the resistors 5 and 6 have the same resistance value.

[0012] Now, the transconductance of FET3 and FET4 and g _m, the drain conductance of FET3 and FET4 and g _d, if the threshold voltage of FET3 and FET4 and V _TH, the current flowing between the drain and the source of the FET Ids can be expressed as _{Ids = g m (Vg -Vs -V} TH) + g d (Vd -Vs). Here, Vd, Vg, and Vs are drain, gate, and source voltages, respectively. Therefore, the resistance values of the resistors 5 and 6 are represented by r, the drain voltage of the FET ₃ is represented by Vd1, and the drain voltage of the FET4 is represented by Vd.
₂ , the drain current I ₁ of FET ₃ and FE
Drain current I ₂ of T4 _{is, I 1 = g m (r} · I 2 -r · I 1 -V TH) + g d (Vd 1
−r · I ₁ ) I ₂ = g _m (r · I ₁ −r · I ₂ −V _TH ) + g _d (Vd ₂
−r · I ₂ ). When these expressions are arranged for drain currents I ₁ and I ₂ , I ₁ = ｛g _m · g _d · r · V ₂ + (g _d + g _m · g _d ·
^{_{r + g d 2 · r)}} · V 1 - (g m + 2g m 2 · r + g m · g d
・ R) ・ V _TH ｝ / (1 + 2g _m・ r + 2g _d・ r + 2
g _m · g _d · r ² + g _d ² · r ² )｝ Similarly, the drain current I _{2 of the} FET 4 is described as follows.

I ₂ = ｛g _m · g _d · r · V ₁ + (g _d +
g _m · g _d · r + g _d ² · r) · V _2- (g _m + 2 g _m ² ·
r + g _m · g _d · r) · V _TH ｝ / (1 + 2 g _m · r + 2
g _d · r + 2 g _m · g _d · r ² + g _d ² · r ² )｝ Here, the drain voltages V ₁ and V ₂ defined by the on / off of the FET 1 and the FET ₂ are different from each other. Therefore, dV ₁ / dV ₂ = d
V ₂ / dV ₁ = −1, the change in the drain current I ₁ with respect to the change in the drain voltage V ₁ , and the change in the drain voltage V ₂
Change in the drain current I ₂ for the change can be described as follows.

DI ₁ / dV ₁ = g _d / {1 + r · (2 g _m + g _d )} (1) dI ₂ / dV ₂ = g _d / {1 + r · (2 g _m + g _d )} (2) In the conventional source follower circuit shown in FIG.
The transconductance of FET3 and FET4 and g _m, the drain conductance of FET3 and FET4 and g _d, the threshold voltage of FET3 and FET4 V _TH
And, the resistance of the resistor 5 and the resistor 6 and r, the constant voltage applied to the bias terminal 16 and V _G, the drain voltage of FET3 and V _1, the drain voltage of the FET 4 V ₂
Assuming that the drain current of the FET 3 is I ₁ and the drain current of the FET 4 is I ₂ , I ₁ is described as follows.

I ₁ = ｛g _d · V ₁ / (1 + g _m · r + g
_d · r)｝ + ｛g _m · V _G / (1 + g _m · r + g _d ·
r) {− {g _m · V _TH / (1 + g _m · r + g _d · r)} From this, the change of I ₁ with respect to the change of V ₁ is described as the following equation.

DI ₁ / dV ₁ = g _d / {1 + r · (g _m + g _d )} (3) Similarly, the drain current I _{2 of the} FET 4 is described by the following equation.

I ₂ = ｛g _d · V ₂ / (1 + g _m · r + g
_d · r)｝ + ｛g _m · V _G / (1 + g _m · r + g _d ·
r) {− {g _m · V _TH / (1 + g _m · r + g _d · r)} From this, the change of I ₂ with respect to the change of V ₂ is described as the following equation.

DI ₂ / dV ₂ = g _d / {1 + r · (g _m + g _d )} (4) Therefore, the above equations (1) and (2) and the equations (3) and (4)
When comparing with, the former value is clearly smaller. That is, according to the present invention, the change in the drain current with respect to the change in the drain voltage of the current source can be suppressed as compared with the related art, so that the loss of the source follower circuit can be reduced and the decrease in the gain of the source follower circuit can be suppressed. it can.

In the above-mentioned source follower circuit, n-type depletion type field effect transistors are used for FET1 and FET2. However, similar effects can be obtained by using n-type enhancement type field effect transistors.

The source of the FET 1 and the FET 3 in FIG.
Even if a diode or a resistor is inserted between the drain of the FET2 and the drain of the FET4 to form a level shift type source follower circuit, the FET3 and the FET4 have the same configuration as that of FIG. By doing so, a decrease in the gain can be suppressed.

[0021]

Since the present invention is configured as described above, it is possible to provide a source follower circuit having a small gain reduction rate.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional source follower circuit.

[Explanation of symbols]

FET1 to FET4 Field effect transistors, 5, 6
Resistance, 11,12 input terminal, 13,14 output terminal,
15 Power supply terminal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03F 1/00-3/00 H03K 19/00

Claims (1)

(57) [Claims] A first field-effect transistor (hereinafter referred to as an FET) to which a positive-phase signal is supplied to a gate; a second FET to which a negative-phase signal is supplied to a gate;
A third FET having a drain connected to the source of ET;
A fourth FET connected to a source and a drain of the second FET;
And the FET, and a power source connected to the drain of the second FET to the drain of the first FET, said first and third
And a second output terminal for outputting a negative-phase signal from the connection point between the second and fourth FETs. In the source follower circuit, the source of the third FET is connected to one terminal of a first resistor and the gate of the fourth FET, and the source of the fourth FET is connected to one terminal of a second resistor. Connected to the gate of the third FET;
A source follower circuit, wherein the other terminal of the second resistor is grounded.