JP3788707B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electronic apparatus in which such an electro-optical device is mounted as a component. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and the electro-optical device and the electronic device are semiconductor devices.
[0002]
[Prior art]
In recent years, attention has been paid to an active matrix liquid crystal display device in which a circuit is constituted by a thin film transistor (hereinafter referred to as TFT) using a polysilicon film. This realizes high-definition image display by controlling the electric field applied to the liquid crystal in a matrix by a plurality of pixels arranged in a matrix.
[0003]
In such an active matrix type liquid crystal display device, a capacitor (capacitor) is formed by the pixel electrode formed for each pixel and the counter electrode formed on the opposite side via the liquid crystal. Since it is small, it is usually compensated by forming a storage capacitor (also called Cs) separately from it.
[0004]
Although there are various storage capacitor structures (Cs structures), a structure in which an insulating film is sandwiched between two transparent conductive films in consideration of the aperture ratio in a transmissive liquid crystal display device has been reported (Japanese Patent Laid-Open No. 8-43854). No., JP-A-8-306926).
[0005]
According to the Cs structure described in the above publication, a large capacity can be secured without impairing the aperture ratio by using both of the two electrodes constituting the storage capacitor as transparent conductive films such as ITO. A conventional structure is shown in FIG.
[0006]
In FIG. 2, reference numeral 201 denotes a capacitor electrode, which is formed of a transparent conductive film. An interlayer insulating film 202 serving also as a storage capacitor dielectric is formed thereon, and a pixel electrode 203 is further formed.
[0007]
However, in such a structure, the coverage defect of the interlayer insulating film 202 may be a problem at the end portion (region surrounded by a dotted line) 204 of the capacitor electrode. In other words, a thin dielectric is preferable because it can increase the capacity, but if it is thin, a short circuit between the capacitive electrode 201 and the pixel electrode 203 becomes a problem. Therefore, there is a trade-off relationship that a certain degree of film thickness is required to fulfill the function as an interlayer insulating film.
[0008]
For example, since the transparent conductive film has a higher resistance than the metal film, the thickness of the capacitor electrode 201 needs to be about 100 to 200 nm even in consideration of the potential distribution. Therefore, in order to completely cover the capacitor electrode 201, an insulating film having a thickness of at least 200 nm is required. However, since the capacity is inversely proportional to the film thickness of the dielectric, increasing the film thickness is not desirable for securing a large capacity.
[0009]
As described above, it is possible to increase the area where the storage capacitor can be formed without impairing the aperture ratio by sandwiching two sets of transparent conductive films between insulating films, but there are still many problems. It was the current situation.
[0010]
[Problems to be solved by the invention]
The present invention is a technique for solving the above-described problems, and an object thereof is to further improve an electro-optical device having a storage capacitor using two pairs of transparent conductive films. Another object is to provide a higher quality semiconductor device.
[0011]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
A semiconductor device having a plurality of pixel TFTs arranged in a matrix and a storage capacitor connected to each of the plurality of pixel TFTs,
A first transparent conductive film having a first opening;
A capacitor insulating film that covers the first transparent conductive film and has a second opening inside the first opening;
An interlayer insulating film that covers the second opening and is patterned above the pixel TFT;
A second transparent conductive film formed in contact with the interlayer insulating film and the capacitor insulating film, and the storage capacitor is the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film It is characterized by comprising a laminated structure.
[0012]
In addition, the configuration of other inventions is as follows:
A semiconductor device having a plurality of pixel TFTs arranged in a matrix and a storage capacitor connected to each of the plurality of pixel TFTs,
A first transparent conductive film having a first opening;
A capacitor insulating film that covers the first transparent conductive film and has a second opening inside the first opening;
An interlayer insulating film that covers the second opening and is patterned above the pixel TFT;
The holding having a structure in which the second transparent conductive film formed in contact with the interlayer insulating film and the capacitor insulating film, and the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film are stacked. Capacity,
Have
The first transparent conductive film is grounded through a pad electrode formed of the second transparent conductive film.
[0013]
In the above configuration, the interlayer insulating film is preferably a resin material. Examples of such a resin material include polyimide, acrylic, polyamide, polyimide amide, and BCB (benzocyclobutene). Further, it is also preferable to use an interlayer insulating film of a light shielding resin material (a resin material in which a black pigment or a metal element is dispersed) or a laminated structure of a light shielding resin material and a transparent resin material.
[0014]
The present invention having the above configuration will be described in detail below.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a liquid crystal display device using the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a plurality of pixels arranged in a matrix and storage capacitors provided in each of the pixels.
[0016]
In FIG. 1, reference numeral 101 denotes a substrate having an insulating surface, on which a pixel TFT 102 formed by a known means is formed. A planarizing film (first interlayer insulating film) 103 was formed so as to cover the pixel TFT 102. Although any insulating film can be used for the planarizing film 103, it is preferable to use a resin material such as polyimide, acrylic, or BCB (benzocyclobutene) in order to achieve high planarity.
[0017]
A first transparent conductive film 104 was first formed on the planarizing film 103, an opening (first opening) was formed above the drain electrode 110, and then a capacitor insulating film 105 was formed. As the first transparent conductive film 104, tin oxide, ITO (indium tin oxide), or the like may be used. The first transparent conductive film 104 functions as a lower electrode of the storage capacitor.
[0018]
As the capacitor insulating film 105, a transparent insulating film such as silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, or aluminum oxide (alumina) was used. The capacitor insulating film 105 functions as a dielectric of the storage capacitor and is formed over the entire area of the pixel. Therefore, an insulating film with high transmittance is preferable.
[0019]
In the present invention, the area of the storage capacitor can be secured large, and the film thickness of the dielectric can be reduced (described later), so that an insulating film having a relatively high relative dielectric constant is not required. Therefore, since it is possible to select an optimum insulating film with the highest priority on increasing the transmittance, a bright image display is possible.
[0020]
Next, an opening (second opening) 106 was formed in the capacitor insulating film 105. This is an opening for securing a connection portion (hereinafter referred to as a drain connection portion) for connecting the pixel electrode and the drain electrode 110 later. The opening 106 is formed inside the opening (first opening) provided in the first transparent conductive film 104.
[0021]
Then, an insulating film 107 having a low relative dielectric constant was formed so as to cover the opening 106, and the insulating film 107 was patterned. In the patterning step, only the insulating film 107 formed on the portion where the storage capacitor is formed and the drain connection portion is selectively removed, a contact hole is formed in the drain connection portion (opening portion 106), and the capacitor insulating film 105 is formed. It was in an exposed state. That is, a pattern is formed above the pixel TFT 102.
[0022]
The insulating film 107 is preferably made of a resin material. As the resin material, polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene (BCB), or the like can be used. Needless to say, an insulating film containing silicon other than the resin material (such as silicon oxide or silicon nitride) can be used alone, or an insulating film containing silicon and a resin material can be stacked.
[0023]
A second transparent conductive film was formed thereon, and the second transparent conductive film was patterned to form a pixel electrode 108. The pixel electrode 108 was brought into contact with the capacitor insulating film 105 in the pixel to form a storage capacitor 109 composed of the first transparent conductive film / capacitor insulating film / second transparent conductive film.
[0024]
The pixel electrode 108 is electrically connected to the drain electrode 110 of the TFT 102, and the voltage applied to the pixel electrode 108 is controlled by the TFT 102. Although FIG. 1 shows a structure in which the pixel electrode 108 is connected to the drain electrode 110, a structure in which the pixel electrode 108 is directly connected to the active layer of the TFT 102 may be used.
[0025]
In the structure shown in FIG. 1, the TFT 102 is completely shielded by a black mask provided on the counter substrate side of the liquid crystal display device. This is to prevent the active layer of the TFT 102 from being irradiated with light. Of course, a structure in which a light shielding layer is formed between the substrate 101 and the TFT 102 is also possible.
[0026]
A feature of the present invention configured as described above is that the film thickness of the capacitor insulating film 105 (dielectric of the storage capacitor) can be freely adjusted. In the structure described in the conventional example, a film thickness of 200 nm or more is required due to the problem of coverage. However, in the structure of the present invention, the first transparent conductive film 104 and the pixel electrode 108 are completely insulated and separated by the insulating film 107. , And a thickness of about 10 to 200 nm (preferably 50 to 100 nm). That is, the thickness of the capacitor insulating film 105 can be made thinner than that of the first transparent conductive film 104.
[0027]
The reason why the lower limit of the film thickness is set to 10 nm is that the breakdown voltage is weak and the dielectric breakdown is liable to occur below this value. Another reason is that below this, it is difficult to ensure a uniform film thickness. In view of such a reason, it can be said that a film thickness of about 50 to 100 nm is preferable.
[0028]
Basically, there is no upper limit to the thickness of the capacitor insulating film 105. However, if the thickness is too large, it is difficult to secure a large capacity and the throughput is lowered. In this sense, the applicant considers the upper limit to be 200 nm (preferably 100 nm).
[0029]
Thus, the fact that the film thickness of the dielectric of the storage capacitor can be set freely is a very great advantage. As is generally known, there is a condition (antireflection condition) that increases the transmittance when thin films having different refractive indexes are laminated. This relationship is given by nd = λ / 4 where n is the refractive index, d is the film thickness, and λ is the transmitted light wavelength.
[0030]
In the present invention, since the selection range of the dielectric material forming the storage capacitor and the film thickness is wide, it is easy to adjust the term nd in the above formula. Therefore, by controlling the film thickness of each laminated film so as to match the antireflection condition, a high transmittance can be realized, and a pixel region capable of displaying a bright image while functioning as a storage capacitor can be formed.
[0031]
The present invention configured as described above will be described in more detail with reference to the following examples.
[0032]
【Example】
[Example 1]
In this embodiment, an example of a process for manufacturing an active matrix liquid crystal display device will be described with reference to FIGS. In this embodiment, the description will be made with attention paid to one pixel of the pixel matrix circuit, but it goes without saying that a driver circuit and a signal processing circuit can be integrally formed on the same substrate.
[0033]
First, a glass substrate provided with a base film made of silicon oxide on the surface was prepared as a substrate 301 having an insulating surface. Of course, in addition to the glass substrate, a quartz substrate (there may be no base) or a ceramic glass substrate may be used, or a silicon wafer on which a thermal oxide film is formed may be used. In addition, although a balance between heat resistance and process temperature is achieved, it is possible to use a plastic substrate as the substrate.
[0034]
It is also effective to provide a heat dissipation layer such as a metal film or an aluminum nitride film between the substrate and the base film.
[0035]
Next, a TFT was formed on the substrate 301. Since the present invention does not depend on the TFT structure, the TFT can be manufactured using any known means. Therefore, only an outline will be described in this embodiment.
[0036]
First, an active layer 302 made of a semiconductor thin film was formed on the substrate 301. As the semiconductor thin film, any material such as an amorphous silicon thin film, a polycrystalline (or microcrystalline) silicon thin film, a single crystal silicon thin film, or a silicon germanium thin film can be used. Any known means may be used as the crystallization technique for changing the amorphous silicon thin film to the polycrystalline silicon thin film.
[0037]
Next, a 100 nm thick silicon oxide film was formed as the gate insulating film 303, and a gate wiring 304 was formed thereon. In this embodiment, a structure in which titanium is laminated on tantalum is used as the gate wiring 304. Of course, other materials can be used.
[0038]
In this specification, a portion of the gate wiring that overlaps with the active layer is particularly called a gate electrode. In the source wiring, a portion in contact with the active layer is particularly called a source electrode.
[0039]
In this way, the state of FIG. Next, the gate insulating film 303 was etched using the gate wiring 304 as a mask to form a gate insulating film 305 having a new shape. Then, impurity ions imparting one conductivity in a self-aligning manner were added to the active layer 302 using the gate wiring 304 and the gate insulating film 305 as masks. (Fig. 3 (B))
[0040]
In the step shown in FIG. 3B, the technique described in Japanese Patent Application Laid-Open No. 7-135318 by the present applicant was used. That is, the impurity ion addition step was performed in two steps, a low acceleration voltage and a high acceleration voltage, to form a source region 306, a drain region 307, and an LDD region 308. After the impurity ions were added, activation was performed by laser annealing, furnace annealing, or the like.
[0041]
Next, an interlayer insulating film 309 was formed to a thickness of about 1 μm. In this embodiment, a laminated structure in which a silicon nitride film having a thickness of 25 nm is first formed and an acrylic resin film having a thickness of 900 nm is formed thereon.
[0042]
Next, contact holes were formed in the interlayer insulating film 309, a metal layer having a three-layer structure of titanium / aluminum / titanium was formed, and patterning was performed to form the source wiring 310 and the drain electrode 311. Thus, a pixel TFT as shown in FIG. 3C was completed.
[0043]
Next, a planarization film 312 was formed so as to cover the pixel TFT. In this embodiment, acrylic is used as the planarizing film 312, but other resin materials may be used. A first transparent conductive film 313 was formed on the planarization film 312 and patterned to provide a first opening 314 above the drain electrode 311. Further, a capacitor insulating film 315 was formed thereon. (Fig. 3 (D))
[0044]
As the first transparent conductive film 313, an ITO (indium tin oxide) film having a thickness of 100 nm formed by a sputtering method was used. In this embodiment, ITO is used as a target, and a mixed gas of argon and oxygen is used as a sputtering gas, and the film formation pressure is 3 × 10. ^-3 set to torr. Further, the film formation was performed with DC current control of 1.5 A, and the substrate temperature was set to room temperature.
[0045]
When a resin material is used as a base (planarization film) as in this embodiment, a process that requires heating the substrate is inappropriate because degassing from the resin material becomes a problem. In this respect, the sputtering method is a suitable means because it can form a film at room temperature.
[0046]
As the capacitor insulating film 315, a 50 nm thick silicon oxide film formed by sputtering was used. At this time, it is an advantage of the present invention that the capacitor insulating film 315 can be made thinner than the first transparent conductive film 313.
[0047]
In this embodiment, the target is SiO. ₂ And a deposition pressure of 3 × 10 using a mixed gas of argon (30 sccm) and oxygen (10 sccm) as a sputtering gas. ^-3 set to torr. In addition, the film formation was performed under RF power control of 2000 W, and the substrate temperature was room temperature.
[0048]
In this case, when the substrate temperature is high, the film quality of the first transparent conductive film 313 made of ITO becomes a crystalline state, which causes a problem that etching becomes difficult.
[0049]
According to the applicant's knowledge, it has been found that when the film forming temperature of the capacitor insulating film 315 is 180 ° C. or higher, etching of the ITO film becomes difficult. On the other hand, if the substrate temperature is lowered too much, the film quality of the capacitor insulating film 315 made of silicon oxide deteriorates. That is, there is an adverse effect that the breakdown voltage is lowered.
[0050]
Experimental results have shown that it is necessary to form a film in a temperature range of preferably 180 ° C. or lower (preferably 100 to 150 ° C.), and for that purpose, sputtering is the most preferable film forming method. It can be said.
[0051]
Although a silicon oxide film is used as the capacitor insulating film 315 in this embodiment, other transparent insulating films may be used. As the relative dielectric constant is higher, a sufficient capacity can be ensured even if the film thickness is increased, so that the occurrence rate of defects due to a short circuit can be further reduced. Of course, as described above, even if the film thickness is too thick, the throughput is lowered, so it is better to set the upper limit to 200 nm.
[0052]
When the state of FIG. 3D is obtained in this way, a second opening 316 is formed at a position where a contact hole for electrically connecting the drain electrode 311 and a pixel electrode (not shown) is formed later. The diameter of the second opening 316 is smaller than that of the first opening 314 and is formed inside the first opening 314. Moreover, it is preferable to make it sufficiently larger than the diameter of a contact hole to be formed later. By doing so, a short circuit between the first transparent conductive film 313 and the pixel electrode (not shown) can be prevented. (Fig. 4 (A))
[0053]
In this embodiment, the second opening 316 is formed with a 3 μm margin in the diameter of the contact hole to be formed later. If the radius of the contact hole is r μm, it can be said that it is sufficient to set the radius of the second opening to (r + 3) μm. Of course, the contact hole and the second opening 316 are formed concentrically.
[0054]
Next, an interlayer insulating film (second interlayer insulating film) 317 was formed to cover the capacitor insulating film 315 and the second opening 316. As the interlayer insulating film 317, acrylic having a relative dielectric constant of 3.2 was used, but a material having a relative dielectric constant of 4.0 or less (preferably 3.5 or less) (typically a resin such as polyimide, polyamide, polyimide amide, or benzocyclobutene). Material) is preferred. Further, in consideration of flatness, it is desirable to use benzocyclobutene. (Fig. 4 (B))
[0055]
After the interlayer insulating film 317 was formed, patterning was performed to remove the interlayer insulating film 317 formed in a portion where a storage capacitor is to be formed later. The portion where the storage capacitor is formed substantially coincides with the image display area (pixel). As a result, an interlayer insulating film 318 was patterned over the pixel TFT.
[0056]
In this state, since the second opening 316 is covered with the patterned interlayer insulating film 318, a short circuit occurs between the pixel electrode (not shown) and the end face of the first transparent conductive film 313. I was able to prevent it.
[0057]
In addition, a contact hole 319 for connecting a pixel electrode (not shown) and the drain electrode 311 was formed in the region where the second opening 316 was formed simultaneously with the formation of the pattern of the interlayer insulating film. (Fig. 4 (C))
[0058]
In this step, first, a resist mask (not shown) was formed at a predetermined position of the interlayer insulating film 317 and etched to form a patterned interlayer insulating film 318. Then, the planarizing film 312 is formed by etching using the resist mask as it is. At this time, if the condition is such that a taper is formed on the side wall of the contact hole, disconnection of the pixel electrode can be prevented.
[0059]
Then, an ITO film having a thickness of 120 nm was formed as the second transparent conductive film, and the pixel electrode 320 was formed by patterning. In a portion where the pixel electrode 320 is in contact with the capacitor insulating film 315, a storage capacitor 321 is formed by the capacitor insulating film 315 sandwiched between two transparent conductive films (first transparent conductive film and second transparent conductive film). I was able to. (Fig. 4 (D))
[0060]
The pixel structure of the present embodiment having the above-described configuration has an advantage that the area serving as the storage capacitor occupies almost the entire area of the pixel and can substantially secure the same area as the image display area.
[0061]
Further, the characteristic points in the structure of this embodiment are specifically shown in FIGS. FIG. 15A is a TEM observation photograph of the peripheral part of the contact hole. FIG. 15B is a TEM observation photograph in which an end portion of the first transparent conductive film in FIG. 15A is enlarged, and FIG. 15C is a schematic diagram of FIG. . Note that in FIGS. 15A to 15C, a depressed portion is seen in the interlayer insulating film 309, which is generated at the time of sampling, and is not related to the structure of the present invention.
[0062]
As is apparent from the drawings shown in FIGS. 15A to 15C, the characteristic features of the structure of this embodiment are the end of the first transparent conductive film 313 and the pixel electrode 320 in the contact hole. Can be completely insulated and separated by the interlayer insulating film 318, so that the thickness of the capacitor insulating film 315 can be reduced to 10 to 200 nm (preferably 50 to 100 nm).
[0063]
Accordingly, since the proportion of the capacitance forming area is large and a storage capacitor having a thin dielectric film thickness can be formed, a sufficient capacitance can be secured even if the relative dielectric constant is not so high. This means that the degree of freedom of materials that can be selected is greatly expanded.
[0064]
As a result, it is possible to select materials with priority on high transmittance characteristics, and to achieve high transmittance with an antireflection effect by appropriately combining the film thickness of transparent conductive film and capacitive insulating film Is also possible. In that respect, in the conventional structure, since the dielectric material and film thickness are limited to some extent, such a degree of freedom is small.
[0065]
Note that the state shown in FIG. 4D is a state in which the TFT formation side substrate (active matrix substrate) of the liquid crystal display device is almost completed. FIG. 16 shows an SEM photograph of the actual active matrix substrate (pixel portion) in this state observed from above. In FIG. 16, the area that appears to be indented (indicated by A in FIG. 16) is the storage capacitor. Actually, there is a step of forming an alignment film so as to cover the pixel electrode.
[0066]
Further, if an opposing substrate having an opposing electrode and an alignment film is prepared and a liquid crystal material is sealed between the active matrix substrate and the opposing substrate, an active matrix type liquid crystal display device having a structure as shown in FIG. 6 is completed. . Since the process of encapsulating the liquid crystal material may use a known cell assembly process, detailed description thereof is omitted.
[0067]
In FIG. 6, 601 is a substrate having an insulating surface, 602 is a pixel matrix circuit, 603 is a source driver circuit, 604 is a gate driver circuit, 605 is a counter substrate, 606 is an FPC (flexible printed circuit), and 607 and 608 are outside. IC chip attached.
[0068]
The IC chips 607 and 608 may be attached as necessary. In some cases, a circuit having an equivalent function may be integrally formed with a source driver circuit, a gate driver circuit, or the like instead of the IC chip. That is, a signal processing circuit such as a D / A converter or a γ correction circuit may be configured with a TFT.
[0069]
Further, in this embodiment, the liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromic) display device as long as it is an active matrix display device. It goes without saying that it is also possible to do.
[0070]
[Example 2]
In this embodiment, in the structure shown in FIG. 1, a light-blocking resin material (typically a black resin material) is used as the insulating film 107, and the portion is used as a black mask. Note that the structure of this example is obtained only by changing the material of the insulating film 107 shown in FIG. 1, and the structure shown in this example can be easily realized by following the manufacturing steps shown in Example 1. it can.
[0071]
In this embodiment, the black resin material can be a black pigment, a metal (titanium, chromium, etc.) material or a resin material in which a carbon-based material (graphite, etc.) is dispersed. The OD value is desirably 3 or more. In this embodiment, a resin material (OD value is 3) in which graphite is dispersed is used.
[0072]
The OD value is a guideline indicating the light-shielding property of the thin film, and OD = -Log _Ten T (T is transmittance and T = 0.001 is substituted when the transmittance is 0.1%). That is, the higher the absolute value of the OD value, the higher the transmittance.
[0073]
As described above, by using the black resin material, the TFT can be covered with the black interlayer insulating film, and can be used as it is as a black mask. That is, the process can be simplified by using the technique of this embodiment.
[0074]
Example 3
In this embodiment, a laminated structure of a transparent resin material such as acrylic and polyimide and a black resin material is employed instead of the interlayer insulating film 107 in FIG. The configuration of this example can be easily realized by following the manufacturing steps of Example 1 as in Example 2.
[0075]
Example 4
In this embodiment, a pixel structure of an active matrix liquid crystal display device manufactured using the present invention will be described. A top view of the pixel structure of this embodiment is shown in FIG.
[0076]
In FIG. 5A, 501 is an active layer, 502 is a gate wiring (a portion overlapping with the active layer 501 is particularly called a gate electrode), 503 is a source wiring (a portion in contact with the active layer 501 is especially called a source electrode), Reference numeral 504 denotes a drain electrode. FIG. 5A corresponds to a top view in the state of FIG. 3C in the first embodiment.
[0077]
Next, FIG. 5B shows a top view corresponding to the state in FIG. 4A in the first embodiment. In FIG. 5B, 505 is a first transparent conductive film, and 506 is an opening. A drain electrode 504 exists below the opening provided in the first transparent conductive film 505.
[0078]
Next, FIG. 5C shows a top view corresponding to the state of FIG. 4D in the first embodiment. In FIG. 5C, reference numeral 507 denotes an interlayer insulating film, which corresponds to the interlayer insulating film 318 in FIG. Reference numeral 508 denotes a pixel electrode, and reference numeral 509 denotes a contact hole (corresponding to the contact hole 319 in FIG. 4C). The pixel electrode 508 is formed so that the edge covers the gate wiring 502 and the source wiring 503 so that the influence of the electric field disturbance generated at the edge portion is not noticeable.
[0079]
The pixel structure shown in this embodiment is an embodiment when the present invention is implemented, and the present invention is not limited to this structure. However, when the structure of this embodiment is employed, the entire pixel region functions as a storage capacitor, so that a sufficient storage capacitor can be secured even in a liquid crystal display device having a high-definition pixel structure.
[0080]
Example 5
In this embodiment, a structure for fixing the first transparent conductive film 104 functioning as the lower electrode of the storage capacitor 109 to the common potential (ground potential) in the structure shown in FIG. 1 will be described with reference to FIG.
[0081]
The structure shown in FIG. 7 is an enlarged view of the grounding pad electrode provided outside the image display area (panel portion) of the liquid crystal display device. A capacitive insulating film 702 is formed on the first transparent conductive film 701 with an opening 703. The opening 703 was formed at the same time as the step of FIG.
[0082]
Reference numeral 704 denotes an interlayer insulating film made of a resin material, and a pad electrode 705 used as a common contact pad is formed thereon with a second transparent conductive film (same material as the pixel electrode). This pad electrode 705 was formed simultaneously with the step of FIG.
[0083]
In the structure of this embodiment, the first transparent conductive film 701 and the pad electrode 705 come into contact with each other at the contact surface 706 to have the same potential. Then, the first transparent conductive film 701 is fixed to the ground potential by the pad electrode 705 being grounded.
[0084]
The common contact pad can also function as a pad for fixing the counter electrode to the ground potential. A paste material mixed with conductive particles is formed on the pad electrode 705, and in this state, the active matrix substrate and the counter substrate are bonded to establish conduction between the counter electrode provided on the counter substrate and the pad electrode. The electrode can be fixed at ground potential.
[0085]
In this manner, using a transparent conductive film formed in the same layer as the pixel electrode as the pad electrode 705 is effective because the process can be greatly simplified.
[0086]
Note that the structure of this embodiment can be combined with all of the embodiments 1 to 4.
[0087]
Example 6
In this embodiment, an example in which a step of removing the planarizing film on the drain electrode of the pixel TFT is added will be described with reference to FIG.
[0088]
First, in the process of Example 1, the state shown in FIG. Then, dry etching using oxygen plasma was performed in the state of FIG. At this time, a part of the planarizing film 312 made of a resin material is removed using the patterned capacitor insulating film 315 as a mask.
[0089]
FIG. 8A shows a state in which an interlayer insulating film 12 made of a resin material (polyimide in this embodiment) is formed after forming the drop portion 11 by a dry etching method. Note that the opening width of the dropping portion 11 is substantially the same as the opening width of the second opening portion 316 shown in FIG.
[0090]
Then, the interlayer insulating film 12 was patterned to form a patterned interlayer insulating film 13, and at the same time, a contact hole 14 for connecting the pixel electrode and the TFT was formed. (Fig. 8 (B))
[0091]
After the contact hole 14 was formed in this way, a second transparent conductive film was formed and patterned to form a pixel electrode 15 connected to the TFT. At this time, the storage capacitor 16 was also formed at the same time. At the same time, the ground pad structure shown in the fifth embodiment may be formed.
[0092]
The structure of this embodiment is advantageous in that the contact hole 14 can be formed only by etching an interlayer insulating film made of the same material.
[0093]
Example 7
This embodiment shows a manufacturing process of an active matrix type liquid crystal display device as in Embodiment 1. This embodiment is a modification of the second and third embodiments. In Examples 2 and 3, the pixel TFT is shielded from light using a black resin for the planarizing film. However, in this example, a black mask is formed on the active matrix substrate side to shield the pixel TFT. .
[0094]
A present Example is described using FIG. 9, FIG. In this embodiment, the description will be given focusing on one pixel of the pixel matrix circuit, but it goes without saying that a driver circuit and a signal processing circuit can be integrally formed on the same substrate.
[0095]
A glass substrate provided with a base film made of silicon oxide on the surface is prepared as the substrate 800 having an insulating surface, and the structure of FIG. This is shown in FIG.
[0096]
As shown in FIG. 9A, an active layer made of a semiconductor thin film, a gate insulating film 802 made of a silicon oxide film, and a gate wiring 803 made of a tantalum / titanium two-layer film are stacked on the surface of the substrate 800 in this order. ing. A source region 804, a drain region 805, and an LDD region 806 are formed in the active layer. An interlayer insulating film 807 is formed on the entire surface of the substrate so as to cover the gate wiring 803. As the interlayer insulating film 807, a laminated film made of a 25 nm thick silicon nitride film and a 900 nm thick acrylic resin film is formed.
[0097]
Contact holes were formed in the interlayer insulating film 807, and a source wiring 808 and a drain electrode 809 having a three-layer structure of titanium / aluminum / titanium were formed. Thus, the pixel TFT shown in FIG. 9A was completed.
[0098]
Next, a planarization film 810 was formed so as to cover the pixel TFT. In this embodiment, acrylic is formed by a coating method as the planarizing film 810. The thickness of acrylic was 0.7 μm at the thickest part.
[0099]
Next, a titanium film having a thickness of 200 nm is formed by a sputtering method, and patterned by a dry etching method using a chlorine-based gas, thereby forming a black mask 811 made of titanium. Acrylic was formed as a planarizing film 812 on the entire surface of the substrate by a coating method. The thickness of this acrylic was 0.5 μm at the thickest part. The black mask 811 is integrally formed with a pixel matrix circuit and connected to a common potential. (Fig. 9 (B))
[0100]
Next, an ITO (indium tin oxide) film having a thickness of 115 nm was formed as the first transparent conductive film 813 by sputtering. The first transparent conductive film 813 constitutes a storage capacitor electrode. The ITO film is formed by using ITO as a target, a mixed gas of argon and oxygen as a sputtering gas, and a film forming pressure of 3 × 10. ^-3 DC current control of torr and 1.5 A was performed, and the substrate temperature was set to room temperature.
[0101]
A first opening 814 was formed above the drain electrode 809 in the first transparent conductive film 813 by wet etching using an etchant dedicated to ITO. (Figure 9 (C))
[0102]
A silicon oxide film having a thickness of 150 nm was formed as a capacitor insulating film 815 over the first transparent conductive film 813 by a sputtering method. The silicon oxide film formation conditions are as follows. ₂ And using a mixed gas of argon (30 sccm) and oxygen (10 sccm) as the sputtering gas, the film forming pressure is 3 × 10. ^-3 torr. In addition, the film formation was performed under RF power control of 2000 W, and the substrate temperature was room temperature.
[0103]
The capacitor insulating film 815 made of silicon oxide was etched with buffered hydrofluoric acid to form a second opening 816. The diameter of the second opening 816 is smaller than that of the first opening 814 and is formed inside the first opening 814. Here, a margin of 3 μm was taken for the second opening 816 than the diameter of the contact hole. (Figure 9 (D))
[0104]
Next, an interlayer insulating film 819 was formed to cover the capacitor insulating film 815 and the second opening 816. As the interlayer insulating film 819, acrylic was formed by a coating method. The thickest part of the acrylic was 0.5 μm. (Fig. 10 (A))
[0105]
Next, a contact hole 822 is formed in the interlayer insulating film 819 made of acrylic and the planarizing films 810 and 812, and at the same time, the interlayer insulating film 819 in a portion for forming a storage capacitor is removed.
[0106]
In this process, a photoresist mask is used to ₂ / CF _Four Using gas, the interlayer insulating film 819 made of acrylic is etched to form a patterned interlayer insulating film 821, and the same photoresist mask is used as it is. ₂ / CF _Four The planarization films 812 and 810 were dry-etched with a gas to form contact holes 822. At this time, when the taper is formed on the side wall of the contact hole 822, disconnection of the pixel electrode can be prevented.
[0107]
Then, an ITO film having a thickness of 120 nm was formed by sputtering as the second transparent conductive film. The second transparent conductive film constitutes a pixel electrode and an electrode of a storage capacitor. The ITO film was etched with a special etchant to form a pixel electrode 823. In a portion where the pixel electrode 823 is in contact with the capacitor insulating film 815, a storage capacitor 824 is formed by the capacitor insulating film 815 sandwiched between two transparent conductive films (a first transparent conductive film and a second transparent conductive film). .
[0108]
Also in this embodiment, since the second opening 816 is covered with the patterned interlayer insulating film 821, the pixel electrode 823 can be prevented from being short-circuited with the end face of the first transparent conductive film 813.
[0109]
For example, it is assumed that the structure of Example 1 uses a combination of acrylic as the planarization film 312 and polyimide as the interlayer insulating film 317. In this case, since the etching rate of acrylic is slightly faster, there is a possibility that the chipping occurs under the first transparent conductive film 313, and there is a risk of causing poor coverage of the pixel electrode, that is, poor disconnection.
[0110]
In that respect, since the contact hole is formed entirely in the same material in the structure of the present embodiment, there is no abnormality in the shape of the contact hole due to the difference in etching rate, and it is possible to prevent the pixel electrode from being disconnected due to a gap or the like. It was possible.
[0111]
In addition, the structure of a present Example can be combined with any Example shown in Examples 1-5. Regardless of the configuration, the effect of preventing disconnection failure of the pixel electrode due to the shape of the contact hole is the same.
[0112]
Example 8
In this embodiment, as in the seventh embodiment, a black mask is formed on the active matrix substrate side in order to shield the pixel TFT.
[0113]
A glass substrate provided with a base film made of silicon oxide on the surface is prepared as the substrate 900 having an insulating surface, and the structure shown in FIG. This is shown in FIG.
[0114]
As shown in FIG. 11A, an active layer made of a semiconductor thin film, a gate insulating film 902 made of a silicon oxide film, and a gate wiring 903 made of a tantalum / titanium two-layer film are stacked on the surface of the substrate 900 in this order. ing. A source region 904, a drain region 905, and an LDD region 906 are formed in the active layer. An interlayer insulating film 907 is formed on the entire surface of the substrate so as to cover the gate wiring 903. As the interlayer insulating film 907, a laminated film made of a 25 nm thick silicon nitride film and a 900 nm thick acrylic resin film is formed.
[0115]
Contact holes were formed in the interlayer insulating film 907, and a source wiring 908 and a drain electrode 909 having a three-layer structure of titanium / aluminum / titanium were formed. Thus, the pixel TFT shown in FIG. 11A was completed.
[0116]
Next, the pixel TFT was covered with a planarizing film 910 made of acrylic. Acrylic was formed by a coating method so that the thickest part was 1.2 μm. Next, a first transparent conductive film 911 made of ITO having a thickness of 115 nm, a capacitor insulating film 912 made of silicon oxide having a thickness of 150 nm, and a metal film 913 for black mask made of a titanium film having a thickness of 200 nm are stacked by sputtering. Then, a film was formed on the surface of the planarizing film 910. (Fig. 11 (B))
[0117]
Next, a photoresist mask (not shown) is formed, and the black mask metal film 913 made of titanium and the capacitor insulating film 912 made of silicon oxide are dry-etched to form a first opening 915 above the drain electrode 909. . Chlorine gas is used as the etching gas for the titanium film, and CHF is used as the etching gas for the silicon oxide film. _Three Fluorine gas such as is used. The step of forming the first opening is preferably performed by anisotropic dry etching rather than wet etching. (Fig. 11 (C))
[0118]
After removing the photoresist mask for the first opening, a photoresist mask 916 is formed again. The black mask metal film 913 in the storage capacitor portion is removed by dry etching to form a black mask 917 made of titanium. By using a chlorine-based gas for etching the metal film 913, the capacitor insulating film 912 made of silicon oxide can function as an etching stopper. The black mask 917 is integrally formed with a pixel matrix circuit and is connected to a common potential. (Fig. 11 (D))
[0119]
Further, using the same photoresist mask 916, the first transparent conductive film 911 is etched with an ITO dedicated etchant to form a second opening 918. The diameter of the second opening 918 is smaller than that of the first opening 915 and is formed inside the first opening 915. A second opening 918 is formed with a margin of 3 μm. (Figure 11 (E))
[0120]
After the photoresist mask 916 was peeled off, an interlayer insulating film 919 was formed on the entire surface of the substrate so as to cover the black mask 917, the capacitor insulating film 912, and the second opening 918. As the interlayer insulating film 919, acrylic was formed by a coating method. The thickest part of the acrylic was 0.5 μm. (Fig. 12 (A))
[0121]
Next, a photoresist mask (not shown) is formed, and O ₂ / CF _Four The interlayer insulating film 919 made of acrylic with a gas is dry-etched to form a patterned interlayer insulating film 920. Continue O ₂ / CF _Four A contact hole 921 was formed by dry etching with gas and etching the planarizing film 910 made of acrylic. At this time, if the taper is formed on the side wall of the contact hole 921, the pixel electrode can be prevented from being disconnected. (Fig. 12 (B))
[0122]
Then, an ITO film having a thickness of 120 nm was formed by sputtering as the second transparent conductive film and patterned to form a pixel electrode 923. In a portion where the pixel electrode 923 is in contact with the capacitor insulating film 912, a storage capacitor 924 is formed by the capacitor insulating film 912 sandwiched between the pair of transparent conductive films (the first transparent conductive film 911 and the pixel electrode 923). (Figure 12 (C))
[0123]
Also in this embodiment, since the second opening 918 is covered with the patterned interlayer insulating film 920, the pixel electrode 923 can be prevented from being short-circuited with the end face of the first transparent conductive film 911.
[0124]
Here, in the step shown in FIG. 12B, the patterned interlayer insulating film 920 is formed so as not to cover the entire black mask (also referred to as a black matrix) 917, so that the pixel electrode 923 is a black mask. Since the pixel TFT is in an off state, the potential is connected to the common potential.
[0125]
Alternatively, in the step shown in FIG. 12B, the interlayer insulating film 919 can be patterned as shown in FIG. 12D to form a patterned interlayer insulating film 930. That is, a structure in which the pixel mask 931 and the black mask 917 are not connected can be obtained by covering the entire black mask (also referred to as black matrix) 917 with the patterned interlayer insulating film 930.
[0126]
Example 9
The CMOS circuit and the pixel matrix circuit formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display media.
[0127]
Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or electronic books). Etc.). Examples of these are shown in FIGS.
[0128]
FIG. 13A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.
[0129]
FIG. 13B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.
[0130]
FIG. 13C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0131]
FIG. 13D illustrates a goggle type display which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.
[0132]
FIG. 13E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.
[0133]
FIG. 13F illustrates a digital camera which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not illustrated). The present invention can be applied to the display device 2502 and other signal control circuits.
[0134]
FIG. 14A illustrates a front type projector which includes a display device 2601 and a screen 2602. The present invention can be applied to display devices and other signal control circuits.
[0135]
FIG. 14B illustrates a rear projector, which includes a main body 2701, a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0136]
Note that FIG. 14C illustrates an example of the structure of the display devices 2601 and 2702 in FIGS. 14A and 14B. The display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2805 to 2807, dichroic mirrors 2803 and 2804, optical lenses 2808 and 2809, a prism 2811, a liquid crystal display device 2810, and a projection optical system 2812. The projection optical system 2812 is configured by an optical system including a projection lens. In this embodiment, an example of a three-plate type using three liquid crystal display devices 2810 is shown. However, the present invention is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0137]
FIG. 14D shows an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes light sources 2813 and 2814, a combining prism 2815, collimator lenses 2816 and 2820, lens arrays 2817 and 2818, and a polarization conversion element 2819. Note that although the light source optical system shown in FIG. 14D uses two light sources, three or four or more light sources may be used. Of course, one light source may be used. In addition, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like in the light source optical system. It can also be used for a single plate type.
[0138]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.
[0139]
Example 10
In addition to the TN liquid crystal, various liquid crystals can be used for the liquid crystal display device manufactured according to the above embodiment. For example, 1998, SID, “Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability” by H. Furue et al., 1997, SID DIGEST, 841, “A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time ”by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.
[0140]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. ing.
[0141]
Here, FIG. 17 shows an example of the light transmittance characteristics of the thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optic response with respect to the applied voltage. The vertical axis of the graph shown in FIG. 17 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The transmission axis of the polarizing plate on the incident side of the liquid crystal display device is set to be substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal that substantially coincides with the rubbing direction of the liquid crystal display device. . Further, the transmission axis of the output-side polarizing plate is set to be substantially perpendicular (crossed Nicols) to the transmission axis of the incident-side polarizing plate.
[0142]
As shown in FIG. 17, it can be seen that when such a thresholdless antiferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible.
[0143]
When such a low-voltage thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having an analog driver, the power supply voltage of the image signal sampling circuit is suppressed to about 5V to 8V, for example. Is possible. Therefore, the operating power supply voltage of the driver can be lowered, and low power consumption and high reliability of the liquid crystal display device can be realized.
[0144]
Further, even when such a low-voltage thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having a digital driver, the output voltage of the D / A conversion circuit can be lowered. The operating power supply voltage of the A conversion circuit can be lowered, and the operating power supply voltage of the driver can be lowered. Therefore, low power consumption and high reliability of the liquid crystal display device can be realized.
[0145]
Therefore, using such a thresholdless antiferroelectric mixed liquid crystal driven at a low voltage makes it possible to use a TFT (for example, 0 nm to 500 nm or 0 nm to 200 nm) having a relatively small LDD region (low concentration impurity region). It is also effective when used.
[0146]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. Further, the driving method of the liquid crystal display device may be line-sequential driving so that the gradation voltage writing period (pixel feed period) to the pixel is lengthened to compensate for the small storage capacity.
[0147]
In addition, since low voltage drive is implement | achieved by using such a thresholdless antiferroelectric mixed liquid crystal, the low power consumption of a liquid crystal display device is implement | achieved.
[0148]
Note that any liquid crystal having electro-optical characteristics as shown in FIG. 17 can be used as the display medium of the liquid crystal display device of the present invention.
[0149]
【The invention's effect】
By implementing the present invention, the thickness of the capacitor insulating film sandwiched between the transparent conductive films can be freely set, so that the entire pixel area can be used as a storage capacitor without impairing the light transmittance in the pixel. It became possible to do.
[0150]
Therefore, when a high-definition active matrix display device with a small pixel area is formed, a sufficient storage capacity can be secured. In addition, since the light transmittance is sufficiently high even when the entire area in the pixel is a storage capacitor, a bright image display is possible. That is, a high-definition and high-quality electro-optical device and an electronic apparatus equipped with such an electro-optical device can be realized.
[Brief description of the drawings]
FIG. 1 illustrates a cross-sectional structure of a pixel and a storage capacitor.
FIG. 2 is a diagram showing a cross-sectional structure of a conventional pixel and a storage capacitor.
FIGS. 3A and 3B are diagrams illustrating a manufacturing process of a pixel structure. FIGS.
FIGS. 4A and 4B are diagrams illustrating a manufacturing process of a pixel structure. FIGS.
FIG. 5 is a top view of a pixel structure.
FIG. 6 is a diagram showing the appearance of an active matrix liquid crystal display device.
FIG. 7 is a diagram showing a cross-sectional structure of a common contact portion.
FIGS. 8A to 8D are diagrams illustrating a manufacturing process of a pixel structure. FIGS.
FIG. 9 illustrates a manufacturing process of a pixel structure.
FIGS. 10A and 10B are diagrams illustrating a manufacturing process of a pixel structure. FIGS.
FIG. 11 illustrates a manufacturing process of a pixel structure.
FIGS. 12A to 12C illustrate a manufacturing process of a pixel structure. FIGS.
FIG 13 illustrates an example of an electronic device.
FIG 14 illustrates an example of an electronic device.
FIG. 15 is a TEM observation photograph and a schematic diagram thereof.
FIG. 16 is a SEM observation photograph of the surface.
FIG. 17 is a graph showing applied voltage-transmittance characteristics of thresholdless antiferroelectric mixed liquid crystal.

Claims (11)

An active layer arranged in a matrix and having a source region and a drain region, a gate insulating film, a gate electrode, and a first interlayer insulating layer formed on the active layer, the gate insulating film, and the gate electrode A film, a source electrode formed on the first interlayer insulating film and connected to the source region, and a drain electrode formed on the first interlayer insulating film and connected to the drain region. A plurality of pixel TFTs;
A planarization film formed on the plurality of pixel TFTs;
A first transparent conductive film formed on the planarization film and having a first opening;
A capacitor insulating film that covers the first transparent conductive film and has a second opening inside the first opening;
A second interlayer insulating film that covers the second opening and is patterned above each of the plurality of pixel TFTs;
A second transparent electrode formed in contact with the second interlayer insulating film and the capacitor insulating film and connected to the drain electrode through a contact hole formed in the planarizing film and the second interlayer insulating film; A conductive film;
A storage capacitor formed of the first transparent conductive film, a laminate of the capacitive insulating film and the second transparent conductive film structure,
Have
The semiconductor device according to claim 1, wherein the second interlayer insulating film is removed in a region where the storage capacitor is formed . An active layer arranged in a matrix and having a source region and a drain region, a gate insulating film, a gate electrode, and a first interlayer insulating layer formed on the active layer, the gate insulating film, and the gate electrode A film, a source electrode formed on the first interlayer insulating film and connected to the source region, and a drain electrode formed on the first interlayer insulating film and connected to the drain region. A plurality of pixel TFTs;
A planarization film formed on the plurality of pixel TFTs;
A first transparent conductive film formed on the planarization film and having a first opening;
A capacitor insulating film that covers the first transparent conductive film and has a second opening inside the first opening;
A second interlayer insulating film covering the second opening and patterned over each of the plurality of pixel TFTs;
The second interlayer insulating film and formed in contact with the capacitor insulating film, the planarizing film and the second transparent connected to the drain electrode through a contact hole formed in the second interlayer insulating film A conductive film;
A storage capacitor formed of the first transparent conductive film, a laminate of the capacitive insulating film and the second transparent conductive film structure,
Have
The first transparent conductive film is grounded via a pad electrode formed of the same material as the second transparent conductive film ,
The semiconductor device according to claim 1, wherein the second interlayer insulating film is removed in a region where the storage capacitor is formed . An active layer arranged in a matrix and having a source region and a drain region, a gate insulating film, a gate electrode, and a first interlayer insulating layer formed on the active layer, the gate insulating film, and the gate electrode A film, a source electrode formed on the first interlayer insulating film and connected to the source region, and a drain electrode formed on the first interlayer insulating film and connected to the drain region. A plurality of pixel TFTs;
A planarization film formed on the plurality of pixel TFTs and having a drop portion;
A first transparent conductive film formed on the planarization film and having a first opening;
A capacitor insulating film that covers the first transparent conductive film and has a second opening inside the first opening;
A second interlayer insulating film that covers the second opening, is formed in the drop-in portion, and is patterned above each of the plurality of pixel TFTs;
A second layer connected to the drain electrode through a contact hole formed in contact with the second interlayer insulating film and the capacitor insulating film and formed in the second interlayer insulating film in the drop portion. A transparent conductive film;
A storage capacitor having a structure in which the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film are laminated;
Have
The planarizing film is removed on the drain electrode,
The opening width of the drop-in part and the opening width of the second opening part are the same,
The semiconductor device according to claim 1, wherein the second interlayer insulating film is removed in a region where the storage capacitor is formed. In any one of Claims 1 thru | or 3 ,
The semiconductor device , wherein the planarizing film is made of a resin material. In any one of Claims 1 thru | or 4,
The semiconductor device according to claim 2, wherein the second interlayer insulating film is made of a resin material. In any one of Claims 1 thru | or 4 ,
The second interlayer insulating film has a light shielding resin material or a laminated structure of a light shielding resin material and a transparent resin material. Form a base film on the substrate,
Forming an active layer on the base film;
Forming a gate insulating film on the active layer;
Forming a gate electrode on the gate insulating film;
Impurity ions are added to the active layer to form a source region and a drain region in the active layer,
Forming a first interlayer insulating film on the active layer, the gate insulating film and the gate electrode;
Forming a source electrode connected to the source region on the first interlayer insulating film;
By forming a drain electrode connected to the drain region on the first interlayer insulating film,
Forming a plurality of pixel TFTs in a matrix;
Forming a planarization film on the plurality of pixel TFTs;
Forming a first transparent conductive film on the planarizing film and forming a first opening in the first transparent conductive film;
A step of the first transparent conductive film to form a capacitor insulating film so as to cover the, by removing a portion of the capacitor insulating film, forming a second opening on the inner side than the first opening,
Forming a second interlayer insulating film covering the second opening;
Removing the second interlayer insulating film in a region where a storage capacitor is to be formed, and forming a pattern above each of the plurality of pixel TFTs;
Forming a contact hole reaching the drain electrode in the patterned second interlayer insulating film and the planarizing film;
Forming a second transparent conductive film connected to the drain electrode through the contact hole on the capacitor insulating film;
Have
A method for manufacturing a semiconductor device, wherein the storage capacitor is formed in a structure in which the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film are stacked. Form a base film on the substrate,
Forming an active layer on the base film;
Forming a gate insulating film on the active layer;
Forming a gate electrode on the gate insulating film;
Impurity ions are added to the active layer to form a source region and a drain region in the active layer,
Forming a first interlayer insulating film on the active layer, the gate insulating film and the gate electrode;
Forming a source electrode connected to the source region on the first interlayer insulating film;
By forming a drain electrode connected to the drain region on the first interlayer insulating film,
Forming a plurality of pixel TFTs in a matrix;
Forming a planarization film on the plurality of pixel TFTs;
Forming a first transparent conductive film on the planarizing film and forming a first opening in the first transparent conductive film;
Forming a capacitor insulating film so as to cover the first transparent conductive film, removing a part of the capacitor insulating film, and forming a second opening inside the first opening;
Removing a part of the planarization film using the capacitor insulating film as a mask to form a drop portion reaching the drain electrode;
Forming a second interlayer insulating film covering the second opening and the drop portion;
Removing the second interlayer insulating film in a region where a storage capacitor is to be formed, and patterning over each of the plurality of pixel TFTs;
Forming a contact hole reaching the drain electrode in the patterned second interlayer insulating film in the drop portion;
Forming a second transparent conductive film connected to the drain electrode through the contact hole on the capacitor insulating film;
Have
A method for manufacturing a semiconductor device, wherein the storage capacitor is formed in a structure in which the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film are stacked. In claim 7 or claim 8 ,
The planarization layer is a method for manufacturing a semiconductor device characterized by comprising a resin material. In any one of Claims 7 to 9,
The method for manufacturing a semiconductor device, wherein the second interlayer insulating film is made of a resin material. In any one of Claims 7 to 9 ,
The second interlayer insulating film, a method for manufacturing a semiconductor device characterized by a layered structure of the resin material and a transparent resin material having a resin material or a light-shielding property having a light shielding property.

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