JP2001056485A5 - - Google Patents
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- JP2001056485A5 JP2001056485A5 JP1999207354A JP20735499A JP2001056485A5 JP 2001056485 A5 JP2001056485 A5 JP 2001056485A5 JP 1999207354 A JP1999207354 A JP 1999207354A JP 20735499 A JP20735499 A JP 20735499A JP 2001056485 A5 JP2001056485 A5 JP 2001056485A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- transparent conductive
- conductive film
- interlayer insulating
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000011229 interlayer Substances 0.000 claims 14
- 239000003990 capacitor Substances 0.000 claims 13
- 239000000463 material Substances 0.000 claims 8
- 239000011347 resin Substances 0.000 claims 8
- 229920005989 resin Polymers 0.000 claims 8
- 239000004065 semiconductor Substances 0.000 claims 7
- 238000004519 manufacturing process Methods 0.000 claims 3
- 239000011159 matrix material Substances 0.000 claims 3
- 238000000059 patterning Methods 0.000 claims 2
Claims (7)
前記複数の画素ＴＦＴの各々に接続された保持容量と、
前記複数のＴＦＴ上に形成された第１の層間絶縁膜と、
前記第１の層間絶縁膜上に形成され、第１開口部を有する第１透明導電膜と、
前記第１透明導電膜を覆い、且つ前記第１開口部よりも内側に第２開口部を形成する容量用絶縁膜と、
前記第２開口部を覆い、且つ前記複数の画素ＴＦＴの各々の上方にパターン形成された第２の層間絶縁膜と、
前記第２の層間絶縁膜及び前記容量用絶縁膜に接して形成された第２透明導電膜と、を有し、
前記保持容量は、前記第１透明導電膜、前記容量用絶縁膜及び前記第２透明導電膜を積層した構造からなることを特徴とする半導体装置。A plurality of pixel TFTs arranged in a matrix ,
A storage capacitor connected to each of the plurality of pixel TFTs ;
A first interlayer insulating film formed on the plurality of TFTs,
A first transparent conductive film formed on the first interlayer insulating film and having a first opening;
A capacitor insulating film that covers the first transparent conductive film and forms a second opening inside the first opening;
A second interlayer insulating film that covers the second opening and is patterned above each of the plurality of pixel TFTs;
A second transparent conductive film formed in contact with the second interlayer insulating film and the capacitor insulating film,
The semiconductor device according to claim 1 , wherein the storage capacitor has a structure in which the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film are stacked.
前記複数の画素ＴＦＴの各々に接続された保持容量と、
第１開口部を有する第１透明導電膜と、
前記第１透明導電膜を覆い、且つ前記第１開口部よりも内側に第２開口部を形成する容量用絶縁膜と、
前記第２開口部を覆い、且つ前記複数の画素ＴＦＴの各々の上方にパターン形成された層間絶縁膜と、
前記層間絶縁膜及び前記容量用絶縁膜に接して形成された第２透明導電膜と、
前記第１透明導電膜、前記容量用絶縁膜及び前記第２透明導電膜を積層した構造からなる前記保持容量と、
を有し、
前記第１透明導電膜は前記第２透明導電膜で形成されたパッド電極を介して接地されていることを特徴とする半導体装置。A plurality of pixel TFTs arranged in a matrix ,
A storage capacitor connected to each of the plurality of pixel TFTs ;
A first transparent conductive film having a first opening;
A capacitor insulating film that covers the first transparent conductive film and forms a second opening inside the first opening;
An interlayer insulating film that covers the second opening and is patterned above each of the plurality of pixel TFTs;
A second transparent conductive film formed in contact with the interlayer insulating film and the capacitor insulating film;
The storage capacitor having a structure in which the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film are stacked;
Has,
The semiconductor device according to claim 1, wherein the first transparent conductive film is grounded via a pad electrode formed of the second transparent conductive film.
前記層間絶縁膜は樹脂材料からなることを特徴とする半導体装置。In claim 1 or claim 2,
The semiconductor device, wherein the interlayer insulating film is made of a resin material.
前記層間絶縁膜は遮光性を有する樹脂材料若しくは遮光性を有する樹脂材料と透明樹脂材料との積層構造からなることを特徴とする半導体装置。In claim 1 or claim 2,
A semiconductor device, wherein the interlayer insulating film has a light-shielding resin material or a laminated structure of a light-shielding resin material and a transparent resin material.
前記複数の画素ＴＦＴ上に第１の層間絶縁膜を形成する工程と、
前記第１の層間絶縁膜上に第１透明導電膜を形成し、前記第１透明導電膜に第１の開口部を形成する工程と、
前記第１透明導電膜を覆うように容量用絶縁膜を形成し、前記容量用絶縁膜をパターニングして前記第１開口部よりも内側に第２開口部を形成する工程と、
前記第２開口部を覆う第２の層間絶縁膜を形成し、前記第２の層間絶縁膜をパターニングして前記複数の画素ＴＦＴのそれぞれの上方のみにパターン形成する工程と、
前記容量用絶縁膜上に、前記複数の画素ＴＦＴの各々に接続された第２透明導電膜を形成する工程と、
を有し、
前記第１透明導電膜、前記容量用絶縁膜及び前記第２透明導電膜を積層した構造で、前記複数の画素ＴＦＴの各々に接続された保持容量が形成されることを特徴とする半導体装置の作製方法。 Forming a plurality of pixel TFTs in a matrix;
Forming a first interlayer insulating film on the plurality of pixel TFTs;
A step of the first transparent conductive film is formed, to form a first opening in the first transparent conductive film on the first interlayer insulating film,
A step of the first insulating film is formed capacitance so as to cover the transparent conductive film, forming a second opening on the inner side than the first opening by patterning the capacitor insulating film,
Forming a second interlayer insulating film covering the second opening, and patterning the second interlayer insulating film to form a pattern only above each of the plurality of pixel TFTs;
Forming a second transparent conductive film connected to each of the plurality of pixel TFTs on the capacitance insulating film;
Has,
The semiconductor device according to claim 1, wherein a storage capacitor connected to each of the plurality of pixel TFTs is formed in a structure in which the first transparent conductive film, the capacitor insulating film, and the second transparent conductive film are stacked. Production method.
前記層間絶縁膜として樹脂材料を用いることを特徴とする半導体装置の作製方法。In claim 5,
A method for manufacturing a semiconductor device, wherein a resin material is used as the interlayer insulating film.
前記層間絶縁膜として遮光性を有する樹脂材料若しくは遮光性を有する樹脂材料と透明樹脂材料との積層構造を用いることを特徴とする半導体装置の作製方法。In claim 5,
A method for manufacturing a semiconductor device, wherein a resin material having a light-shielding property or a laminated structure of a resin material having a light-shielding property and a transparent resin material is used as the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20735499A JP3788707B2 (en) | 1998-08-06 | 1999-07-22 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23496198 | 1998-08-06 | ||
| JP25409798 | 1998-09-08 | ||
| JP10-234961 | 1999-06-08 | ||
| JP11-160460 | 1999-06-08 | ||
| JP10-254097 | 1999-06-08 | ||
| JP16046099 | 1999-06-08 | ||
| JP20735499A JP3788707B2 (en) | 1998-08-06 | 1999-07-22 | Semiconductor device and manufacturing method thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001056485A JP2001056485A (en) | 2001-02-27 |
| JP2001056485A5 true JP2001056485A5 (en) | 2004-11-11 |
| JP3788707B2 JP3788707B2 (en) | 2006-06-21 |
Family
ID=27473674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20735499A Expired - Fee Related JP3788707B2 (en) | 1998-08-06 | 1999-07-22 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3788707B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6614083B1 (en) | 1999-03-17 | 2003-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Wiring material and a semiconductor device having wiring using the material, and the manufacturing method |
| JP4865142B2 (en) * | 2001-04-04 | 2012-02-01 | セイコーインスツル株式会社 | Liquid crystal display element and manufacturing method thereof |
| US8305507B2 (en) | 2005-02-25 | 2012-11-06 | Samsung Display Co., Ltd. | Thin film transistor array panel having improved storage capacitance and manufacturing method thereof |
| JP2007212499A (en) * | 2006-02-07 | 2007-08-23 | Seiko Epson Corp | Liquid crystal device and projector |
| JP4818839B2 (en) * | 2006-07-19 | 2011-11-16 | 株式会社 日立ディスプレイズ | Liquid crystal display device and manufacturing method thereof |
| JP5589359B2 (en) | 2009-01-05 | 2014-09-17 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| JP5182116B2 (en) * | 2009-01-23 | 2013-04-10 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| JP5352333B2 (en) | 2009-04-23 | 2013-11-27 | 株式会社ジャパンディスプレイ | Active matrix display device |
| US8866982B2 (en) | 2009-08-20 | 2014-10-21 | Innolux Corporation | Display device |
| JP5987197B2 (en) * | 2012-03-12 | 2016-09-07 | 東京瓦斯株式会社 | Hydrogen separation membrane and hydrogen separation method |
| JP2013200574A (en) * | 2013-06-05 | 2013-10-03 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP5685633B2 (en) * | 2013-10-08 | 2015-03-18 | 株式会社半導体エネルギー研究所 | Display device |
| JP6457879B2 (en) * | 2015-04-22 | 2019-01-23 | 株式会社ジャパンディスプレイ | Display device and manufacturing method thereof |
-
1999
- 1999-07-22 JP JP20735499A patent/JP3788707B2/en not_active Expired - Fee Related
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