JP3787591B2 - Resistance circuit - Google Patents
Resistance circuit Download PDFInfo
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- JP3787591B2 JP3787591B2 JP2002036744A JP2002036744A JP3787591B2 JP 3787591 B2 JP3787591 B2 JP 3787591B2 JP 2002036744 A JP2002036744 A JP 2002036744A JP 2002036744 A JP2002036744 A JP 2002036744A JP 3787591 B2 JP3787591 B2 JP 3787591B2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000009966 trimming Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路に用いる抵抗回路、特に分圧回路部作成のためのレイアウト配置に関するものである。
【０００２】
【従来の技術】
半導体集積回路に用いる図２のような端子Aと端子Cとの電圧を分割する分圧回路部分は、図２のように基準抵抗部分Ｒｒｅｆと所望の値を調整できる数個の要素からなる抵抗部、この所望の抵抗値を決定するために用いる抵抗部数個と同数のトリミングできるヒューズで構成されている。ここで、端子AC間の電圧をV、端子ＡＢ間の電圧をＶＡＢ、端子ＡＢ間にある基準抵抗部の抵抗をＲｒｅｆ、端子BC間の電圧をＶＢＣ、端子ＢＣ間の抵抗をRBCとすると、端子AC間を分圧した電圧ＶＡＢとＶＢＣはそれぞれ次式で表される。
【０００３】
ＶＡＢ＝Ｖ・Ｒｒｅｆ／（Ｒｒｅｆ＋ＲＢＣ）
ＶＢＣ＝Ｖ・ＲＢＣ／（Ｒｒｅｆ＋ＲＢＣ）
と表される。AC端子間電圧VはＶＡＢ対ＶＢＣと分圧されるので上式よりABとBC間の電圧は、抵抗比Ｒｒｅｆ対RBCで分圧することが可能である。所望の値を要求する端子BC間の抵抗値は以下のとおりである。一般に抵抗のトリミングでは、端子BC間の抵抗値をある所望の値に合わせ込む。ここでは、トリミング素子F1〜F4が直列に接続されており、各トリミング素子と並列に抵抗R1〜R4が接続されている。ここで、トリミング素子F1,F2,F3,F4の抵抗値をそれぞれRF1,RF2,RF3,RF4とする。トリミング素子F1と抵抗R1の並列抵抗値をRF1//R１とすれば、端子BC間の抵抗値は（RF1//R１）＋（RF2//R2）＋（RF3//R3）＋（RF4//R4）で与えられる。また一般的にトリミング素子F1〜F4の抵抗値RF1〜RF4は、抵抗R1〜R4の抵抗値に比べて無視できるほど小さい。従ってトリミング素子をカットしない状態では端子BC間の抵抗値は、RF1＋RF2＋RF3＋RF4となる。ここで、トリミング素子F1をカットすると端子BC間の抵抗はR1＋RF2＋RF3+RF4となるが、R1に比較してRF2,RF3,RF4は無視できるほど小さいので端子BC間の抵抗値は、ほぼR1となる。
【０００４】
また、トリミング素子のF1とF2をカットすれば端子BC間の抵抗値はR1+R2+RF3+RF4となるが、R1＋R2に比較してRF3＋RF4は無視できるほど小さいので端子BC間の抵抗値はR1＋R2となる。従って、トリミング素子F1〜F4を任意にカットすることで端子BC間の抵抗値を所望の値に調節することが可能である。以上述べた分圧回路の作成過程におけるレイアウトパターン配置は考慮されていない。
【０００５】
【発明が解決しようとする課題】
半導体集積回路の抵抗部分は、トランジスタ、高抵抗ポリシリコン、拡散などで作られている。ここでは一例として高抵抗ポリシリコンで示す。高抵抗ポリシリコンはイオン注入によって作製し、抵抗値は抵抗素子の面積で設定することができるが、イオン注入には不均一性があり、この不均一性がチップの面内バラツキとして現れるので、面内全体に高精度で均一な抵抗値を実現することは困難である。
【０００６】
分圧回路は基準抵抗部と所望の値の抵抗部との抵抗比で決定されるが、従来のようにレイアウト配置を考慮しないで基準抵抗部と所望の値の抵抗部分がチップ内で離れて配置された場合、大きな抵抗値誤差を生む要因であった。このイオン注入の不均一性による抵抗値の面内バラツキの影響が抵抗比誤差として現れてくるので、高精度な分圧回路の実現が困難である。
【０００７】
【課題を解決するための手段】
上記の課題を解決するために、本発明は半導体集積回路に用いる分圧回路のレイアウトパターン配置において、基準抵抗部分の周囲に抵抗値の一番大きい要素から順番に並べて配置することを特徴とするものである。
【０００８】
即ち、抵抗回路は、基準抵抗部分と、抵抗素子と前記抵抗素子と並列に接続された前記抵抗素子をトリミングする為のヒューズとからなる抵抗部と、を有し、前記基準抵抗部分の周囲に、前記抵抗素子が前記基準抵抗部分に隣接するように抵抗値の大きい前記抵抗素子から順番に並べて配置されている。
【０００９】
【発明の実施の形態】
本発明の分圧回路に用いる抵抗素子のレイアウトパターン配置は、基準抵抗の周囲に抵抗値の大きい要素から並べて配置したものである。
【００１０】
【実施例】
以下、本発明の実施の形態について図面を参照して詳細に説明する。図１(a)は本発明第１の実施例の抵抗素子のレイアウトパターン配置である。基準抵抗の左右に、所望の値を調整できる数個の要素から成る抵抗部分のうち値の一番大きい要素から順番で並べて配置する。図１(a)〜(f)においてＲｒｅｆは基準抵抗部、R1、R2、R3、R4は図２における回路図の端子BC間の抵抗要素である。端子BC間の抵抗要素の大小関係はR1≦R2≦R3≦R4である。
【００１１】
図２の回路図に対応した抵抗素子の実際のレイアウトパターンを図３に示す。ここでは一例として高抵抗ポリシリコンで示している。図３において高抵抗ポリシリコン１は金属配線２で配線しており、コンタクト３で高抵抗ポリシリコンと金属配線を接続している。
【００１２】
高抵抗ポリシリコンの長さＬ及び高抵抗ポリシリコンの幅Ｗで決められる面積によって抵抗素子の抵抗値は設定される。設定された任意の抵抗値Rを持った図３（ａ）のような１本の高抵抗ポリシリコン抵抗素子を、例えば、金属配線で任意の本数を直列または並列に接続して所望の抵抗値を作ることができる。例えば、図３（ｂ）は任意の抵抗Rを直列に２本つないでおり抵抗値R2となる。図３（ｃ）は直列に４本つないでおり抵抗値R4となる。また、図３（ｄ）は任意の抵抗Rを並列につないでおり抵抗値R/２となる。図３（ｄ）は並列に４本つないでおり抵抗値はR/４となる。ここで、金属配線の抵抗値は高抵抗ポリシリコンの抵抗値に比べて無視できるほど小さい。
【００１３】
このように作られた各抵抗要素に並列にトリミング素子が金属配線で接続されており、分圧回路が図２の回路図ように構成されている。
図１（ｂ）、（ｃ）は、本発明第２の実施例で、抵抗素子のレイアウトパターン配置である。
基準抵抗部分の周囲に抵抗値の一番大きい要素から上下左右及び左右上下順番に並べて配置することを特徴とする。
【００１４】
図１（d）は本発明第３の実施例で、抵抗素子のレイアウトパターン配置である。基準抵抗部分の周囲に所望の値を調整できる数個の異なる値を持つ要素からなる抵抗部を均等に分割したものを抵抗値の一番大きい要素から上下左右順番に並べて配置することを特徴とする。
【００１５】
例えば、各抵抗値を４・Ｒｒｅｆ＝４・Ｒ１＝２・Ｒ２＝４／３・Ｒ３＝Ｒ４とする。さらにレイアウトパターン配置においてＲｒｅｆとR1を図３（ａ）、又は図３（ｄ）を２つ直列に接続したものと考えると、Ｒ２は図３（ｂ）、R3は図３(a)と図３(b)の直列接続、R4は図３(c)にそれぞれ対応している。また、図３(a)のような基準としてある高抵抗ポリシリコン１本を金属配線で接続し図３(b)〜(e)のように希望の抵抗を作っているので、図３（ｂ）〜（ｅ）は高抵抗ポリシリコンが離れたところに分割配置されていても金属配線で接続することで希望の抵抗を作ることが可能である。
【００１６】
図１（ｅ），（ｆ）は本発明第４の実施例で、抵抗素子のレイアウトパターン配置である。基準抵抗部分の周囲に所望の値を調整できる数個の異なる値を持つ要素からなる抵抗部を均等に分割したものを抵抗値の一番大きい要素から上下左右及び左右上下順番に並べて配置することを特徴とする。
【００１７】
【発明の効果】
本発明は、以上説明したように構成されているので、以下に記載されるような効果がある。基準抵抗と基準抵抗からの比で決定される所望の抵抗値との比が精度良く作ることができる。これにより、不良発生率が減少されコスト削減につながる。
【図面の簡単な説明】
【図１】本発明の分圧回路における抵抗部全体のレイアウトパターン配置図である。
【図２】図１に示したレイアウトパターン配置に対する分圧回路全体の回路図である。
【図３】図１に示した抵抗部分の実際のレイアウトパターン図の例である。
【符号の説明】
１ 高抵抗ポリシリコン
２ 金属配線
３ コンタクト
L 高抵抗ポリシリコンの長さ
Ｗ 高抵抗ポリシリコンの幅[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a resistor circuit used in a semiconductor integrated circuit, and more particularly to a layout arrangement for creating a voltage dividing circuit section.
[0002]
[Prior art]
The voltage dividing circuit portion for dividing the voltage between the terminal A and the terminal C as shown in FIG. 2 used in the semiconductor integrated circuit is a resistance composed of a reference resistance portion Rref and several elements capable of adjusting a desired value as shown in FIG. And the same number of fuses that can be trimmed as the number of resistors used to determine the desired resistance value. Here, when the voltage between the terminals AC is V, the voltage between the terminals AB is VAB, the resistance of the reference resistance portion between the terminals AB is Rref, the voltage between the terminals BC is VBC, and the resistance between the terminals BC is RBC, Voltages VAB and VBC obtained by dividing the voltage between terminals AC are represented by the following equations, respectively.
[0003]
VAB = V · Rref / (Rref + RBC)
VBC = V · RBC / (Rref + RBC)
It is expressed. Since the voltage V between the AC terminals is divided between VAB and VBC, the voltage between AB and BC can be divided by the resistance ratio Rref vs. RBC from the above equation. The resistance value between the terminals BC that requires a desired value is as follows. In general, in resistance trimming, the resistance value between the terminals BC is adjusted to a desired value. Here, trimming elements F1 to F4 are connected in series, and resistors R1 to R4 are connected in parallel with the respective trimming elements. Here, the resistance values of the trimming elements F1, F2, F3, and F4 are RF1, RF2, RF3, and RF4, respectively. If the parallel resistance value of the trimming element F1 and the resistor R1 is RF1 // R1, the resistance value between the terminals BC is (RF1 // R1) + (RF2 // R2) + (RF3 // R3) + (RF4 / / R4). In general, the resistance values RF1 to RF4 of the trimming elements F1 to F4 are negligibly smaller than the resistance values of the resistors R1 to R4. Therefore, when the trimming element is not cut, the resistance value between the terminals BC is RF1 + RF2 + RF3 + RF4. Here, when the trimming element F1 is cut, the resistance between the terminals BC becomes R1 + RF2 + RF3 + RF4. However, since RF2, RF3, and RF4 are negligibly small compared to R1, the resistance value between the terminals BC is almost R1. .
[0004]
If the trimming elements F1 and F2 are cut, the resistance value between the terminals BC becomes R1 + R2 + RF3 + RF4, but the resistance value between the terminals BC is R1 + R2 because RF3 + RF4 is negligibly small compared to R1 + R2. It becomes. Therefore, the resistance value between the terminals BC can be adjusted to a desired value by arbitrarily cutting the trimming elements F1 to F4. The layout pattern arrangement in the process of creating the voltage dividing circuit described above is not taken into consideration.
[0005]
[Problems to be solved by the invention]
The resistance portion of the semiconductor integrated circuit is made of a transistor, high resistance polysilicon, diffusion, or the like. Here, high resistance polysilicon is shown as an example. High resistance polysilicon is produced by ion implantation, and the resistance value can be set by the area of the resistance element, but ion implantation has non-uniformity, and this non-uniformity appears as in-plane variation of the chip. It is difficult to realize a highly accurate and uniform resistance value over the entire surface.
[0006]
The voltage divider circuit is determined by the resistance ratio between the reference resistor portion and the resistor portion having a desired value, but the reference resistor portion and the resistor portion having the desired value are separated from each other in the chip without considering the layout arrangement as in the prior art. When arranged, it was a factor causing a large resistance value error. Since the influence of the in-plane variation of the resistance value due to the non-uniformity of ion implantation appears as a resistance ratio error, it is difficult to realize a highly accurate voltage dividing circuit.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention is characterized in that, in a layout pattern arrangement of a voltage dividing circuit used in a semiconductor integrated circuit, elements are arranged in order from the element having the largest resistance value around the reference resistance portion. Is.
[0008]
That is, the resistance circuit includes a reference resistance portion, and a resistance portion including a resistance element and a fuse for trimming the resistance element connected in parallel with the resistance element, around the reference resistance portion. The resistor elements are arranged in order from the resistor element having a large resistance value so that the resistor element is adjacent to the reference resistor portion.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The layout pattern arrangement of the resistance elements used in the voltage dividing circuit of the present invention is arranged by arranging elements having a large resistance value around the reference resistance.
[0010]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1A shows the layout pattern arrangement of the resistance element according to the first embodiment of the present invention. On the left and right sides of the reference resistance, elements having the largest value among the resistance parts composed of several elements whose desired values can be adjusted are arranged in order. In FIGS. 1A to 1F, Rref is a reference resistance unit, and R1, R2, R3, and R4 are resistance elements between terminals BC in the circuit diagram of FIG. The magnitude relationship of the resistance elements between the terminals BC is R1 ≦ R2 ≦ R3 ≦ R4.
[0011]
FIG. 3 shows an actual layout pattern of resistance elements corresponding to the circuit diagram of FIG. Here, high resistance polysilicon is shown as an example. In FIG. 3, the high resistance polysilicon 1 is wired by the
[0012]
The resistance value of the resistance element is set by the area determined by the length L of the high resistance polysilicon and the width W of the high resistance polysilicon. A desired resistance value is obtained by connecting one high resistance polysilicon resistance element having an arbitrary resistance value R as shown in FIG. 3A in series or in parallel with a metal wiring, for example. Can be made. For example, in FIG. 3 (b), two arbitrary resistors R are connected in series, resulting in a resistance value R2. In FIG. 3C, four resistors are connected in series, resulting in a resistance value R4. Further, in FIG. 3D, an arbitrary resistance R is connected in parallel, and the resistance value becomes R / 2. In FIG. 3D, four resistors are connected in parallel, and the resistance value is R / 4. Here, the resistance value of the metal wiring is negligibly small compared to the resistance value of the high resistance polysilicon.
[0013]
Trimming elements are connected by metal wiring in parallel to the resistance elements made in this way, and the voltage dividing circuit is configured as shown in the circuit diagram of FIG.
FIGS. 1B and 1C show a layout pattern arrangement of resistance elements according to the second embodiment of the present invention.
Around the reference resistance portion, the elements having the largest resistance value are arranged in order from top to bottom, left and right, and left and right and up and down.
[0014]
FIG. 1D shows a layout pattern arrangement of resistance elements according to the third embodiment of the present invention. Around the reference resistance portion, the resistance portion composed of several elements having different values capable of adjusting a desired value is arranged in equal order from the element with the largest resistance value in the vertical and horizontal order. To do.
[0015]
For example, each resistance value is set to 4 · Rref = 4 · R1 = 2 · R2 = 4/3 · R3 = R4. Further, assuming that Rref and R1 are connected in series in FIG. 3 (a) or FIG. 3 (d) in the layout pattern arrangement, R2 is shown in FIG. 3 (b), and R3 is shown in FIG. 3 (a). The series connection 3 (b), R4, corresponds to FIG. 3 (c). Further, since one high resistance polysilicon as a reference as shown in FIG. 3 (a) is connected by metal wiring to produce a desired resistance as shown in FIGS. 3 (b) to 3 (e), FIG. In (e) to (e), even if the high-resistance polysilicon is divided and arranged at a distance, it is possible to make a desired resistance by connecting with metal wiring.
[0016]
FIGS. 1E and 1F show a layout pattern arrangement of resistance elements according to a fourth embodiment of the present invention. Around the reference resistance part, the resistance part consisting of several elements with different values that can adjust the desired value is divided equally and arranged in the order of the top and bottom and left and right and up and down from the element with the largest resistance value. It is characterized by.
[0017]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained. The ratio between the reference resistance and the desired resistance value determined by the ratio from the reference resistance can be made with high accuracy. This reduces the defect occurrence rate and leads to cost reduction.
[Brief description of the drawings]
FIG. 1 is a layout pattern layout diagram of an entire resistor section in a voltage dividing circuit according to the present invention.
2 is a circuit diagram of an entire voltage dividing circuit with respect to the layout pattern arrangement shown in FIG. 1. FIG.
FIG. 3 is an example of an actual layout pattern diagram of the resistance portion shown in FIG. 1;
[Explanation of symbols]
1
L Length of high resistance polysilicon W Width of high resistance polysilicon
Claims (4)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002036744A JP3787591B2 (en) | 2002-02-14 | 2002-02-14 | Resistance circuit |
| US10/267,364 US6725436B2 (en) | 2002-02-14 | 2002-10-09 | Resistor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002036744A JP3787591B2 (en) | 2002-02-14 | 2002-02-14 | Resistance circuit |
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| Publication Number | Publication Date |
|---|---|
| JP2003243513A JP2003243513A (en) | 2003-08-29 |
| JP3787591B2 true JP3787591B2 (en) | 2006-06-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002036744A Expired - Lifetime JP3787591B2 (en) | 2002-02-14 | 2002-02-14 | Resistance circuit |
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|---|---|
| US (1) | US6725436B2 (en) |
| JP (1) | JP3787591B2 (en) |
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|---|---|---|---|---|
| WO2014041950A1 (en) | 2012-09-14 | 2014-03-20 | セイコーインスツル株式会社 | Voltage divider circuit |
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| JP3887260B2 (en) * | 2002-04-09 | 2007-02-28 | 沖電気工業株式会社 | Dividing resistor layout method |
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| JP4841220B2 (en) | 2005-10-14 | 2011-12-21 | 株式会社リコー | Semiconductor device |
| US7721119B2 (en) * | 2006-08-24 | 2010-05-18 | International Business Machines Corporation | System and method to optimize multi-core microprocessor performance using voltage offsets |
| WO2009014765A1 (en) * | 2007-07-26 | 2009-01-29 | Fultec Semiconductor, Inc. | Transient blocking unit having a fab-adjustable threshold current |
| JP5433957B2 (en) * | 2008-02-26 | 2014-03-05 | 株式会社リコー | Semiconductor device |
| JP2010093637A (en) * | 2008-10-09 | 2010-04-22 | Nec Electronics Corp | Delay circuit |
| US8143993B2 (en) * | 2009-07-29 | 2012-03-27 | Fairchild Semiconductor Corporation | Method and circuit for recycling trimmed devices |
| KR101730784B1 (en) | 2010-11-29 | 2017-04-26 | 르네사스 일렉트로닉스 가부시키가이샤 | Semiconductor device |
| GB201207490D0 (en) * | 2012-04-30 | 2012-06-13 | Emblation Ltd | Apparatus and method for determining a status of a medical device component |
| JP6073705B2 (en) * | 2013-02-26 | 2017-02-01 | エスアイアイ・セミコンダクタ株式会社 | Fuse circuit and semiconductor integrated circuit device |
| WO2019132879A1 (en) * | 2017-12-27 | 2019-07-04 | Intel Corporation | Compensation of resistance in thin film resistor |
| JP2022094379A (en) * | 2020-12-15 | 2022-06-27 | エイブリック株式会社 | Resistance circuit and current detection circuit including resistance circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5239162A (en) * | 1975-09-23 | 1977-03-26 | Jiyuichirou Ozawa | Fuse resistor |
| JPS5831426A (en) * | 1981-08-19 | 1983-02-24 | Matsushita Electric Ind Co Ltd | Power supply unit |
| US4401963A (en) * | 1981-12-14 | 1983-08-30 | Warco, Inc. | Resistor insertion fuse |
| US6532568B1 (en) * | 2000-10-30 | 2003-03-11 | Delphi Technologies, Inc. | Apparatus and method for conditioning polysilicon circuit elements |
-
2002
- 2002-02-14 JP JP2002036744A patent/JP3787591B2/en not_active Expired - Lifetime
- 2002-10-09 US US10/267,364 patent/US6725436B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014041950A1 (en) | 2012-09-14 | 2014-03-20 | セイコーインスツル株式会社 | Voltage divider circuit |
| KR20150054820A (en) | 2012-09-14 | 2015-05-20 | 세이코 인스트루 가부시키가이샤 | Voltage divider circuit |
| US9806605B2 (en) | 2012-09-14 | 2017-10-31 | STI Semiconductor Corporation | Voltage divider circuit having at least two kinds of unit resistors |
Also Published As
| Publication number | Publication date |
|---|---|
| US20030154456A1 (en) | 2003-08-14 |
| US6725436B2 (en) | 2004-04-20 |
| JP2003243513A (en) | 2003-08-29 |
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