WO2019132879A1

WO2019132879A1 - Compensation of resistance in thin film resistor

Info

Publication number: WO2019132879A1
Application number: PCT/US2017/068540
Authority: WO
Inventors: Nicholas J. MCKUBRE; Kevin Lin
Original assignee: Intel Corporation
Priority date: 2017-12-27
Filing date: 2017-12-27
Publication date: 2019-07-04

Abstract

An apparatus is provided which includes: a first line and a second line, the first line and the second line separated by a space therebetween. In an example, a dielectric material and a third line is in the space between the first and second lines. A top surface of the third line may be coplanar with top surfaces of the first and second lines. The apparatus may further include a substrate. The first and second lines may be on the substrate, and the third line may be over a thickness of the dielectric material on the substrate. An interconnect structure may be over the dielectric material, where the interconnect structure may be in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

Description

COMPENSATION OF RESISTANCE IN THIN FILM RESISTOR

BACKGROUND

[0001] Integrated circuit chips often include passive components, such as capacitors, resistors, inductors, etc. A resistor, e.g., a thin film resistor (TFR), may be formed by deposition of one or more conductive lines. In a conventional TFR, unintentional variation of widths of the conductive lines can correspondingly vary a resistance of the TFR from an intended resistance value. Such undesirable variation of the resistance may be reduced, for example, by laser etching individual conductive lines (e.g., to match the widths to the intended widths), which may be time consuming and/or costly.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Figs. 1A and IB illustrate a device comprising a thin film resistor, in which widths of one or more compensation conductive lines of the device are compensated for possible variation in widths of one or more backbone conductive lines (e.g., to reduce variation in resistance of the device due to variation in widths of the backbone conductive lines), according to some embodiments.

[0004] Fig. 1C illustrates a compensation conductive line providing compensation for variation of widths of adjacent backbone conductive lines in the device of Figs. 1A-1B,

according to some embodiments.

[0005] Fig. ID illustrates a graph depicting comparison of a resistor in the device of

Figs. 1A-1B having compensation for possible variation of conductive lines and a resistor that does not provide any such compensation, according to some embodiments.

[0006] Fig. IE illustrates the device of Figs. 1A-1B, where one or more antifuses may be used to short one or more corresponding sections of a resistor of the device, according to some embodiments. [0007] Fig. IF illustrates a device in which interconnect structures are arranged to form a capacitor, according to some embodiments.

[0008] Figs. 2A, 2B, 2C, 2D, 2E, and 2F illustrate an example process for forming the device of Figs. 1A-1B, according to some embodiments.

[0009] Figs. 3A and 3B illustrate a device comprising a thin film resistor, in which widths of one or more conductive lines of the device are compensated for possible variation in widths of another one or more conductive lines, according to some embodiments.

[0010] Fig. 3C illustrates a magnified cross-sectional view of the device of Figs. 3A-3B, in which sidewalls of compensation conductive lines may be slanted (e.g., at an angle that is not perpendicular) with respect to a substrate, according to some embodiments.

[0011] Figs. 4A, 4B, 4C, 4D, 4E, 4F, and 4G illustrate an example process for forming the device of Figs. 3A-3C, according to some embodiments.

[0012] Fig. 5 is a flow diagram illustrating a method of forming a resistor, in which widths of one or more conductive lines of the device are compensated for possible variation in widths of another one or more conductive lines, according to some embodiments.

[0013] Fig. 6 illustrates a computing device or a SoC (System-on-Chip) comprising a device including a thin film resistor, in which widths of one or more compensation conductive lines of the device are compensated for possible variation in widths of one or more backbone conductive lines (e.g., to reduce variation in resistance of the device due to variation in widths of the backbone conductive lines), according to some embodiments.

DETAILED DESCRIPTION

[0014] Various embodiments of this disclosure disclose a thin film resistor (TFR), in which the resistance of the TFR is auto compensated against possible variation of widths of conductive lines. In some embodiments, the TFR comprises one or more backbone conductive lines. Subsequent to forming the backbone conductive lines, one or more compensation conductive lines are formed.

[0015] In some embodiments, widths of the compensation conductive lines are at least in part complementary to the widths of the backbone conductive lines. For example, while forming the backbone conductive lines, it may be possible that the width of a backbone conductive line deviate from an intended width. In such a case, widths of adjacent compensation conductive lines may be compensated in a complementary manner. For example, if the backbone conductive line is wider than intended, one or more adjacent compensation conductive lines may be correspondingly narrower. Such compensation may be achieved by, for example conformal deposition of dielectric material between two adjacent backbone conductive lines, and forming a compensation conductive line within the dielectric material. As discussed in further details herein, such conformal deposition of the dielectric material may ensure the complementary nature of the compensation conductive lines with respect to the backbone conductive lines.

[0016] Thus, the TFR autocorrects for any deviation of widths of the backbone conductive line by deviating widths of the compensation conductive line in a complementary manner. This may ensure that the net resistance of the TFR is near to or about equal to the intended resistance, in spite of the width variations. Other technical effects will be evident from the various embodiments and figures.

[0017] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0018] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit.

Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0019] Throughout the specification, and in the claims, the term“connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term“coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term“circuit” or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term“signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of“a,”“an,” and“the” include plural references. The meaning of“in” includes“in” and“on.” The terms“substantially,”“close,”“approximately,”“near,” and “about,” generally refer to being within +/- 10% of a target value.

[0020] Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and

“third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0021] For the purposes of the present disclosure, phrases“A and/or B” and“A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms“left,” “right,”“front,”“back,”“top,”“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0022] Figs. 1A and IB illustrate a device 100 comprising a thin film resistor, in which widths of one or more compensation conductive lines 1 l6a, 1 l6b, 1 l6c, and 1 l6d of the device 100 are compensated for possible variation in widths of one or more backbone conductive lines l08a, l08b, and l08c (e.g., to reduce variation in resistance of the device due to variation in widths of the backbone conductive lines), according to some embodiments. Fig. IB illustrates a plan view or top view of the device 100 (e.g., illustrates a top view in the X and Y axis), e.g., along a line BB’ of a cross-sectional view of Fig. 1A. Fig. 1A illustrates the cross-sectional view of the device 100 (e.g., illustrates a cross sectional view in the X and Z axis), e.g., along a lone AA’ of the plan view of Fig. IB. It is to be noted that in the plan view of Fig. IB, sections of dielectric material 112 (e.g., those deposited over conductive lines 116, 108) are not illustrated for purposes of illustrative clarity.

[0023] Referring to Figs. 1A and IB, in some embodiments, the device 100 has a plurality of backbone conductive lines l08a, l08b, and l08c. The conductive lines l08a, l08b, and l08c are also referred to herein as backbone conductive lines, or as backbone lines (e.g., for reasons discussed herein later). In some embodiments, the device 100 has a plurality of conductive lines 116a, 116b, 116c, and H6d. The conductive lines 116a, 116b, 116c, and H6d are also referred to herein as compensation conductive lines, or as compensation lines (e.g., for reasons discussed herein later). Although three backbone conductive lines l08a, l08b, and l08c and four compensation conductive lines 1 l6a, 1 l6b, 1 l6c, and 1 l6d are illustrated in Figs. 1A- 1B, the device 100 may include any different number of backbone conductive lines and/or compensation conductive lines.

[0024] Elements referred to herein with a common reference label followed by a particular number or alphabet may be collectively referred to by the reference label alone. For example, conductive lines l08a, l08b, and l08c may be collectively and generally referred to as conductive lines (or backbone lines) 108 in plural, and conductive line (or backbone line) 108 in singular. Similarly, conductive lines 1 l6a, 1 l6b, 1 l6c, and 1 l6d may be collectively and generally referred to as conductive lines (or compensation lines) 116 in plural, and conductive line (or compensation line) 116 in singular.

[0025] In some embodiments, the conductive lines 108 include conductive material such as, but not limited to, one or more of platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), copper (Cu), and/or the like. In some embodiments, the conductive lines 116 includes conductive material such as, but not limited to, one or more of platinum (Pt), aluminum- copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), copper (Cu), and/or the like.

[0026] In some embodiments, the conductive lines 108 and the conductive lines 116 comprise same conductive material. In some other embodiments, the conductive material of the conductive lines 108 and the conductive material of the conductive lines 116 may be different. For example, as discussed herein later in further details, the conductive lines 108 and the conductive lines 116 may be deposited in two different processes and at two different times, and hence, it may be possible to have different types of conductive materials for the conductive lines 108 and the conductive lines 116.

[0027] For example, a variation of resistance with temperature (also referred to as temperature coefficient of resistance) for first conductive material of the conductive lines 116 can be different from a variation of resistance with temperature for second conductive material of the conductive lines 108. Such different variations of resistance with temperature for the conductive materials of the conductive lines 108 and 116 may provide resistance compensation for variation of temperature in the device 100.

[0028] In one example, one of the conductive lines 116 or 108 may have a positive temperature coefficient of resistance, and another of the conductive lines 116 or 108 may have a negative temperature coefficient of resistance. In another example, one of the conductive lines 116 or 108 may have a positive and relatively high temperature coefficient of resistance, and another of the conductive lines 116 or 108 may have a positive and relatively low value (or about zero) temperature coefficient of resistance. Thus, while the resistance of one of the conductive lines 116 or 108 may increase with a change in temperature, the resistance of another of the conductive lines 116 or 108 may have an opposite effect (or may increase, but at a lower rate) with the change in temperature, thereby providing some degree of temperature compensation of resistance for the overall structure comprising the combination of conductive lines 116 and 108.

[0029] In some embodiments, it may be desired that two conductive lines in the device 100 having similar widths provide similar resistance. However, as illustrated in Fig. 1A, heights of the conductive lines 116 is lower than heights of the conductive lines 108.

Accordingly, in some embodiments, a resistivity for conductive material of the conductive lines 116 is different from a resistivity for conductive material of the conductive lines 108. This may, for example, result in two conductive lines in the device 100 with similar widths providing similar resistance. For example, the resistivity for the conductive material of the conductive lines 116 is lower than the resistivity for conductive material of the conductive lines 108 (e.g., among other things, to compensate for a lower height of the conductive lines 116 compared to the conductive lines 108).

[0030] In an example, the conductive lines 116 and 108 may be interleaved (e.g., along the X axis). For example, a conductive line 108 may separate two adjacent conductive lines 116 along the X axis. For example, the conductive line l08a may be in between conductive lines 1 l6a and 1 l6b; the conductive line l08b may be in between conductive lines 1 l6b and 1 l6c; and so on.

[0031] The device 100 comprises a substrate 104. In some embodiments, the substrate

104 includes one or more Interlayer Dielectric (ILD) layers. In some embodiments, the substrate 100 includes a variety of materials, such as, but not limited to, silicon (Si), silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), gallium nitride (GaN), silicon carbide (SiC), sapphire, any appropriate dielectric material, a low-k dielectric (e.g., having a dielectric constant below 3.5), and/or the like.

[0032] In an example, bottom surfaces of the conductive lines 108 and 116 may be nearest to the substrate 104. Top surfaces of the conductive lines 108 and 116 may be opposite to the bottom surfaces. In some embodiments, the top surfaces of the conductive lines 108 and 116 are coplanar.

[0033] In some embodiments, dielectric material 112 at least in part encapsulates the conductive lines 108 and 116, as illustrated in Figs. 1A-1B. In some embodiments, the dielectric material 112 comprises insulating or dielectric material, such as, but not limited to, one or more of nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (W03), aluminum oxide (A1203), tantalum oxide (TaO), molybdenum oxide (MoO), copper oxide (CuO), silicon dioxide, silicon nitride (Si3 N4), polymide, and/or the like.

[0034] The conductive lines 108 (e.g., bottom surfaces of the conductive lines 108) may be formed over the substrate 104. In some embodiments, the conductive lines 108 (e.g., bottom surfaces of the conductive lines 108) are formed on the substrate 104. In some embodiments, no intervening dielectric material 112 is present between the bottom surfaces of the conductive lines 108 and the substrate 104.

[0035] In some embodiments, at least a part of the dielectric material 112 may separate the conductive lines 116 (e.g., bottom surfaces of the conductive lines 116) from the substrate 104, e.g., as illustrated in Fig. 1A. In some embodiments, a thickness of the dielectric material 112 in between the bottom surfaces of the conductive lines 116 and the substrate 104 is about cl (e.g., within ±5% of cl), e.g., as illustrated in Fig. 1A. In an example, the thickness of the dielectric material 112 in between the bottom surfaces of individual ones of the conductive lines 1 l6a, 1 l6b, 1 l6c, and/or 1 l6d may be substantially uniform at about cl (e.g., within ±5% of cl).

[0036] In some embodiments, the device 100 includes interconnect structures l20a, l20b, l20c, l22a, l22b, and l22c (it is to be noted that only the interconnect structures l20a, l20b, l20c are visible in the cross-sectional view of Fig. 1A). In some embodiments, an interconnect structure 120 or 122 couples (e.g., interconnects) two corresponding lines of the conductive lines 116 and/or 108. For example, the interconnect structure l20a interconnects the conductive line 1 l6a and a first end of the conductive line l08a; the interconnect structure l22a interconnects a second end of the conductive line l08a and a first end of the conductive line 1 l6b; the interconnect structure l20b interconnects a second end of the conductive line 1 l6b and a first end of the conductive line l08b; the interconnect structure l22b interconnects a second end of the conductive line l08b and a first end of the conductive line 1 l6c, and so on.

[0037] Thus, in the embodiment of Figs. 1A-1B, the interconnect structures 120, 122 and the conductive lines 108, 116 form a serpentine structure of conductive materials, where these components are connected in series. In some embodiments, the serpentine structure of conductive material of the conductive lines 108, 116 and the interconnect structures 120, 122 results in a formation of a resistor (e.g., a thin film resistor) in the device 100. Merely as an example, the conductive lines 1 l6a and 1 l6d may form two terminals of the resistor.

[0038] As illustrated in Fig. IB, a width of the conductive lines l08a, l08b, l08c, 1 l6a,

1 l6b, 1 l6c, and 1 l6d are respectively equal to al, a2, a3, bl, b2, b3, and b4. In some embodiments, the widths al, a2, and a3 may be substantially equal; while in some other embodiments, the widths al, a2, and a3 may be unequal.

[0039] In some embodiments, a width of the dielectric material 112 between two nearest sidewalls of two respectively adjacent conductive lines is equal to about cl (e.g., within ±5% of cl). For example, a width of the dielectric material 112 between a sidewall of the conductive line l08a and a sidewall of the conductive line 1 l6b is about cl; a width of the dielectric material 112 between another sidewall of the conductive line 1 l6b and a sidewall of the conductive line l08b is about cl; a width of the dielectric material 112 between another sidewall of the conductive line l08b and a sidewall of the conductive line 1 l6c is about cl, and so on, as illustrated in Fig. IB

[0040] In some embodiments, while forming the device 100 (and as explained in further details herein later), the backbone conductive lines 108 are initially formed on the substrate 104. Subsequently, the dielectric material 112 is conformally deposited over the backbone conductive lines 108, and the conformal deposition results in the width of the dielectric material 112 uniformly being about cl.

[0041] For example, the conductive line l08a and the conductive line l08b are separated by a space having a width of Sl; and the conductive line l08b and the conductive line l08c are separated by a space having a width of S2. In some embodiments, after the conformal deposition of the dielectric material 112 having the width of cl (and after possible selective etching of the dielectric material 112), a width of a remainder of the space between the conductive lines l08a and l08b is b2, and a width of a remainder of the space between the conductive lines l08b and l08c is b3. The compensation conductive lines 116b and 1 l6c are formed in the remainder of the spaces with widths b2 and b3, respectively.

[0042] Thus, for example, the conductive lines l08a and l08b are separated by the space having the width of Sl. The conductive line 116b is formed within a part of this space, where the width b2 of the conductive line 1 l6b is equal to the space Sl minus twice the width cl of the dielectric material 112.

[0043] In some embodiments, the compensation conductive lines 116 provide compensation for any variation of the widths of the backbone conductive lines 108. For example, as discussed herein, the device 100 may be used as a resistor. Assume that for a certain desired resistance value for the resistor, it may be desirable to have the width of the conductive line l08b to be a2’ (e.g., it may be calculated that the width of the conductive line l08b is to be a2’ for the aimed resistance value). However, during deposition, the actual width of the conductive line l08b is, for example, a2, where a2 is less than a2\ Without any compensation, this may tend to increase the resistance of the resistor. However, the conductive lines 1 l6b and 1 l6c adjacent to the conductive line l08b may provide compensation for the less than desired width of the conductive line l08b. For example, as the width a2 of the conductive line l08b is less than the intended width a2’, the space Sl and/or S2 may correspondingly increase. Also, increase in the space Sl and/or S2 may result in increase in the widths of the conductive lines 1 l6b and/or 1 l6c (e.g., as the width of the dielectric material 112 is uniform at cl). Thus, any decrease (or increase) in the width of the backbone conductive line l08b may result in a corresponding increase (or decrease) in the adjacent compensation conductive lines 1 l6b and/or 1 l6c. In some embodiments, the compensation provided by the compensation conductive lines 116 results in the overall resistance of the resistor being close to the intended resistance of the resistor. Thus, the width of the compensation conductive lines 116 can compensate for variations in the width of the backbone conductive lines 108.

[0044] Put differently, when a backbone conductive line 108 is wider (or narrower) than intended, adjacent one or both compensation conductive lines 116 are correspondingly narrower (or wider). Because the compensation conductive lines 116 and the backbone conductive lines 108 are connected in series, the reduced (or increased) resistance due to a wider (or narrower) than intended backbone conductive line is compensated by the complementary narrower, higher resistance (or wider, lower resistance) adjacent compensation conductive lines.

[0045] Fig. 1C illustrates a compensation conductive line 116 providing compensation for variation of widths of adjacent backbone conductive lines 116 in the device 100 of Figs. 1A- 1B, according to some embodiments. Fig. 1C illustrates a magnified plan view of the conductive lines l08a, l08b, and H6b of the device 100.

[0046] Also illustrated are the interconnects l22b and l20b, although these interconnects are illustrated using transparent blocks (e.g., instead of the shaded blocks of Figs. 1A-1B), e.g., for purposes of illustrative clarity. Similarly, the dielectric material 112 is illustrated using transparent blocks (e.g., instead of the shaded blocks of Figs. 1A-1B), e.g., for purposes of illustrative clarity.

[0047] In some embodiments, width of a backbone conductive line 108 may vary over the length of the conductive line. Fig. 1C illustrates such example variations in the conductive lines l08a and l08b. In an example, the variations in the width of a conductive line 108 over a length of the conductive line 108 may be a result of incidental line edge roughness (LER) associated with formation of the conductive line 108. In an example, such variations may be a result of deliberate modulation of patterning polygons, for example, according to an optical proximity correction (OPC) algorithm, or otherwise. In an example, such variations may be to fine tune a resistance of the resistor of the device 100.

[0048] As illustrated in Fig. 1C, irrespective of the variation of the widths of the conductive lines l08a and l08b, the width of the dielectric material 112 between adjacent sidewalls of two conductive lines is maintained at cl. For example, in Fig. 1C, a right sidewall of the conductive line l08a and a left sidewall of the conductive line 116b is separated by the dielectric material 112 having uniform width cl. The uniformity of the width of the dielectric material 112 may be maintained because, for example, the dielectric material 112 is formed by conformal deposition of dielectric material, as discussed herein later in further details.

Accordingly, in some embodiments, a shape of the right sidewall of the conductive line l08a is complementary to a shape of the left sidewall of the conductive line 1 l6b.

[0049] Thus, for example, a space between the conductive lines l08a and l08b may vary as a function of the widths or shapes of the conductive lines l08a and l08b. In some

embodiments, the width of the conductive line 1 l6b varies by the same amount as the space varies (e.g., as the width of the dielectric material 112 is maintained at cl). Thus, due to the uniformity of the width of the dielectric material 112, the compensation conductive line 1 l6b compensates for any variation of the width of the conductive lines l08a, l08b.

[0050] In some embodiments, the widths of the conductive lines l08a, l08b, l08c may be similar, and the widths of one or more of the conductive lines 116 may be different from the widths of the conductive lines l08a, l08b, l08c. For example, a difference between a width of the conductive line 1 l6b and widths of either of the conductive lines l08a and l08b is greater than a difference between the widths of the conductive lines l08a and l08b. Merely as an example, a difference between widths of the conductive lines l08a and l08b is less than 5% of the width of the conductive line l08a, and a difference between widths of the conductive lines l08a and 116b is greater than 10% of the width of the conductive line l08a.

[0051] Fig. ID illustrates a graph 190 depicting comparison of the resistor in the device

100 having compensation for possible variation of conductive lines 116 and a resistor that does not provide any such compensation, according to some embodiments. The boxes 193 a, l93b, l93c, l93d, l93e, l93f, and l93g with diagonal shades correspond to the resistor in the device 100 having the compensation conductive lines 116. The boxes l94a, l94b, l94c, l94d, l94e, l94f, and l94g with dots correspond to the resistor without any such compensation (also referred to as an uncompensated resistor). The uncompensated resistor does not have any compensation conductive lines - it only has backbone conductive lines.

[0052] The X axis of the graph 190 represents the width of the conductive lines for the two resistors (e.g., the width of the backbone conductive lines). The Y axis represents the resistance of the two resistors. The dotted line 102 represents a nominal or intended resistance Rl intended for the two resistors.

[0053] Referring to boxes 193 a and l93b, these boxes pertain to a scenario where widths of the conductive lines of the two resistors (e.g., backbone conductive lines 108 of the resistor of the device 100, and backbone conductive lines of the uncompensated resistor) are about 50% less than their respectively intended widths. In such a scenario, the resistor of the device 100 has a resistance value that is much closer to the nominal resistance Rl, e.g., compared to the uncompensated resistor.

[0054] Referring to boxes l94a and l94b, these boxes pertain to a scenario where widths of the conductive lines of the two resistors are about 20% less than their respectively intended widths. In such a scenario, the resistor of the device 100 has a resistance value that is much closer to the nominal resistance Rl, e.g., compared to the uncompensated resistor.

[0055] Other boxes illustrate scenarios where widths of the conductive lines of the two resistors are: about 5% less than their respectively intended widths, exactly correspond to their nominal widths, about 5% more than their respectively intended widths, about 20% more than their respectively intended widths, and about 50% more than their respectively intended widths, as illustrated in Fig. ID. In an example, as seen in Fig. ID, the compensation in the device 100 may produce a net resistance that may be close to the nominal value, e.g., even at a fairly extreme 20% variation in the line width.

[0056] In an example, the compensation in the device 100 generate a resistance that may be higher than the nominal resistance Rl . For example, all the boxes l93a, l93b, l93c, l93d, l93e, l93f, and l93g (e.g., boxes corresponding to the resistor of the device 100) are equal to, or higher than the line 192 in Fig. ID. This may be because, for example, reducing the width of a conductive line may increase its resistance more than increasing the width of the same conductive line by the same amount decreases its resistance.

[0057] For example, assume that the width of the backbone conductive line l08a is reduced by 5 nanometer (nm) from its intended or nominal width, due to which the resistance of the conductive line l08a increases by 0.5 ohms (note that the numerical values are merely examples to clarify aspects of this disclosure, and does not in any manner limit the teachings of this disclosure). The adjacent compensation conductive line 116b may correspondingly increase by 5 nm, and as a result, the resistance of the conductive line 1 l6b may decrease by 0.4 ohms. This may result in a net increase of 0.1 ohms in the resistor of the device 100. Thus, the compensation conductive lines 116 compensate by reducing the increase in the resistance from 0.5 ohms to 0.1 ohms. The overall resistance of the device 100 may still be slightly higher (e.g., 0.1 ohms higher) than the nominal resistance. Note that without any compensation, the overall resistance would have increased by 0.5 ohms.

[0058] In another example, assume that the width of the backbone conductive line l08a is increased by 5 nm from its intended or nominal, due to which the resistance of the conductive line l08a decreases by 0.4 ohms. The adjacent compensation conductive line 1 l6b may correspondingly decrease by 5 nm, and as a result, the resistance of the conductive line 1 l6b may increase by 0.5 ohms. Similar to the above example, this may result in a net increase of 0.1 ohms in the resistor of the device 100. Thus, the overall resistance of the device 100 may still be slightly higher (e.g., 0.1 ohms higher) than the nominal resistance. Note that without any compensation, the overall resistance would have decreased by 0.4 ohms.

[0059] Thus, in the example of Fig. ID, the compensation in the device 100 generate a resistance that may be higher than, or substantially equal to, the nominal resistance Rl. For example, all the boxes l93a, l93b, l93c, l93d, l93e, l93f, and l93g are equal to, or higher than the line 192 in Fig. ID.

[0060] Because the compensation in the device 100 mostly generates a resistance that is higher than the nominal resistance Rl, in some embodiments, sections of the resistor 100 may be shorted out, e.g., such that the resistance of the device 100 comes closer to the intended nominal value Rl (e.g., if even greater resistance accuracy or resistance compensation is to be achieved). Fig. IE illustrated the device 100 of Figs. 1A-1B, where one or more antifuses (e.g., antifuse 184) may be used to short one or more corresponding sections of the resistor of the device 100, according to some embodiments. For example, in Fig. IE, an antifuse 184 (illustrated symbolically in the figure) is coupled between the conductive lines 1 l6a and 1 l6b. If reduction of the resistance of the device 100 is desired (e.g., to bring the resistance closer to the nominal value Rl, as discussed with respect to Fig. ID), the antifuse 184 may be blown or activated, which may short the conductive lines 1 l6a and 1 l6b (e.g., thereby shunting out the conductive lines l08a and l22a) and reduce the overall resistance of the device 100. Although Fig. IE illustrates only one example antifuse 184, in an example, the device 100 may have multiple such antifuses. Although Fig. IE illustrates the antifuse 184 shorting two conductive lines, in an example, the antifuse may short sections of one conductive line, three conductive lines, sections of multiple conductive lines, and/or the like.

[0061] Referring again to Fig. 1A-1B, as discussed herein, the device 100 may form a resistor, and the conductive lines 1 l6a and 1 l6d may form two terminals of the resistor. In some embodiments, the interconnect structures 120, 122 of the device 100 can also be arranged in a different manner to form a capacitor instead. Fig. IF illustrates a device 100’, which may be similar to the device 100 of Figs. 1A-1B, but with the interconnect structures 120, 122 arranged in a different manner, to form a capacitor, according to some embodiments. For example, the interconnect structures l20a, l20b may interconnect the conductive lines l08a, l08b, l08c; and the interconnect structures l22a, l22b, l22c may interconnect the conductive lines H6a, H6b, 1 l6c, 1 l6d. In some embodiments, the conductive lines l08a, l08b, l08c act as a first terminal of the capacitor, and the conductive lines 1 l6a, 1 l6b, 1 l6c, 116d act as a second terminal of the capacitor. For example, as the spacing between the conductive lines may be tightly controlled (e.g., as the dielectric material 112 has a uniform width of cl), the device 100’ may be used as the capacitor.

[0062] Figs. 2A, 2B, 2C, 2D, 2E, and 2F illustrate an example process for forming the device 100 of Figs. 1A-1B, according to some embodiments. For example, Figs. 2A-2E are cross-sectional views of the device 100 evolving as example operations for formation of the device 100 are performed, and Fig. 2F is a plan view of the device 100.

[0063] Referring to Fig. 2A, backbone conductive lines l08a, l08b, l08c are formed over the substrate 104. For example, conductive material may be deposited over the substrate 104 to form the conductive lines 108. As discussed with respect to Fig. IB, widths of the conductive lines l08a, l08b, l08c are al, a2, and a3, respectively. As also discussed with respect to Fig. IB, the conductive lines l08a and l08b are separated by a space having a width of Sl; and the conductive lines l08b and l08c are separated by a space having a width of S2.

[0064] Referring now to Fig. 2B, in some embodiments, dielectric material 112 is conformally deposited on the conductive lines 108. Due to the conformal deposition of the dielectric material 112, the dielectric material 112 has a uniform width of about cl (e.g., within ±5% of cl). For example, trenches may form within the dielectric material 112, where the trenches have widths of bl, b2, b3, and b4. As discussed in further detail with respect to Figs. 1A-1B, the widths bl, b2, b3, and b4 may be a function of the widths of the conductive lines 108.

[0065] Referring now to Fig. 2C, in some embodiments, the trenches are backfilled with conductive material 216. Referring now to Fig. 2D, in some embodiments, the conductive material 216 is polished to reveal the top surfaces of the conductive lines 108. Polishing the conductive material 216 results in formation of the conductive lines 1 l6a, 1 l6b, 1 l6c, and 1 l6d. In some embodiments, the top surfaces of the conductive lines 108 and 116 are coplanar (e.g., as the polishing operation is to remove the dielectric material 112 and the conductive material 216 to form the conductive lines 116 and to reveal the conductive lines 108).

[0066] Referring now to Figs. 2E and 2F (where Fig. 2E and Fig. 2F respectively illustrate the cross sectional and plan view, similar to Figs. 1A-1B, respectively), in some embodiments, interconnect structures 120 and 122 may be formed. In an example, further dielectric material 112 may be deposited to cover the interconnect structures 120 and 122, e.g., to form the device 100. In some embodiments (and although not illustrated in Figs. 2E-2F), the interconnect structures 120 and 122 can be formed in a different manner to form the device 100’ of Fig. IF

[0067] Figs. 3A and 3B illustrate a device 300 comprising another thin film resistor, in which widths of one or more conductive lines of the device 300 are compensated for possible variation in widths of another one or more conductive lines, according to some embodiments.

Fig. 3A illustrates a cross-sectional view of the device 300, and Fig. 3B illustrates a plan view of the device 300.

[0068] The device 300 of Figs. 3A-3B may be at least in part similar to the device 100 of

Figs. 1A-1B. For example, the device 300 may include backbone conductive lines 308a, 308b, 308c, and compensation conductive lines 3 l6a, 3 l6b, 3 l6c, 3 l6d, which may be similar to the backbone conductive lines 108 and compensation conductive lines 116, respectively, of the device 100 of Fig. 1A-1B. Furthermore, similar to the interconnect structures 120, 122 of the device 100 of Figs. 1A-1B, the device 300 may comprise interconnect structures 320a, 320b, 320c, 322a, 322b, 322c. Also, similar to the dielectric material 112 of the device 100 of Figs. 1A-1B, the device 300 may comprise dielectric material 312. Accordingly, these components of the device 300 are not discussed in further details herein. Relevant discussion of these components with respect to the device of Figs. 1A-1E may also apply to the device 300 of Figs. 3A-3B, unless such discussion is contrary to or contradicts the structure of the device 300 (or unless specified in this disclosure).

[0069] In some embodiments, unlike the device 100 (e.g., in which the dielectric material

112 separated the bottom surfaces of the compensation conductive lines 116 from the substrate 104), in the device 300, no substantial dielectric material 312 is present between the bottom surfaces of the compensation conductive lines 316 and the substrate 304. However, traces of dielectric material 312 may be present between the bottom surfaces of the compensation conductive lines 316 and the substrate 304 (e.g., for reasons discussed herein later). In an example, no traces of dielectric material 312 may be present between the bottom surfaces of the backbone conductive lines 308 and the substrate 304 (e.g., for reasons discussed herein later).

For example, a thickness of the traces of the dielectric material 312 present between the bottom surfaces of the compensation conductive lines 316 and the substrate 304 may be 5% or less, 1% or less, 0.5 % or less, or less than 0.1% of the width cl of the dielectric material 312 elsewhere.

[0070] In some embodiments (e.g., unlike the device 100), sidewalls of the compensation conductive lines 316 in the device 300 may be sloped (e.g., at an angle that is not perpendicular) with respect to the substrate 304. For example, Fig. 3C illustrates a magnified cross-sectional view of the device 300, in which the sidewalls of the compensation conductive lines 316 may be slanted (e.g., at an angle that is not perpendicular) with respect to the substrate 304, according to some embodiments. Fig. 3C illustrates only the conductive lines 3 l6a, 3 l6b, 308a, and 308b.

[0071] In some embodiments, the sidewalls of the backbone conductive lines 308 are about perpendicular, e.g., at about 90^° angle (e.g., 90^°± 0.5^°, 90^° ± 1^°, or 90^°± 2^°) with respect to the substrate 304 (e.g., angles 371 and 372 of Fig. 3C).

[0072] In some embodiments, the compensation conductive lines 316 may be tapered, such that a top surface of a compensation conductive line 316 has a larger surface area than a bottom surface of the compensation conductive line 316. For example, a first sidewall of the conductive line 3 l6b may be at an angle 373 with respect to the substrate 304, where the angle 373 may be an obtuse angle (e.g., larger than 90^°, 90.5^° or larger, 91^° or larger, or 92^° or larger). For example, a second sidewall of the conductive line 3 l6b may be at an angle 374 with respect to the substrate 304, where the angle 374 may be an acute angle (e.g., smaller than 90^°, at most 89.5^° or smaller, at most 89^° or smaller, or at most 88^° or smaller).

[0073] Thus, in some embodiments, sidewalls of the backbone conductive lines 308 are about perpendicular with respect to the substrate 304. For individual compensation conductive lines 316, a first sidewall is at an acute angle with respect to the substrate 304, and a second sidewall is at an obtuse angle with respect to the substrate 304. Rationale behind such geometry of the conductive lines 308, 316 are discussed in further details herein later. In contrast, in an example, the sidewalls of the conductive lines 108, 116 in the device 100 may be about perpendicular with respect to the substrate 104.

[0074] Figs. 4A, 4B, 4C, 4D, 4E, 4F, and 4G illustrate an example process for forming the device 300 of Figs. 3A-3C, according to some embodiments. For example, Figs. 4A-4F are cross-sectional views of the device 300 evolving as example operations for formation of the device 300 are performed, and Fig. 4G is a plan view of the final device 300. [0075] Referring to Fig. 4A, backbone conductive lines 308a, 308b, 308c are formed over the substrate 304. For example, conductive material may be deposited over the substrate 304 to form the conductive lines 308. Similar to Fig. 2A, widths of the conductive lines 308a, 308b, 308c are al, a2, and a3, respectively. Similar to Fig. 2A, the conductive lines 308a and 308b are separated by a space having a width of Sl; and the conductive lines 308b and 308c are separated by a space having a width of S2.

[0076] Referring now to Fig. 4B, in some embodiments, dielectric material 312 is conformally deposited on the conductive lines 308. Due to the conformal deposition of the dielectric material 312, the dielectric material 312 has a uniform width of about cl (e.g., within ±5% of cl). For example, trenches may form within the dielectric material 312, where the trenches have widths of bl, b2, b3, and b4. The widths bl, b2, b3, and b4 may be a function of the widths of the conductive lines 308.

[0077] Referring now to Fig. 4C, in some embodiments, the trenches are extended, e.g., by etching the dielectric material 312 through the trenches. In some embodiments, the substrate 304 is exposed through the trenches. In some embodiments, traces of the dielectric material 312 remains on the substrate 304 within the trenches, e.g., after selectively etching the dielectric material 312. In an example, amount of such traces of the dielectric material 312 remaining on the substrate 304 within the trenches may depend on the etching process.

[0078] Referring now to Fig. 4D, in some embodiments, the extended trenches are backfilled with conductive material 416. Referring now to Fig. 4E, in some embodiments, the conductive material 416 are polished to reveal the top surfaces of the conductive lines 308 and the top surfaces of the dielectric material 312, thereby forming the conductive lines 3 l6a, 3 l6b,

3 l6c, and 3 l6d from the conductive material 416. In some embodiments, the top surfaces of the conductive lines 308 and 316 are coplanar.

[0079] Referring now to Figs. 4F and 4G (where Fig. 4F and Fig. 4G respectively illustrates the cross sectional and plan view, similar to Figs. 3A-3B, respectively), in some embodiments, interconnect structures 320 and 322 may be formed. In an example, further dielectric material 312 may be deposited to cover the interconnect structures 320 and 322, e.g., to form the device 300.

[0080] In some embodiments (and although not illustrated in Figs. 4F-4G), the interconnect structures 320 and 322 can be formed in a different manner, e.g., such that the interconnect structures 320 interconnect the conductive lines 308a, 308b, and 308c; and the interconnect structures 322 interconnect the conductive lines 3 l6a, 3 l6b, l6c, and 3 l6d, e.g., as discussed with respect to Fig. IF (e.g., to form a capacitor).

[0081] Referring again to Fig. 4A, the conductive lines 308 are formed via deposition of conductive material over the substrate 104. Accordingly, in some embodiments, sidewalls of the conductive lines 308 are about perpendicular with respect to the substrate 304 (e.g., as discussed with respect to Fig. 3C).

[0082] In contrast, the conductive lines 316 are formed in a space formed by etching the dielectric material 312, e.g., as discussed with respect to Figs. 4B-4D. In some embodiments, etching the dielectric material 312 may form the trenches in Fig. 4C with slanted or tapered sidewalls (e.g., a bottom of a trench on the substrate 304 may have smaller area than a top of the trench that is coplanar with the top surface of the conductive lines 308), although such slanting is not illustrated in Fig. 4C. Thus, when the conductive materials 416 are backfilled in the trenches and the conductive lines 316 are formed, the sidewalls of individual conductive lines 316 may be either at an acute angle or obtuse angle, as discussed with respect to Fig. 3C.

[0083] Fig. 5 is a flow diagram illustrating a method 500 of forming a resistor of a device

(e.g., the device 100 and/or 300), in which widths of one or more conductive lines of the device are compensated for possible variation in widths of another one or more conductive lines, according to some embodiments. Although the blocks in the flowchart with reference to Fig. 5 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 5 may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

[0084] In some embodiments, the method 500 includes, at 504, forming a first line and a second line (e.g., lines l08a and l08b of Fig. 2A, or lines 308a and 308b of Fig. 4A). In some embodiments, the first and second lines comprise a first conductive material and are separated by a space therebetween.

[0085] In some embodiments, the method 500 includes, at 508, conformally depositing a first thickness of dielectric material (e.g., dielectric material 112 or Fig. 2B, or dielectric material 312 or Fig. 4B) over a sidewall the first line and over a sidewall of the second line. In some embodiments, the method 500 includes, at 512, forming a third line (e.g., line 1 l6b of Fig. 2D, or line 3 l6b of Fig. 4E) by backfilling a remainder of the space with a second conductive material, subsequent to conformally depositing the dielectric material. In some embodiments, the method 500 includes, at 516, forming an interconnect structure (e.g., interconnect structure l20b of Fig. 2E, or interconnect structure 320b of Fig. 4F) over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

[0086] Fig. 6 illustrates a computing device or a SoC (System-on-Chip) including a device including a thin film resistor (e.g., the device 100 and/or 300, of Figs. 1A-5), in which widths of one or more compensation conductive lines of the device are compensated for possible variation in widths of one or more backbone conductive lines (e.g., to reduce variation in resistance of the device due to variation in widths of the backbone conductive lines), according to some embodiments. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0087] In some embodiments, computing device 2100 represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an IOT device, a server, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 2100.

[0088] In some embodiments, computing device 2100 includes a first processor 2110.

The various embodiments of the present disclosure may also comprise a network interface within 2170 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0089] In one embodiment, processor 2110 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 2110 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 2100 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0090] In one embodiment, computing device 2100 includes audio subsystem 2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 2100, or connected to the computing device 2100. In one embodiment, a user interacts with the computing device 2100 by providing audio commands that are received and processed by processor 2110.

[0091] Display subsystem 2130 represents hardware (e.g., display devices) and software

(e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 2100. Display subsystem 2130 includes display interface 2132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 2132 includes logic separate from processor 2110 to perform at least some processing related to the display. In one embodiment, display subsystem 2130 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0092] I/O controller 2140 represents hardware devices and software components related to interaction with a user. I/O controller 2140 is operable to manage hardware that is part of audio subsystem 2120 and/or display subsystem 2130. Additionally, I/O controller 2140 illustrates a connection point for additional devices that connect to computing device 2100 through which a user might interact with the system. For example, devices that can be attached to the computing device 2100 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0093] As mentioned above, I/O controller 2140 can interact with audio subsystem 2120 and/or display subsystem 2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 2100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 2130 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 2140. There can also be additional buttons or switches on the computing device 2100 to provide I/O functions managed by I/O controller 2140.

[0094] In one embodiment, I/O controller 2140 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 2100. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0095] In one embodiment, computing device 2100 includes power management 2150 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 2160 includes memory devices for storing information in computing device 2100. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 2160 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 2100. In one embodiment, computing device 2100 includes a clock generation subsystem 2152 to generate a clock signal.

[0096] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 2160) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 2160) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g.,

BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0097] Connectivity 2170 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 2100 to communicate with external devices. The computing device 2100 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0098] Connectivity 2170 can include multiple different types of connectivity. To generalize, the computing device 2100 is illustrated with cellular connectivity 2172 and wireless connectivity 2174. Cellular connectivity 2172 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 2174 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0099] Peripheral connections 2180 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 2100 could both be a peripheral device ("to" 2182) to other computing devices, as well as have peripheral devices ("from" 2184) connected to it. The computing device 2100 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 2100. Additionally, a docking connector can allow computing device 2100 to connect to certain peripherals that allow the computing device 2100 to control content output, for example, to audiovisual or other systems.

[00100] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 2100 can make peripheral connections 2180 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00101] In some embodiments, the device 100 and/or 300 (e.g., comprising the thin film resistor discussed herein) may be used as a resistor (or the device 100’ may be used as a capacitor) in any appropriate component of the computing device 2100. The device may be formed, e.g., as discussed with respect to Figs. 1A-5. In some embodiments, the device 100, 100’, and/or 300 may be used for any appropriate application of the computing device 2100, e.g., where one or more resistors or capacitors may be used (e.g., in the processor 2110, a memory of the memory subsystem 2160, and/or another component of the computing device 2100).

[00102] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or

characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an

embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00103] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive

[00104] While the disclosure has been described in conjunction with specific

embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00105] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00106] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00107] Example 1. An integrated circuit (IC) structure, comprising: a first line and a second line comprising a first conductive material, the first line and the second line separated by a space therebetween; a dielectric material and a third line in the space between the first and second lines, wherein the third line comprises a second conductive material, and wherein a top surface of the third line is coplanar with top surfaces of the first and second lines; a substrate, wherein the first and second lines are on the substrate and the third line is over a thickness of the dielectric material on the substrate; and an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

[00108] Example 2. The IC structure of example 1 or any other example, wherein: the first line is of a first width, the second line of a second width, and the third line is of a third width; the dielectric material between a sidewall of the first line and a sidewall of the third line has a fourth width; and the dielectric material between a sidewall of the second line and another sidewall of the third line has the fourth width.

[00109] Example 3. The IC structure of example 2 or any other example, wherein the third width is equal to a width of the space between the first and second lines minus twice the fourth width, and wherein at least one of the first, second and third widths is unequal to another of the first, second and third widths.

[00110] Example 4. The IC structure of example 2 or any other example, wherein: the first width varies over a first length of the first line; the second width varies over a second length of the second line adjacent to the first length; the space between the first and second lines varies as a function of the first and second widths; and the third width varies by the same amount as the space varies. [00111] Example 5. The IC structure of example 2 or any other example, further comprising: a fourth line separated from the first line by a second space therebetween, wherein the fourth line comprises the first conductive material; dielectric material and a fifth line in the space between the first and fourth lines, wherein the dielectric material between another sidewall of the first line and a sidewall of the fifth line has the fourth width, and wherein the dielectric material between a sidewall of the fourth line and another sidewall of the fifth line has the fourth width; and another interconnect structure over the dielectric material, wherein the interconnect structure comprises the third conductive material in contact with the fourth line and in contact with the fifth line.

[00112] Example 6. The IC structure of example 2 or any other example, wherein a difference between the third width and either of the first and second widths is greater than a difference between the first and second widths.

[00113] Example 7. The IC structure of example 2 or any other example, wherein the thickness of the dielectric material under the third line is within 5% of the fourth width.

[00114] Example 8. The IC structure of any one of examples 1-7 or any other example, wherein the first interconnect structure is in contact with the first line and a first end of the third line, and wherein the IC structure further comprises: a second interconnect structure over the dielectric material, the second interconnect structure comprising the third conductive material, in contact with a second end of the third line, and in contact with the second line.

[00115] Example 9. The IC structure of any one of examples 1-7 or any other example, wherein the interconnect structure is a first interconnect structure that is in contact with the first line and the second line, and wherein the IC structure further comprises: a second interconnect structure over the dielectric material, the second interconnect structure comprising the third conductive material, in contact with the third line, and in contact with a fourth line that is separated from the first line by a second space therebetween.

[00116] Example 10. The IC structure of example 9 or any other example, wherein the IC structure comprises a capacitor with a first terminal comprising the first interconnect structure, and a second terminal comprising the second interconnect structure.

[00117] Example 11. The IC structure of any one of examples 1-7 or any other example, wherein: the first and second conductive materials comprise titanium and nitrogen; and the interconnect structure comprises one or more of tantalum, nitrogen, copper, or ruthenium. [00118] Example 12. The IC structure of any one of examples 1-7 or any other example, further comprising: an antifuse structure over the dielectric material, wherein the antifuse structure comprises a first terminal coupled to one of the first, second, or third lines, and a second terminal coupled to another of the first, second, or third lines, the antifuse structure to selectively short out one or more of the first, second, or third lines.

[00119] Example 13. The IC structure of any of examples 1-7 or any other example, wherein the first conductive material and the second conductive material comprises same material.

[00120] Example 14. The IC structure of any of examples 1-7 or any other example, wherein a variation of resistance with temperature for the first conductive material is different from a variation of resistance with temperature for the second conductive material.

[00121] Example 15. The IC structure of any of examples 1-7 or any other example, wherein the first conductive material has a first resistivity that is higher than a second resistivity of the second conductive material.

[00122] Example 16. A system comprising: a memory to store instructions; and a processor coupled to the memory, the processor to execute the instructions, wherein one of the memory, the processor, or another component of the system comprises a structure comprising: a first line and a second line comprising a first conductive material, the first line and the second line separated by a space therebetween; a dielectric material and a third line in the space between the first and second lines, wherein the third line comprises a second conductive material, and wherein a top surface of the third line is coplanar with top surfaces of the first and second lines; a substrate, wherein the first and second lines are on the substrate and the third line is over a thickness of the dielectric material on the substrate; and an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

[00123] Example 17. The system of example 16 or any other example, wherein: the first line of a first width varies over a first length of the first line; the second line of a second width that varies over a second length of the second line adjacent to the first length; the space between the first and second lines varies as a function of the first and second widths; and the third line is of a third width that varies by the same amount as the space varies. [00124] Example 18. The system of any of examples 16-17 or any other example, wherein the structure is a thin film resistor.

[00125] Example 19. A resistor comprising: a first line and a second line over a substrate, the first and second lines comprising a first conductive material, the first line and the second line separated by a space therebetween; a dielectric material and a third line over the substrate and in the space between the first and second lines, wherein the third line comprises a second conductive material, and wherein a top surface of the third line is coplanar with top surfaces of the first and second lines; and an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines, wherein a sidewall of the first line is at a first angle with respect to the substrate, wherein a first sidewall of the third line is at a second angle with respect to the substrate, wherein a second sidewall of the third line is at a third angle with respect to the substrate, wherein the third angle is larger than the first angle, and wherein the first angle is larger than the second angle.

[00126] Example 20. The resistor of example 19 or any other example, wherein: a sidewall of the second line is at the first angle with respect to the substrate; the first angel is a perpendicular angle; the second angle is an acute angle; and the third angle is an obtuse angle.

[00127] Example 21. The resistor of any of examples 19-20 or any other example, wherein: the first line and the second line are on a substrate; and a third line is over the substrate, with traces of the dielectric material between the third line and the substrate.

[00128] Example 22. A method comprising: forming a first line and a second line, wherein the first and second lines comprise a first conductive material and are separated by a space therebetween; conformally depositing a first thickness of dielectric material over a sidewall the first line and over a sidewall of the second line; forming a third line by backfilling a remainder of the space with a second conductive material, subsequent to conformally depositing the dielectric material; and forming an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

[00129] Example 23. The method of example 22 or any other example, wherein forming the third line comprises: selectively removing the dielectric material from the space to empty the reminder of the space; and forming the third line by backfilling the remainder of the space with the second conductive material, subsequent to selectively removing the dielectric material.

[00130] Example 24. The method of any of examples 22-23 or any other example, wherein forming the interconnect structure further comprises: polishing top surfaces of the first, second and third lines, such that the top surfaces of the first, second and third lines is coplanar; and forming the interconnect structure, subsequent to polishing the top surfaces of the first, second and third lines.

[00131] Example 25. The method of any of examples 22-23 or any other example, wherein the first interconnect structure is in contact with the first line and a first end of the third line, and wherein the method further comprises: forming a second interconnect structure over the dielectric material, the second interconnect structure comprising the third conductive material, in contact with a second end of the third line, and in contact with the second line.

[00132] Example 26. An apparatus comprising: means for performing the method of any of the examples 21-25 or any other example.

[00133] Example 27. An apparatus comprising: means for forming a first line and a second line, wherein the first and second lines comprise a first conductive material and are separated by a space therebetween; means for conformally depositing a first thickness of dielectric material over a sidewall the first line and over a sidewall of the second line; means for forming a third line by backfilling a remainder of the space with a second conductive material, subsequent to conformally depositing the dielectric material; and means for forming an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

[00134] Example 28. The apparatus of example 27 or any other example, wherein the means for forming the third line comprises: means for selectively removing the dielectric material from the space to empty the reminder of the space; and means for forming the third line by backfilling the remainder of the space with the second conductive material, subsequent to selectively removing the dielectric material.

[00135] Example 29. The apparatus of any of examples 27-28 or any other example, wherein the means for forming the interconnect structure further comprises: means for polishing top surfaces of the first, second and third lines, such that the top surfaces of the first, second and third lines is coplanar; and means for forming the interconnect structure, subsequent to polishing the top surfaces of the first, second and third lines.

[00136] Example 30. The apparatus of any of examples 27-28 or any other example, wherein the first interconnect structure is in contact with the first line and a first end of the third line, and wherein the apparatus further comprises: means for forming a second interconnect structure over the dielectric material, the second interconnect structure comprising the third conductive material, in contact with a second end of the third line, and in contact with the second line.

[00137] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An integrated circuit (IC) structure, comprising:

a first line and a second line comprising a first conductive material, the first line and the second line separated by a space therebetween;

a dielectric material and a third line in the space between the first and second lines, wherein the third line comprises a second conductive material, and wherein a top surface of the third line is coplanar with top surfaces of the first and second lines;

a substrate, wherein the first and second lines are on the substrate and the third line is over a thickness of the dielectric material on the substrate; and

an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

2. The IC structure of claim 1, wherein:

the first line is of a first width, the second line of a second width, and the third line is of a third width;

the dielectric material between a sidewall of the first line and a sidewall of the third line has a fourth width; and

the dielectric material between a sidewall of the second line and another sidewall of the third line has the fourth width.

3. The IC structure of claim 2, wherein the third width is equal to a width of the space between the first and second lines minus twice the fourth width, and wherein at least one of the first, second and third widths is unequal to another of the first, second and third widths.

4. The IC structure of claim 2, wherein:

the first width varies over a first length of the first line;

the second width varies over a second length of the second line adjacent to the first length; the space between the first and second lines varies as a function of the first and second widths; and

the third width varies by the same amount as the space varies.

5. The IC structure of claim 2, further comprising:

a fourth line separated from the first line by a second space therebetween, wherein the fourth line comprises the first conductive material;

dielectric material and a fifth line in the space between the first and fourth lines, wherein the dielectric material between another sidewall of the first line and a sidewall of the fifth line has the fourth width, and wherein the dielectric material between a sidewall of the fourth line and another sidewall of the fifth line has the fourth width; and

another interconnect structure over the dielectric material, wherein the interconnect structure comprises the third conductive material in contact with the fourth line and in contact with the fifth line.

6. The IC structure of claim 2, wherein a difference between the third width and either of the first and second widths is greater than a difference between the first and second widths.

7. The IC structure of claim 2, wherein the thickness of the dielectric material under the third line is within 5% of the fourth width.

8. The IC structure of any one of claims 1-7, wherein the first interconnect structure is in contact with the first line and a first end of the third line, and wherein the IC structure further comprises:

a second interconnect structure over the dielectric material, the second interconnect structure comprising the third conductive material, in contact with a second end of the third line, and in contact with the second line.

9. The IC structure of any one of claims 1-7, wherein the interconnect structure is a first interconnect structure that is in contact with the first line and the second line, and wherein the IC structure further comprises: a second interconnect structure over the dielectric material, the second interconnect structure comprising the third conductive material, in contact with the third line, and in contact with a fourth line that is separated from the first line by a second space therebetween.

10. The IC structure of claim 9, wherein the IC structure comprises a capacitor with a first terminal comprising the first interconnect structure, and a second terminal comprising the second interconnect structure.

11. The IC structure of any one of claims 1-7, wherein:

the first and second conductive materials comprise titanium and nitrogen; and

the interconnect structure comprises one or more of tantalum, nitrogen, copper, or ruthenium.

12. The IC structure of any one of claims 1-7, further comprising:

an antifuse structure over the dielectric material, wherein the antifuse structure comprises a first terminal coupled to one of the first, second, or third lines, and a second terminal coupled to another of the first, second, or third lines, the antifuse structure to selectively short out one or more of the first, second, or third lines.

13. The IC structure of any of claims 1-7, wherein the first conductive material and the second conductive material comprises same material.

14. The IC structure of any of claims 1-7, wherein a variation of resistance with temperature for the first conductive material is different from a variation of resistance with temperature for the second conductive material.

15. The IC structure of any of claims 1-7, wherein the first conductive material has a first resistivity that is higher than a second resistivity of the second conductive material.

16. A system comprising:

a memory to store instructions; and a processor coupled to the memory, the processor to execute the instructions, wherein one of the memory, the processor, or another component of the system comprises a structure comprising:

17. The system of claim 16, wherein:

the first line of a first width varies over a first length of the first line;

the second line of a second width that varies over a second length of the second line adjacent to the first length;

the space between the first and second lines varies as a function of the first and second widths; and

the third line is of a third width that varies by the same amount as the space varies.

18. The system of any of claims 16-17, wherein the structure is a thin film resistor.

19. A resistor comprising:

a first line and a second line over a substrate, the first and second lines comprising a first conductive material, the first line and the second line separated by a space therebetween;

a dielectric material and a third line over the substrate and in the space between the first and second lines, wherein the third line comprises a second conductive material, and wherein a top surface of the third line is coplanar with top surfaces of the first and second lines; and an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines,

wherein a sidewall of the first line is at a first angle with respect to the substrate, wherein a first sidewall of the third line is at a second angle with respect to the substrate, wherein a second sidewall of the third line is at a third angle with respect to the substrate, wherein the third angle is larger than the first angle, and wherein the first angle is larger than the second angle.

20. The resistor of claim 19, wherein:

a sidewall of the second line is at the first angle with respect to the substrate;

the first angel is a perpendicular angle;

the second angle is an acute angle; and

the third angle is an obtuse angle.

21. The resistor of any of claims 19-20, wherein:

the first line and the second line are on a substrate; and

a third line is over the substrate, with traces of the dielectric material between the third line and the substrate.

22. A method comprising:

forming a first line and a second line, wherein the first and second lines comprise a first conductive material and are separated by a space therebetween;

conformally depositing a first thickness of dielectric material over a sidewall the first line and over a sidewall of the second line;

forming a third line by backfilling a remainder of the space with a second conductive material, subsequent to conformally depositing the dielectric material; and

forming an interconnect structure over the dielectric material, wherein the interconnect structure comprises a third conductive material in contact with a first of the first, second or third lines, and in contact with a second of the first, second, or third lines.

23. The method of claim 22, wherein forming the third line comprises: selectively removing the dielectric material from the space to empty the reminder of the space; and

forming the third line by backfilling the remainder of the space with the second conductive material, subsequent to selectively removing the dielectric material.

24. The method of any of claims 22-23, wherein forming the interconnect structure further comprises:

polishing top surfaces of the first, second and third lines, such that the top surfaces of the first, second and third lines is coplanar; and

forming the interconnect structure, subsequent to polishing the top surfaces of the first, second and third lines.

25. The method of any of claims 22-23, wherein the first interconnect structure is in contact with the first line and a first end of the third line, and wherein the method further comprises: forming a second interconnect structure over the dielectric material, the second interconnect structure comprising the third conductive material, in contact with a second end of the third line, and in contact with the second line.