JPH06120223A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH06120223A
JPH06120223A JP28344092A JP28344092A JPH06120223A JP H06120223 A JPH06120223 A JP H06120223A JP 28344092 A JP28344092 A JP 28344092A JP 28344092 A JP28344092 A JP 28344092A JP H06120223 A JPH06120223 A JP H06120223A
Authority
JP
Japan
Prior art keywords
wiring
power supply
functional block
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28344092A
Other languages
Japanese (ja)
Other versions
JP3179211B2 (en
Inventor
Masami Kishimoto
政己 岸本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP28344092A priority Critical patent/JP3179211B2/en
Publication of JPH06120223A publication Critical patent/JPH06120223A/en
Application granted granted Critical
Publication of JP3179211B2 publication Critical patent/JP3179211B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent deterioration of interelement matching of a plurality of elements arranged in a function block, and enable reducing of the wiring regions of power supply wiring and earth wiring which connect a plurality of the function blocks. CONSTITUTION:In a semiconductor integrated circuit device wherein power supply wiring VCC and earth wiring GND are arranged on both side parts of a function block 1, and elements Q1-Q6 and R1-R4 are connected with the power supply wiring and the earth wiring through element wiring 2, each of the power supply wiring and the earth wiring is formed in a line type with arbitrary width, and the element wiring which connects elements in the function block is connected with the power supply wiring and the earth wiring, at one point of each wiring.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はアナログ回路の半導体集
積回路装置に関し、特にコンピュータによる自動配置配
線に使用される機能ブロックの構成に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device of an analog circuit, and more particularly to a configuration of functional blocks used for automatic placement and routing by a computer.

【0002】[0002]

【従来の技術】近年の大規模アナログ集積回路では、設
計期間の短縮、及び設計の標準化を図るため、数十素子
の回路素子を1つの機能ブロック単位とし、各機能ブロ
ックの配置配線をコンピュータにより行っている。この
ような自動配置配線に用いる従来の機能ブロックは、図
3に示すように矩形領域である機能ブロック枠1Aの上
辺と底辺に、その一部を素子電極と同じメタル配線層に
よって形成した電源配線VCCと接地配線GNDを有し
ている。これらの配線の両端にはそれぞれ外部端子11
〜14が設けられる。また、機能ブロック内のレイアウ
ト設計は、所望の回路素子に応じたトランジスタQ1〜
Q6や、抵抗R1〜R4等を選択し、予め定められた機
能ブロック枠1Aの矩形領域に収まるように各素子の配
置と、素子配線2による配線を行っている。なお、この
機能ブロックで構成される回路の等価回路を図2に示
す。
2. Description of the Related Art In recent large-scale analog integrated circuits, in order to shorten the design period and standardize the design, several tens of circuit elements are set as one functional block unit, and the layout and wiring of each functional block is performed by a computer. Is going. As shown in FIG. 3, the conventional functional block used for such automatic placement / wiring is a power supply wiring in which a part of the functional block frame 1A, which is a rectangular area, is formed by the same metal wiring layer as the element electrodes on the top and bottom sides. It has a VCC and a ground wiring GND. External terminals 11 are provided on both ends of these wirings, respectively.
~ 14 are provided. In addition, the layout design in the functional block is performed by selecting the transistors Q1 to Q1 according to the desired circuit element.
Q6, resistors R1 to R4, etc. are selected, and each element is arranged so that it fits within a predetermined rectangular area of the functional block frame 1A and wiring by the element wiring 2 is performed. An equivalent circuit of a circuit composed of this functional block is shown in FIG.

【0003】[0003]

【発明が解決しようとする課題】このような従来の半導
体集積回路装置では、カレントミラー回路を構成してい
るトランジスタQ1とトランジスタQ2のエミッタ配線
が電源配線に対し共通インピーダンスを持つように接続
されているが、各エミッタ配線がそれぞれ個別に電源配
線GNDの異なる位置に接続されているため、この機能
ブロックに対して他の機能ブロックを接続したような場
合に、他の機能ブロックの電流によって各エミッタ配線
の電流に差が生じ、素子間の整合が劣化されることがあ
る。
In such a conventional semiconductor integrated circuit device, the emitter wirings of the transistors Q1 and Q2 forming the current mirror circuit are connected so as to have a common impedance with respect to the power supply wiring. However, since each emitter wiring is individually connected to a different position of the power supply wiring GND, when another functional block is connected to this functional block, each emitter is caused by the current of the other functional block. There may be a difference in the current of the wiring, which may deteriorate the matching between the elements.

【0004】また、図4のように複数個の機能ブロック
A〜Gを配列して電源配線VCCと接地配線GNDを接
続した半導体集積回路装置10を構成した場合、各機能
ブロック列に流し得る回路電流の合計値はボンディング
パッドPDに最も近い機能ブロックA,Dの配線幅で制
限される。このため、機能ブロックA,Dで接地配線の
電流容量が不足する場合には、図3における接地配線1
2の配線の最小幅(この例では接地配線GNDを中間で
スルーホール4により接続している2層配線3の幅)を
広げる等の設計の変更が必要とされ、或いは機能ブロッ
クAの接地配線GNDのように単独でボンディングパッ
ド近傍まで配線することになり、配線領域が増大する要
因になっていた。本発明の目的は、機能ブロック内の素
子間整合の劣化を防止し、かつ電源及び接地配線におけ
る配線領域の縮小を可能にした半導体集積回路装置を提
供することにある。
Further, when the semiconductor integrated circuit device 10 in which a plurality of functional blocks A to G are arranged to connect the power supply wiring VCC and the ground wiring GND as shown in FIG. The total current value is limited by the wiring width of the functional blocks A and D closest to the bonding pad PD. Therefore, when the current capacity of the ground wiring in the functional blocks A and D is insufficient, the ground wiring 1 in FIG.
It is necessary to change the design such as increasing the minimum width of the second wiring (in this example, the width of the two-layer wiring 3 in which the ground wiring GND is connected by the through hole 4 in the middle), or the ground wiring of the functional block A. As in the case of GND, wires are singly laid up to the vicinity of the bonding pad, which has been a factor of increasing the wiring area. An object of the present invention is to provide a semiconductor integrated circuit device capable of preventing deterioration of matching between elements in a functional block and reducing a wiring area of a power supply and a ground wiring.

【0005】[0005]

【課題を解決するための手段】本発明は、機能ブロック
の両側部に設ける電源配線と接地配線を任意の幅寸法の
直線形状に形成するとともに、機能ブロック内の素子を
接続する素子配線をこれら電源配線と接地配線の各1点
において接続した構成とする。
According to the present invention, the power supply wiring and the ground wiring provided on both sides of the functional block are formed in a linear shape having an arbitrary width dimension, and the element wiring for connecting the elements in the functional block are The power supply wiring and the ground wiring are connected at one point each.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例の機能ブロックの平面図、
図2はその等価回路図である。図1において、機能ブロ
ック枠1の矩形領域内にPNPトランジスタQ1,Q2
と、NPNトランジスタQ3〜Q6、及び抵抗体R1〜
R4を配置する。また、機能ブロック枠1の上下にはそ
れぞれ電源配線VCCと接地配線GNDを直線状に配設
する。そして、各素子は素子配線2により相互に接続さ
れて図2の等価回路を構成するが、この素子配線2に
は、電源配線VCCや接地配線GNDと同一のメタル配
線層が用いられる。なお、回路構成によっては2層メタ
ル配線が用いられる場合があり、この実施例でも一部を
2層配線3で構成している。また、前記電源配線VCC
と接地配線GNDの両端にはそれぞれ外部端子11,1
2と13,14が設けられる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a plan view of a functional block according to an embodiment of the present invention,
FIG. 2 is an equivalent circuit diagram thereof. In FIG. 1, PNP transistors Q1 and Q2 are provided in a rectangular area of the functional block frame 1.
And NPN transistors Q3 to Q6 and resistors R1 to R1.
Place R4. Further, a power supply line VCC and a ground line GND are linearly arranged above and below the functional block frame 1, respectively. The respective elements are connected to each other by the element wiring 2 to form the equivalent circuit of FIG. 2. The element wiring 2 uses the same metal wiring layer as the power wiring VCC and the ground wiring GND. Two-layer metal wiring may be used depending on the circuit configuration. In this embodiment, a part of the wiring is also composed of two-layer wiring 3. In addition, the power supply wiring VCC
And external terminals 11, 1 on both ends of the ground wire GND.
2 and 13, 14 are provided.

【0007】ここで、前記PNPトランジスタQ1,Q
2は図2の回路におけるカレントミラー回路を構成して
おり、各トランジスタQ1,Q2は隣接配置され、各々
のトランジスタのエミッタに接続される電源配線は抵抗
体R1の電源端と共に素子配線2で合一化され、その上
で電源配線VCCに対して外部端子11,12間の1点
で接続される。また、抵抗体R2〜R4の接地端も同一
の素子配線2で合一化され、スルーホール4と2層メタ
ル配線3を介して1点で接地配線GNDの外部端子1
3,14の間に接続される。
Here, the PNP transistors Q1 and Q
2 constitutes a current mirror circuit in the circuit of FIG. 2, the transistors Q1 and Q2 are arranged adjacent to each other, and the power source wiring connected to the emitter of each transistor is connected by the element wiring 2 together with the power source end of the resistor R1. They are unified and connected to the power supply wiring VCC at one point between the external terminals 11 and 12. Further, the ground ends of the resistors R2 to R4 are unified by the same element wiring 2, and the external terminal 1 of the ground wiring GND is connected at one point through the through hole 4 and the two-layer metal wiring 3.
It is connected between 3 and 14.

【0008】したがって、カレントミラー回路を構成す
るトランジスタQ1,Q2は、エミッタ配線が素子配線
2により一点で電源配線VCCに接続されるため、機能
ブロックの配置如何にかかわらず、他の機能ブロックの
電流による整合性が劣化されることはない。また、電源
配線VCCと接地配線GNDは直線形状をしているた
め、機能ブロックの外側に向けて配線幅を任意に広げる
ことが可能となり、電気容量等の配線設計が容易とな
る。
Therefore, in the transistors Q1 and Q2 forming the current mirror circuit, the emitter wiring is connected to the power supply wiring VCC at one point by the element wiring 2, so that the currents of other functional blocks are irrespective of the arrangement of the functional blocks. Does not degrade the integrity. Further, since the power supply wiring VCC and the ground wiring GND have a linear shape, it is possible to arbitrarily widen the wiring width toward the outside of the functional block, which facilitates wiring design such as electric capacitance.

【0009】[0009]

【発明の効果】以上説明したように本発明は、機能ブロ
ックの両側部に設ける電源配線と接地配線を任意の幅寸
法の直線形状に形成するとともに、機能ブロック内の素
子を接続する素子配線をこれら電源配線と接地配線の各
1点において接続しているので、他の機能ブロックの電
流による整合性の悪化が改善されると共に、電源配線と
接地配線の幅を機能ブロックの外側へ任意に拡張してそ
の容量が増大できるので、配線の設計が容易となり、機
能ブロックの流用性も高くなるという効果を得ることが
できる。
As described above, according to the present invention, the power supply wiring and the ground wiring provided on both sides of the functional block are formed in a linear shape having an arbitrary width dimension, and the element wiring for connecting the elements in the functional block is formed. Since the connection is made at each point of the power supply wiring and the ground wiring, the deterioration of the consistency due to the current of the other functional blocks is improved, and the widths of the power supply wiring and the ground wiring are arbitrarily extended to the outside of the functional block. Since the capacity can be increased, the wiring can be easily designed, and the function blocks can be used more effectively.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体集積回路装置の一実施例の機能
ブロック平面図である。
FIG. 1 is a functional block plan view of an embodiment of a semiconductor integrated circuit device of the present invention.

【図2】図1及び図3の回路の等価回路図である。FIG. 2 is an equivalent circuit diagram of the circuits of FIGS. 1 and 3.

【図3】従来の半導体集積回路装置の機能ブロックの平
面図である。
FIG. 3 is a plan view of functional blocks of a conventional semiconductor integrated circuit device.

【図4】従来の機能ブロックにより構成した半導体集積
回路装置の概略配置図である。
FIG. 4 is a schematic layout diagram of a semiconductor integrated circuit device configured by conventional functional blocks.

【符号の説明】[Explanation of symbols]

1 機能ブロック 2 素子配線 3 2層配線 4 スルーホール Q1〜Q6 トランジスタ R1〜R4 抵抗 VCC 電源配線 GND 接地配線 1 Functional Block 2 Element Wiring 3 2 Layer Wiring 4 Through Hole Q1 to Q6 Transistors R1 to R4 Resistance VCC Power Supply Wiring GND Ground Wiring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 機能ブロックの両側部に電源配線と接地
配線を有し、かつ機能ブロック内の素子を素子配線によ
り前記電源配線及び接地配線に接続してなる半導体集積
回路装置において、前記電源配線と接地配線を任意の幅
寸法の直線形状に形成するとともに、これら電源配線と
接地配線の各1点において前記素子配線を接続したこと
を特徴とする半導体集積回路装置。
1. A semiconductor integrated circuit device having power supply wiring and ground wiring on both sides of a functional block, wherein elements in the functional block are connected to the power supply wiring and the ground wiring by element wiring. A semiconductor integrated circuit device characterized in that the element wiring and the ground wiring are formed in a linear shape having an arbitrary width dimension, and the element wiring is connected at each one point of the power wiring and the ground wiring.
JP28344092A 1992-09-30 1992-09-30 Semiconductor integrated circuit device Expired - Fee Related JP3179211B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28344092A JP3179211B2 (en) 1992-09-30 1992-09-30 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28344092A JP3179211B2 (en) 1992-09-30 1992-09-30 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH06120223A true JPH06120223A (en) 1994-04-28
JP3179211B2 JP3179211B2 (en) 2001-06-25

Family

ID=17665574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28344092A Expired - Fee Related JP3179211B2 (en) 1992-09-30 1992-09-30 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP3179211B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08172175A (en) * 1994-12-19 1996-07-02 Fujitsu Ten Ltd Semiconductor integrated circuit
CN104241247A (en) * 2014-09-16 2014-12-24 格科微电子(上海)有限公司 Power source ground network and wire arrangement method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08172175A (en) * 1994-12-19 1996-07-02 Fujitsu Ten Ltd Semiconductor integrated circuit
CN104241247A (en) * 2014-09-16 2014-12-24 格科微电子(上海)有限公司 Power source ground network and wire arrangement method thereof

Also Published As

Publication number Publication date
JP3179211B2 (en) 2001-06-25

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