JP2005229018A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005229018A
JP2005229018A JP2004037867A JP2004037867A JP2005229018A JP 2005229018 A JP2005229018 A JP 2005229018A JP 2004037867 A JP2004037867 A JP 2004037867A JP 2004037867 A JP2004037867 A JP 2004037867A JP 2005229018 A JP2005229018 A JP 2005229018A
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control circuit
power transistor
semiconductor device
semiconductor chip
semiconductor
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Takao Kanzaki
廷夫 勘崎
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a power supply apparatus using the semiconductor device, wherein the device so reduces its characteristic variations caused by its temperature gradient as to be able to prevent nonconformities. <P>SOLUTION: The semiconductor device 1 has a semiconductor chip 10, wherein a power transistor 11 and a control circuit 12 for controlling the power transistor 11 are turned into an single-chip state. The power transistor 11 is disposed in the central portion of the semiconductor chip 10, and the control circuit 12 is disposed at the periphery of the power transistor 11. Consequently, the distance between the peripheral edge 11a of the power transistor 11 and the peripheral edge 12a of the control circuit 12, and the distance between the peripheral edge 11b of the power transistor 11 and the peripheral edge 12b of the control circuit 12 become short respectively, and the temperature difference of the inside of the control circuit 12, which is caused by the temperature gradient generated in the control circuit 12 by the heat generation of the power transistor 11, is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、パワートランジスタ等の発熱素子が設けられた半導体チップを有する半導体装置及びそれを用いた電源装置に関する。   The present invention relates to a semiconductor device having a semiconductor chip provided with a heating element such as a power transistor, and a power supply device using the semiconductor device.

電源装置等に用いられる半導体装置は半導体チップを有している。図７は従来の半導体装置の半導体チップを示す平面図である。半導体チップ１０はパワートランジスタ１１と制御回路１２とを並設してワンチップ化されている。パワートランジスタ１１はスイッチング電源回路においてはスイッチング等を行ない、制御回路１２はそのパワートランジスタ１１を制御する。   A semiconductor device used for a power supply device or the like has a semiconductor chip. FIG. 7 is a plan view showing a semiconductor chip of a conventional semiconductor device. The semiconductor chip 10 is formed as a single chip by arranging a power transistor 11 and a control circuit 12 in parallel. The power transistor 11 performs switching or the like in the switching power supply circuit, and the control circuit 12 controls the power transistor 11.

パワートランジスタ１１及び制御回路１２にはパッド部１３が形成されている。パッド部１３とリードフレーム（不図示）とをワイヤー（不図示）により接続した後、リードフレームが外部に突出するように全体を樹脂によりモールドし、半導体装置が構成されている。
特開２０００−１２４４３３号公報 A pad portion 13 is formed in the power transistor 11 and the control circuit 12. After the pad portion 13 and the lead frame (not shown) are connected by a wire (not shown), the whole is molded with resin so that the lead frame protrudes to the outside, and the semiconductor device is configured.
JP 2000-124433 A

ここ数年来、携帯電話機等に使用されている小型パッケージの小電力出力（出力電流２００ｍＡ以下）の直流安定化電源ＩＣでは、熱源となるパワートランジスタに流れる電流は少ないためにパワートランジスタから発生する熱量は少ない。従って、パワートランジスタをＩＣチップの端に配置しても、ＩＣチップの温度勾配は無い。よって、チップ内の温度勾配が原因となって、制御回路内の抵抗やコンデンサ等の値が変移したり、トランジスタの整合性が崩れたりして制御回路が正常に動作しなくなるという不具合は起こらなかった。   In recent years, in a DC stabilized power supply IC with a small power output (output current of 200 mA or less) in a small package used for mobile phones and the like, the amount of heat generated from the power transistor is small because the current flowing through the power transistor as a heat source is small. There are few. Therefore, even if the power transistor is arranged at the end of the IC chip, there is no temperature gradient of the IC chip. Therefore, there is no problem that the control circuit does not operate normally due to the temperature gradient in the chip causing the value of resistors, capacitors, etc. in the control circuit to change or the transistor consistency to be lost. It was.

しかしながら、近年では出力電流が５００ｍＡ以上の中電流もしくは大電流の直流安定化電源が強く要求されている。なお、トランジスタの整合性が崩れるというのは、ベース・エミッタ間の閾値電圧が加熱により変移して、例えばカレントミラー回路を成す一対のトランジスタの動作電圧がそれぞれ相違してしまったりすることが挙げられる。   However, in recent years, there has been a strong demand for a DC stabilized power supply with an output current of 500 mA or more and a medium or large current. Note that the transistor matching is lost because the threshold voltage between the base and the emitter is changed by heating, for example, the operating voltages of a pair of transistors forming a current mirror circuit are different from each other. .

図８の直流安定化電源回路において、１００は直流電圧の入力端子、１１はＰＮＰ型のパワートランジスタ、Ｑ３はドライブトランジスタである。ドライブトランジスタＱ３はパワートランジスタ１１のベースにコレクタが接続され、エミッタが抵抗Ｒ６を介してグランドに接続される。   In the DC stabilized power supply circuit of FIG. 8, reference numeral 100 is a DC voltage input terminal, 11 is a PNP type power transistor, and Q3 is a drive transistor. The drive transistor Q3 has a collector connected to the base of the power transistor 11, and an emitter connected to the ground via a resistor R6.

Ｑ１、Ｑ２はエミッタが定電流源１０３に接続された差動対トランジスタである。トランジスタＱ２のベースには出力端子１０２の出力電圧を抵抗Ｒ１、Ｒ２で分圧した電圧が印加される。一方、トランジスタＱ１のベースには直流電圧Ｖを抵抗Ｒ５、Ｒ４で分圧した電圧が基準電圧として印加される。尚、抵抗Ｒ５はコンデンサＣと共にノイズ除去用フィルタを構成している。トランジスタＱ１のコレクタは抵抗Ｒ３を通して直流電圧Ｖｃｃに接続され、トランジスタＱ２のコレクタはダイレクトに直流電圧Ｖｃｃに接続されている。   Q1 and Q2 are differential pair transistors whose emitters are connected to the constant current source 103. A voltage obtained by dividing the output voltage of the output terminal 102 by the resistors R1 and R2 is applied to the base of the transistor Q2. On the other hand, a voltage obtained by dividing the DC voltage V by the resistors R5 and R4 is applied as a reference voltage to the base of the transistor Q1. The resistor R5 and the capacitor C constitute a noise removal filter. The collector of transistor Q1 is connected to DC voltage Vcc through resistor R3, and the collector of transistor Q2 is directly connected to DC voltage Vcc.

ここで、パワートランジスタの発熱に基づく抵抗Ｒ１、Ｒ２の抵抗値変移と抵抗Ｒ４，Ｒ５の抵抗値変移とが或る程度以上相違すると、差動増幅回路がバランスを崩し、制御回路１２が正常に動作できなくなる。同じことはパワートランジスタ１１の発熱によるトランジスタＱ１、Ｑ２に対する加熱度合が相違する場合にも生じる。パワートランジスタ１１によるトランジスタＱ１、Ｑ２の閾値電圧（ベース・エミッタ間導通電圧）が互いに相違してしまうからである。また、コンデンサとしては同図では１つのコンデンサＣだけしか示していないが、いろいろなところにコンデンサが用いられるので、これらのコンデンサの容量値変移によっても制御回路が正常に動作しないことになる。   Here, if the resistance value change of the resistors R1 and R2 and the resistance value change of the resistors R4 and R5 due to the heat generation of the power transistor are different from each other to some extent, the differential amplifier circuit is out of balance and the control circuit 12 becomes normal. It becomes impossible to operate. The same thing occurs when the degrees of heating of the transistors Q1 and Q2 due to the heat generated by the power transistor 11 are different. This is because the threshold voltages (base-emitter conduction voltages) of the transistors Q1 and Q2 due to the power transistor 11 are different from each other. Further, although only one capacitor C is shown in the figure as the capacitor, since the capacitors are used in various places, the control circuit does not operate normally even if the capacitance values of these capacitors change.

尚、大電流の電源が要求されるようになってきた背景には、中電流もしくは大電流の直流安定化電源が使用される据え置き型のＣＤ−ＲＯＭやＤＶＤ−ＲＯＭ装置が多く開発されているということがある。これらの中電流もしくは大電流の直流安定化電源は熱源となるパワートランジスタにより多くの電流が流れるために発生する熱量は多くなり、熱源がＩＣチップの端に配置されていると、ＩＣチップ内に無視できない温度勾配が生じてしまう。   Incidentally, a background of the demand for a high-current power supply has been developed many stationary CD-ROM and DVD-ROM devices using a medium-current or high-current DC stabilized power supply. There is. These medium-current or large-current DC-stabilized power supplies generate a large amount of heat because a large amount of current flows through the power transistor serving as a heat source. If the heat source is arranged at the end of the IC chip, A temperature gradient that cannot be ignored occurs.

この結果、上述したように個々の抵抗、コンデンサが所望の値からずれたり、トランジスタの整合性が崩れたりして、制御回路が正常に動作しなくなるという不具合を生じてしまう。このことは、特にアナログの回路で懸念されることであり、熱源と制御回路がワンチップ化されているアナログ回路の半導体装置においては温度勾配に対する対策が不可欠であるといえる。   As a result, as described above, the individual resistors and capacitors are deviated from desired values, or the matching of the transistors is lost, causing a problem that the control circuit does not operate normally. This is particularly a concern for analog circuits, and it can be said that measures against temperature gradients are indispensable in an analog circuit semiconductor device in which a heat source and a control circuit are integrated into a single chip.

本発明は温度勾配による特性変動を低減し、不具合を防止できる半導体装置及びそれを用いた電源装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor device capable of reducing characteristic fluctuations due to a temperature gradient and preventing problems and a power supply device using the same.

上記目的を達成するために本発明の半導体装置は、発熱素子と、前記発熱素子を制御する制御回路とを内蔵した半導体チップを備え、前記発熱素子を前記半導体チップの中央部付近に配置するとともに、前記制御回路を前記発熱素子の周囲に配置したことを特徴としている。この構成によると、パワートランジスタ等の発熱素子の発熱によって制御回路には発熱素子の周縁から半導体チップの周縁に至る温度勾配が形成される。   In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor chip that incorporates a heating element and a control circuit that controls the heating element, and the heating element is arranged near the center of the semiconductor chip. The control circuit is arranged around the heating element. According to this configuration, a temperature gradient from the periphery of the heating element to the periphery of the semiconductor chip is formed in the control circuit by the heat generation of the heating element such as the power transistor.

また、本発明の半導体装置は、発熱素子と、前記発熱素子を制御する制御回路とを内蔵した半導体チップを備え、前記制御回路を前記半導体チップの中央部付近に配置するとともに、前記発熱素子を前記制御回路の周囲に配置したことを特徴としている。この構成によると、発熱素子の発熱によって制御回路には内周縁から制御回路の略中心に至る温度勾配が形成される。   The semiconductor device of the present invention includes a semiconductor chip including a heating element and a control circuit for controlling the heating element, the control circuit is disposed near the center of the semiconductor chip, and the heating element is provided. It is arranged around the control circuit. According to this configuration, a temperature gradient from the inner peripheral edge to the approximate center of the control circuit is formed in the control circuit due to the heat generated by the heating element.

また、本発明は、上記構成の半導体装置において、前記発熱素子は分割した複数の素子部から成ることを特徴としている。この構成によると、制御回路の周囲に複数の素子部が配置される。素子部は均等に配置することが望ましい。   According to the present invention, in the semiconductor device configured as described above, the heat generating element includes a plurality of divided element portions. According to this configuration, the plurality of element units are arranged around the control circuit. It is desirable to arrange the element portions evenly.

また、本発明は、対向配置した前記素子部の間に前記制御回路を配置したことを特徴としている。この構成によると、発熱素子の発熱によって制御回路には対向する発熱素子の両端縁から両発熱素子の略中点に至る温度勾配が形成される。複数の素子部を接続するワイヤーまたは半導体チップ上の配線パターンを設けるとよい。   In addition, the present invention is characterized in that the control circuit is arranged between the element portions arranged to face each other. According to this configuration, a temperature gradient is formed in the control circuit by the heat generation of the heat generating elements from both end edges of the opposing heat generating elements to the substantially middle point of both heat generating elements. A wire connecting a plurality of element portions or a wiring pattern on a semiconductor chip may be provided.

また、本発明の電源装置は上記構成の半導体装置を備えたことを特徴としている。この構成によると、半導体装置には整流器や変圧器等が形成され、半導体装置に入力電圧を所定の電圧に変換して出力する。   In addition, a power supply device of the present invention includes the semiconductor device having the above-described configuration. According to this configuration, a rectifier, a transformer, and the like are formed in the semiconductor device, and an input voltage is converted into a predetermined voltage and output to the semiconductor device.

本発明によると、発熱素子を半導体チップの中央部に配置して制御回路を発熱素子の周囲に配置したので、制御回路が配される発熱素子の周縁から制御回路の周縁までの距離を短縮することができる。このため、制御回路は発熱素子に近い位置と遠い位置との間の温度差が小さくなり、制御回路の温度勾配が減少して特性変動が低減されることにより制御回路が温度勾配の影響を受けて誤動作するという不具合を防止することができる。   According to the present invention, since the heating element is arranged in the center of the semiconductor chip and the control circuit is arranged around the heating element, the distance from the periphery of the heating element where the control circuit is arranged to the periphery of the control circuit is shortened. be able to. For this reason, the temperature difference between the position near the heating element and the position far from the heating element becomes small in the control circuit, the temperature gradient of the control circuit is reduced, and the characteristic fluctuation is reduced, so that the control circuit is affected by the temperature gradient. Malfunction can be prevented.

また、本発明によると、制御回路を前記半導体チップの中央部に配置するとともに、前記発熱素子を制御回路の周囲に配置したので、制御回路が配される発熱素子の内周縁から制御回路の略中心までの距離を短縮することができる。これにより、制御回路の温度勾配を減少させることができる。   In addition, according to the present invention, the control circuit is arranged at the center of the semiconductor chip, and the heating element is arranged around the control circuit, so that the control circuit is abbreviated from the inner periphery of the heating element to which the control circuit is arranged. The distance to the center can be shortened. Thereby, the temperature gradient of the control circuit can be reduced.

また、本発明によると、発熱素子を分割した複数の素子部を制御回路の周囲に配置したので、各素子部から制御回路の略中心までの距離を短縮することができる。これにより制御回路の温度勾配が減少して特性変動が低減するので、制御回路が温度勾配の影響を受けて誤動作するという不具合を防止することができる。また、発熱素子を効率的に使用して小さくできるため、半導体装置の小型化を図ることもできる。   In addition, according to the present invention, since the plurality of element portions obtained by dividing the heating element are arranged around the control circuit, the distance from each element portion to the approximate center of the control circuit can be shortened. As a result, the temperature gradient of the control circuit is reduced and the characteristic variation is reduced, so that it is possible to prevent a malfunction that the control circuit malfunctions due to the influence of the temperature gradient. Further, since the heat generating element can be efficiently used and reduced, the semiconductor device can be reduced in size.

以下に本発明の実施形態を図面を参照して説明する。図１は第１実施形態の半導体装置を示す平面図である。説明の便宜上、前述の図７に示す従来例と同一の部分は同一の符号を付している。この半導体装置１では、リードフレーム６のランド部２上に半導体チップ１０が載置され、銀ペースト３を介してランド部２に接続固定される。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing the semiconductor device of the first embodiment. For convenience of explanation, the same parts as those of the conventional example shown in FIG. In this semiconductor device 1, the semiconductor chip 10 is placed on the land portion 2 of the lead frame 6 and connected and fixed to the land portion 2 via the silver paste 3.

半導体チップ１０上にはパッド部１３が形成されており、そのパッド部１３はボンディングワイヤー４によりリードフレーム７に接続されている。そして、各リードフレーム６、７の一部が外部に突出する形で全体が樹脂によりモールドされ、パッケージ化されている。   A pad portion 13 is formed on the semiconductor chip 10, and the pad portion 13 is connected to the lead frame 7 by a bonding wire 4. The entire lead frames 6 and 7 are molded with resin so that a part of the lead frames 6 and 7 protrudes to the outside.

半導体チップ１０は図２に示すように、中央部にパワートランジスタ１１（発熱素子）が配置され、パワートランジスタ１１の周囲に制御回路１２が配置されている。この制御回路１２は図８の直流安定化回路の場合はパワートランジスタ１１の導通度を制御し、スイッチング電源回路（図示せず）の場合はパワートランジスタ１１のスイッチングを制御するものであって、抵抗やコンデンサ、トランジスタ等から成っている。なお、スイッチング電源回路の場合、制御回路の回路構成は図８とは異なる。   As shown in FIG. 2, the semiconductor chip 10 has a power transistor 11 (heat generating element) disposed in the center, and a control circuit 12 disposed around the power transistor 11. The control circuit 12 controls the continuity of the power transistor 11 in the case of the DC stabilizing circuit of FIG. 8, and controls the switching of the power transistor 11 in the case of a switching power supply circuit (not shown). And capacitors, transistors, etc. In the case of a switching power supply circuit, the circuit configuration of the control circuit is different from that in FIG.

上記のように構成された半導体装置１は大電流の直流安定化電源用ＩＣを構成し、入力電圧を所定の電圧に変換して出力することができる。   The semiconductor device 1 configured as described above constitutes a DC stabilized power supply IC with a large current, and can convert an input voltage into a predetermined voltage and output it.

本実施形態によると、発熱を伴うパワートランジスタ１１を半導体チップ１０の中央部に配置して制御回路１２をパワートランジスタ１１の周囲に配置したので、パワートランジスタ１１の周縁１１ａ、１１ｂから制御回路１２の周縁１２ａ、１２ｂまでの最大距離を前述の図７に示す従来例に比して短縮することができる。   According to the present embodiment, the power transistor 11 that generates heat is disposed in the central portion of the semiconductor chip 10 and the control circuit 12 is disposed around the power transistor 11, so that the control circuit 12 is connected to the peripheral edges 11 a and 11 b of the power transistor 11. The maximum distance to the peripheral edges 12a and 12b can be shortened as compared with the conventional example shown in FIG.

このため、制御回路１２はパワートランジスタ１１に近い位置（１１ａ、１１ｂ）と遠い位置（１２ａ、１２ｂ）との間に生じる温度勾配による温度差が小さくなる。これにより、制御回路１２に設けられた前記近い位置の抵抗の抵抗値やコンデンサの容量値が温度によって所望の値からずれる量と前記遠い位置の抵抗の抵抗値やコンデンサの容量値が温度によって所望の値からずれる量との差が小さくなる。   For this reason, in the control circuit 12, a temperature difference due to a temperature gradient generated between a position (11a, 11b) close to the power transistor 11 and a position (12a, 12b) far from the power transistor 11 becomes small. As a result, the resistance value of the near-position resistor or the capacitance value of the capacitor provided in the control circuit 12 is deviated from a desired value depending on the temperature, and the resistance value of the resistor or the capacitor value of the far-position is desired depending on the temperature. The difference from the amount deviating from the value of becomes smaller.

従って、近い位置と遠い位置に配置された抵抗間の整合性が崩れず、同様にコンデンサの整合性も崩れない。また、制御回路内のトランジスタの整合性も損なわれない。このように、本実施形態では制御回路１２内の温度勾配による特性変動を低減し、制御回路１２が正常に動作しない不具合の発生を防止することができる。   Therefore, the matching between the resistors arranged at the near position and the far position does not break, and the matching of the capacitor does not break. Further, the consistency of the transistors in the control circuit is not impaired. As described above, in this embodiment, the characteristic variation due to the temperature gradient in the control circuit 12 can be reduced, and the occurrence of the malfunction that the control circuit 12 does not operate normally can be prevented.

次に、図３は第２実施形態の半導体装置の半導体チップを示す平面図である。説明の便宜上、前述の図１、図２に示す第１実施形態と同一の部分は同一の符号を付している。本実施形態の半導体チップ１０は中央部に制御回路１２が配置され、制御回路１２の周囲にパワートランジスタ１１が配置されている。その他の構成は第１実施形態と同様である。   Next, FIG. 3 is a plan view showing a semiconductor chip of the semiconductor device of the second embodiment. For convenience of explanation, the same parts as those in the first embodiment shown in FIGS. 1 and 2 are given the same reference numerals. In the semiconductor chip 10 of the present embodiment, a control circuit 12 is disposed at the center, and a power transistor 11 is disposed around the control circuit 12. Other configurations are the same as those of the first embodiment.

本実施形態によると、パワートランジスタ１１の内周縁１１ｃ、１１ｄから制御回路１２の略中心までの距離を短縮することができる。このため、制御回路１２はパワートランジスタ１１に近い位置（１１ｃ、１１ｄ）と遠い位置（略中心）との間に形成される温度勾配による温度差が小さくなる。従って、第１実施形態と同様の効果を得ることができる。   According to this embodiment, the distance from the inner peripheral edges 11 c and 11 d of the power transistor 11 to the approximate center of the control circuit 12 can be shortened. For this reason, in the control circuit 12, the temperature difference due to the temperature gradient formed between the position (11c, 11d) close to the power transistor 11 and the position (substantially center) is small. Therefore, the same effect as the first embodiment can be obtained.

次に、図４は第３実施形態の半導体装置の半導体チップを示す平面図である。説明の便宜上、前述の図１、図２に示す第１実施形態と同一の部分は同一の符号を付している。本実施形態の半導体チップ１０はパワートランジスタ１１を分割した第１、第２素子部１１ｅ、１１ｆが対向配置され、第１、第２素子部１１ｅ、１１ｆの間に制御回路１２が配置されている。   Next, FIG. 4 is a plan view showing a semiconductor chip of the semiconductor device of the third embodiment. For convenience of explanation, the same parts as those in the first embodiment shown in FIGS. 1 and 2 are given the same reference numerals. In the semiconductor chip 10 of the present embodiment, first and second element portions 11e and 11f obtained by dividing the power transistor 11 are arranged to face each other, and a control circuit 12 is arranged between the first and second element portions 11e and 11f. .

また、図５に示すように、第１、第２素子部１１ｅ、１１ｆにそれぞれ設けられたパッド部１３ａ、１３ｂがリードフレーム７の内端部７ａを介してワイヤー４ａ、４ｂにより接続されている。これにより、分割されたパワートランジスタ１１が電気的には一体化されていることになる。その他の構成は第１実施形態と同様である。   Further, as shown in FIG. 5, the pad portions 13 a and 13 b provided in the first and second element portions 11 e and 11 f are connected by wires 4 a and 4 b via the inner end portion 7 a of the lead frame 7. . As a result, the divided power transistors 11 are electrically integrated. Other configurations are the same as those of the first embodiment.

本実施形態によると、第１、第２素子部１１ｅ、１１ｆの内側の端縁１１ｇ、１１ｈから制御部１２の略中心となる第１、第２素子部１１ｅ、１１ｆの中点までの距離を短縮することができる。このため、制御回路１２は第１、第２素子部１１ｅ、１１ｆに近い位置（１１ｇ、１１ｈ）と遠い位置（略中心）との間に形成される温度勾配による温度差が小さくなる。従って、第１実施形態と同様の効果を得ることができる。   According to this embodiment, the distance from the inner edges 11g and 11h of the first and second element portions 11e and 11f to the midpoint of the first and second element portions 11e and 11f that are substantially the center of the control unit 12 is set. It can be shortened. For this reason, in the control circuit 12, the temperature difference due to the temperature gradient formed between the position (11g, 11h) close to the first and second element portions 11e, 11f and the position (substantially the center) is small. Therefore, the same effect as the first embodiment can be obtained.

また、第１、第２素子部１１ｅ、１１ｆにパワートランジスタ１１を分割配置することによって各素子に流れる電流の電流密度がより均一になり、パワートランジスタ１１を効率よく使用することができるためパワートランジスタ１１をより小さく形成する（面積を小さくする）ことができ、全体としての熱源の面積もより小さくできる。これに対し、パワートランジスタの面積が大きいと、パッド部からパワートランジスタ全体へのメタル配線が長くなるためパッド部から離れたトランジスタはパッド部近傍のトランジスタよりもパワートランジスタに流れる電流Ｉとメタル配線の抵抗Ｒによる電位勾配Ｉ×Ｒが大きくなり、特性が低下する。また、本実施形態では、熱源を分割し、各々の熱源の面積を小さくすることによって熱源内の電位勾配も低減することができる。このことによっても熱源をより効率よく使用できる。   Further, by arranging the power transistor 11 in the first and second element portions 11e and 11f, the current density of the current flowing through each element becomes more uniform, and the power transistor 11 can be used efficiently. 11 can be formed smaller (the area can be reduced), and the area of the heat source as a whole can also be reduced. On the other hand, if the area of the power transistor is large, the metal wiring from the pad portion to the entire power transistor becomes long. The potential gradient I × R due to the resistor R increases, and the characteristics deteriorate. In this embodiment, the potential gradient in the heat source can also be reduced by dividing the heat source and reducing the area of each heat source. This also makes it possible to use the heat source more efficiently.

更に、パワートランジスタ１１（従って熱源）の分割によってパワートランジスタに流れる電流の電流密度がより均一になり、パワートランジスタ、第１、第２素子部１１ｅ、１１ｆ内に設けられている電圧降下を低減してパワートランジスタ１１の特性低下を防止し、パワートランジスタ１１を効率よく使用してパワートランジスタ１１の面積を小さくすることができる。従って、その分、更に発熱量が減少して温度勾配による特性変動をより低減し、制御回路が正常に動作しない不具合を防止できる。   Further, the current density of the current flowing through the power transistor is made more uniform by dividing the power transistor 11 (and hence the heat source), and the voltage drop provided in the power transistor, the first and second element portions 11e and 11f is reduced. Thus, the characteristics of the power transistor 11 can be prevented from being deteriorated, and the area of the power transistor 11 can be reduced by using the power transistor 11 efficiently. Accordingly, the amount of heat generation is further reduced, and the characteristic fluctuation due to the temperature gradient is further reduced, so that the malfunction of the control circuit not operating normally can be prevented.

次に、図６は第４実施形態の半導体装置の半導体チップを示す平面図である。説明の便宜上、前述の図４、図５に示す第３実施形態と同一部分は同一の符号を付している。第３実施形態と本実施形態の異なる点は、半導体チップ１０は第１、第２素子部１１ｅ、１１ｆに設けられたパッド部１３ａ、１３ｂが半導体チップ１０上に形成された配線パターン１４より接続されている。これより、分割されたパワートランジスタ１１が電気的に一体化され、第３実施形態と同様の効果を得ることができる。   Next, FIG. 6 is a plan view showing a semiconductor chip of the semiconductor device of the fourth embodiment. For convenience of explanation, the same parts as those in the third embodiment shown in FIGS. 4 and 5 are given the same reference numerals. The difference between the third embodiment and the present embodiment is that the semiconductor chip 10 is connected by the wiring pattern 14 in which the pad portions 13a and 13b provided in the first and second element portions 11e and 11f are formed on the semiconductor chip 10. Has been. Thus, the divided power transistors 11 are electrically integrated, and the same effect as that of the third embodiment can be obtained.

第３、第４実施形態において、パワートランジスタ１１をより多くの素子部に分割してもよい。これにより、各素子部に流れる電流の電流密度をより均一にすることができる。また、複数の各素子部を制御回路１２の周囲に均等に配置すると、制御回路１２の温度勾配を最も小さくすることができる。   In the third and fourth embodiments, the power transistor 11 may be divided into more element portions. Thereby, the current density of the current flowing through each element portion can be made more uniform. Further, when the plurality of element portions are evenly arranged around the control circuit 12, the temperature gradient of the control circuit 12 can be minimized.

なお、第１〜第４実施形態において、半導体装置１０は直流安定化電源用ＩＣを構成しているが、パワートランジスタやロジックＩＣ等の発熱素子と制御回路とをワンチップ化した半導体チップを有する他の目的の半導体装置においても同様の効果を得ることができる。   In the first to fourth embodiments, the semiconductor device 10 constitutes a DC stabilized power supply IC. However, the semiconductor device 10 has a semiconductor chip in which a heating element such as a power transistor or a logic IC and a control circuit are integrated into one chip. Similar effects can be obtained in semiconductor devices for other purposes.

本発明は比較的大電流を要するＤＶＤ−ＲＯＭやＣＤ−ＲＯＭ等の装置の電源用半導体装置として利用可能である。   The present invention can be used as a power supply semiconductor device for a device such as a DVD-ROM or a CD-ROM that requires a relatively large current.

本発明の第１実施形態の半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. 本発明の第１実施形態の半導体装置の半導体チップを示す平面図である。It is a top view which shows the semiconductor chip of the semiconductor device of 1st Embodiment of this invention. 本発明の第２実施形態の半導体装置の半導体チップを示す平面図である。It is a top view which shows the semiconductor chip of the semiconductor device of 2nd Embodiment of this invention. 本発明の第３実施形態の半導体装置の半導体チップを示す平面図であるIt is a top view which shows the semiconductor chip of the semiconductor device of 3rd Embodiment of this invention. 本発明の第３実施形態の半導体装置を示す平面図であるIt is a top view which shows the semiconductor device of 3rd Embodiment of this invention. 本発明の第４実施形態の半導体装置の半導体チップを示す平面図であるIt is a top view which shows the semiconductor chip of the semiconductor device of 4th Embodiment of this invention. 従来の半導体装置の半導体チップを示す平面図であるIt is a top view which shows the semiconductor chip of the conventional semiconductor device. 半導体装置の半導体チップの内部の回路例を示す回路図であるIt is a circuit diagram showing an example of an internal circuit of a semiconductor chip of a semiconductor device

符号の説明Explanation of symbols

１ 半導体装置
３ 銀ペースト
４ ワイヤー
５ モールド樹脂
７ リードフレーム
１０ 半導体チップ
１１ パワートランジスタ
１１ｅ 第１素子部
１１ｆ 第２素子部
１２ 制御回路
１３、１３ａ、１３ｂ パッド部
１４ 配線パターン DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Silver paste 4 Wire 5 Mold resin 7 Lead frame 10 Semiconductor chip 11 Power transistor 11e 1st element part 11f 2nd element part 12 Control circuit 13, 13a, 13b Pad part 14 Wiring pattern

Claims (8)

発熱素子と、前記発熱素子を制御する制御回路とを内蔵した半導体チップを備え、前記発熱素子を前記半導体チップの中央部付近に配置するとともに、前記制御回路を前記発熱素子の周囲に配置したことを特徴とする半導体装置。   A semiconductor chip including a heat generating element and a control circuit for controlling the heat generating element is provided, the heat generating element is disposed near the center of the semiconductor chip, and the control circuit is disposed around the heat generating element. A semiconductor device characterized by the above. 発熱素子と、前記発熱素子を制御する制御回路とを内蔵した半導体チップを備え、前記制御回路を前記半導体チップの中央部付近に配置するとともに、前記発熱素子を前記制御回路の周囲に配置したことを特徴とする半導体装置。   A semiconductor chip including a heat generating element and a control circuit for controlling the heat generating element is provided, the control circuit is disposed near the center of the semiconductor chip, and the heat generating element is disposed around the control circuit. A semiconductor device characterized by the above. 前記発熱素子は分割した複数の素子部から成ることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the heat generating element includes a plurality of divided element portions. 複数の前記素子部を前記制御回路の周囲に均等に配置したことを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the plurality of element portions are arranged uniformly around the control circuit. 対向配置した前記素子部の間に前記制御回路を配置したことを特徴とする請求項３または請求項４に記載の半導体装置。   5. The semiconductor device according to claim 3, wherein the control circuit is arranged between the element portions arranged to face each other. 複数の前記素子部を接続するワイヤーを設けたことを特徴とする請求項３〜請求項５のいずれかに記載の半導体装置。   6. The semiconductor device according to claim 3, further comprising a wire for connecting a plurality of the element portions. 複数の前記素子部を接続する前記半導体チップの配線パターンを設けたことを特徴とする請求項３〜請求項５のいずれかに記載の半導体装置。   6. The semiconductor device according to claim 3, further comprising a wiring pattern of the semiconductor chip that connects a plurality of the element portions. 請求項１〜請求項７のいずれかに記載の半導体を備えたことを特徴とする電源装置。   A power supply device comprising the semiconductor according to claim 1.
JP2004037867A 2004-02-16 2004-02-16 Semiconductor device Pending JP2005229018A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888976B2 (en) 2008-05-12 2011-02-15 Denso Corporation Load-driving circuit having two transistors switched for heat dissipation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888976B2 (en) 2008-05-12 2011-02-15 Denso Corporation Load-driving circuit having two transistors switched for heat dissipation

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