JP3739091B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP3739091B2
JP3739091B2 JP2003099846A JP2003099846A JP3739091B2 JP 3739091 B2 JP3739091 B2 JP 3739091B2 JP 2003099846 A JP2003099846 A JP 2003099846A JP 2003099846 A JP2003099846 A JP 2003099846A JP 3739091 B2 JP3739091 B2 JP 3739091B2
Authority
JP
Japan
Prior art keywords
plate
fixing
electrode
lead terminal
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003099846A
Other languages
Japanese (ja)
Other versions
JP2004311539A (en
Inventor
正孝 難波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2003099846A priority Critical patent/JP3739091B2/en
Publication of JP2004311539A publication Critical patent/JP2004311539A/en
Application granted granted Critical
Publication of JP3739091B2 publication Critical patent/JP3739091B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/77—Apparatus for connecting with strap connectors
    • H01L2224/7725—Means for applying energy, e.g. heating means
    • H01L2224/77272—Oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842—Applying energy for connecting
    • H01L2224/8421—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/84214—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01054—Xenon [Xe]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置、特に半導体チップの電極とリード端子とを板状接続導体で接続した構造のパワーＭＯＳＦＥＴ、ＩＧＢＴ等の電力用の半導体装置の製造方法に関する。
【０００２】
【従来の技術】
近年、パワーＭＯＳＦＥＴまたはＩＧＢＴ等の電力用半導体装置の製造においては、製造コストの低減および接続導体の断線防止のために、高価な金線またはアルミニウム線によるワイヤボンディングの代わりに、Ｃｕ等からなる板状接続導体(以下、これをクリップと呼称する)を用いて半導体チップの電極とリード端子とを接続している。
【０００３】
この種の半導体装置の製造方法としては、図５に示すものが知られている（例えば、特許文献１参照。）。
【０００４】
この特許文献１に開示された半導体装置の製造方法は、図５に示すように、まず、先端部にベッド１０２が設けられた第１のリード端子１０１とこのベッド１０２に一方端部がそれぞれ近接配置された第２および第３のリード端子１０３、１０４とを有するリードフレーム１００を用意し、このリードフレーム１００の第１のリード端子１０１のベッド１０２上に、電極１１１、１１２を有する三端子型のダイオードからなる半導体チップ１１０を高融点半田にて固着する。
【０００５】
次に、半導体チップ１１０の電極１１１、１１２上、第２および第３のリード端子１０３、１０４の一方端部上にそれぞれ低融点半田を形成する。
【０００６】
次いで、第１のクリップ１２０を、その一方端部が低融点半田を形成した第２のリード端子１０３の一方端部上に、その他方端部が低融点半田を形成した電極１１１上に位置するように載置する。これと同様に、第２のクリップ１２１を、その一方端部が第３のリード端子１０４の一方端部上に、その他方端部が電極１１２上に載置する。
【０００７】
次に、これを加熱炉、加熱装置等の固着装置まで搬送し、その固着装置において、第１のクリップ１２０の一方端部を第２のリード端子１０３に、その他方端部を電極１１１にそれぞれ半田を介して固着・接続する。また、これと同様に、第２のクリップ１２１の一方端部を第３のリード端子１０４の一方端部に、その他方端部を電極１１２にそれぞれ半田を介して固着・接続している。
【０００８】
【特許文献１】
特開平８−１４８６２３号公報（３頁−４頁、図２）
【０００９】
【発明が解決しようとする課題】
上述した半導体装置の製造方法おいては、クリップを載置する工程と、クリップを電極およびリード端子に固着する工程とが異なるため、載置する工程と固着する工程の間に搬送する工程が介在する。従って、搬送時の振動または他の製造装置との接触等により、いわゆるクリップの位置ズレが発生し、半導体装置の信頼性の低下や組立て工程の歩留の低下が生じ、特に、複雑な構造や、平面でなく段差を有するクリップの場合には、特にその傾向が顕著であるという問題を有している。
【００１０】
本発明は、上記問題に鑑みてなされたもので、その目的とするところは、半導体装置の信頼性および組立て工程の歩留の向上を図ることが可能な半導体装置の製造方法を提供することにある。
【００１１】
【課題を解決するための手段】
上記目的を解決するために、本発明の半導体装置の一態様の製造方法は、複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、この載置工程において、レーザ光を前記板状接続導体の端部に照射することにより前記板状接続導体を前記リード端子および前記電極にそれぞれ固着する工程とを具備することを特徴とする。
また、本発明の半導体装置の一態様の製造方法は、複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、この載置工程において、ランプ光を前記板状接続導体の端部に照射することにより前記板状接続導体を前記リード端子および前記電極にそれぞれ固着する工程とを具備することを特徴とする。
また、本発明の半導体装置の一態様の製造方法は、複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、この載置工程において、レーザ光を前記板状接続導体の端部に照射することにより前記板状接続導体の両端部うちの少なくとも一方を仮固定する工程と、前記仮固定後、固着装置に搬送して、前記板状接続導体と前記リード端子および前記板状接続導体と前記電極をそれぞれ固着する工程とを具備することを特徴とする。
また、本発明の半導体装置の一態様の製造方法は、複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、この載置工程において、ランプ光を前記板状接続導体の端部に照射することにより前記板状接続導体の両端部うちの少なくとも一方を仮固定する工程と、前記仮固定後、固着装置に搬送して、前記板状接続導体と前記リード端子および前記板状接続導体と前記電極をそれぞれ固着する工程とを具備することを特徴とする。
【００１２】
【発明の実施の形態】
以下本発明の実施形態について図面を参照しながら説明する。
【００１３】
（第１の実施の形態）
まず、本発明の第１の実施の形態に係わる半導体装置の製造方法について、図１乃至３を参照して説明する。本実施の形態は、パワーＭＯＳＦＥＴを製造する場合の例である。
【００１４】
図１はパワーＭＯＳＦＥＴの製造工程を示す工程平面図、図２は図１（c）のＡ−Ａ線に沿う拡大断面図、図３は図１(d)のＢ−Ｂ線に沿う拡大断面図である。
【００１５】
図１(a)に示すように、まず、リードフレーム１０および半導体チップとしてパワーＭＯＳＦＥＴチップ２０を用意する。
【００１６】
このリードフレーム１０は、その長手方向に沿う左右両縁部にサイドフレーム１１ａ、１１ｂを有し、この両サイドフレーム１１ａ、１１ｂのうちの一方のサイドフレーム１１ａには、第1のリード端子１２が内向きに突出するように一体的に形成されている。この第１のリード端子１２の先端部には、半導体チップを搭載するためのベッド１３が形成されている。また、他方のサイドフレーム１１ｂには、第２および第３のリード端子１４、１５が内向きに突出するように形成され、その先端部が第１のリード端子１２のベッド１３と近接して向合うように配置されている。
【００１７】
一方、パワーＭＯＳＦＥＴチップ２０は、その上面にソース電極２１およびゲート電極２２を、下面にドレイン電極をそれぞれ有する。
【００１８】
そして、このリードフレーム１０の第１のリード端子１２のベッド１３上に高融点半田を形成した後に、パワーＭＯＳＦＥＴチップ２０を搭載し、固着する。
【００１９】
なお、このパワーＭＯＳＦＥＴチップ２０とベッド１３との固着は、高融点半田の代わりにＢａＮｉ／ＡｕＧｅまたはＴｉ／ＡｕからなるメタルをパワーＭＯＳＦＥＴ２０下面に形成し、ベッド１３に固着させてもよい。
【００２０】
次に、図１(b)に示すように、パワーＭＯＳＦＥＴチップ２０のソース電極２１、ゲート電極２２上、第２および第３のリード端子１４、１５の一方端部上にそれぞれ導電性固着部材、例えば融点２１０℃以下の低融点半田２３ａ、２３ｂ、２３ｃ、２３ｄを形成する。この低融点半田としては、ＳｎＰｂ系、ＳｎＢｉ系、ＳｎＡｇＣｕＩｎ系、およびＳｎＺｎ系等の共晶半田のいずれでもよい。また、低融点半田の代わりに、半田バンプ、Ａｕバンプ、或いは金属、または導電性接着材を用いてもよい。
【００２１】
次いで、図１(c)に示すように、細長い方形状の板状接続導体、例えば銅（Ｃｕ）製の第１のクリップ３０を、その一方端部が第２のリード端子１４の低融点半田２３c上に、その他方端部がパワーＭＯＳＦＥＴチップ２０のソース電極２１の低融点半田２３a上に位置するように載置する。これと同様に、Ｃｕ製の第２のクリップ３１を、その一方端部が第３のリード端子１５の低融点半田２３d上に、その他方端部がパワーＭＯＳＦＥＴチップ２０のゲート電極２２の低融点半田２３b上に位置するように載置する。このクリップ３０，３１は、Ｃｕに限らず、Ａｌ(アルミニウム)、またはＣｕ合金箔で形成してもよい。
【００２２】
ここで、上記クリップ３０、３１の供給方法としては、例えば、予め所定形状に曲げ加工された複数のクリップ３０，３１を異なるパーツフィーダにそれぞれ投入し、各パーツフィーダからクリップを一旦１列状に排出し、さらに、この排出されたクリップを個々に吸着コレット等により吸着保持した状態で、所定位置に移送するといったものが適用できる。また、クリップ３０，３１の載置時には、画像処理装置で、クリップ３０，３１の載置状態を認識し、１回の移送毎に第１および第２のクリップ３０、３１の位置を設定し直すことも可能である。
【００２３】
続いて、低融点半田２３ａ、２３ｃ上に位置する第１のクリップ３０の両端部および低融点半田２３ｂ、２３ｄ上に位置する第２のクリップ３１の両端部に、それぞれレーザ光を照射することにより、第１のクリップ３０の端部と第２のリード端子および１４ソース電極２１間、第２のクリップ３１の端部と第３のリード端子１５およびゲート電極２２間の低融点半田２３ａ、２３ｂ、２３ｃ、２３ｄをそれぞれ溶融させ、クリップ３０、３１の一方端部と第２および第３のリード端子１４，１５、その他方端部とソースおよびゲート電極２１、２２との双方を合金化させることにより、それぞれ固着・接続する。
【００２４】
本実施の形態では、第１および第２のクリップ３０、３１を載置した後は、移動させることなく、その載置工程において、第1および第２のクリップ３０、３１を、第1および第2のリード端子１４、１５とソースおよびゲート電極２１、２２とに固着・接続しているので、クリップの位置ズレは発生する恐れがない。
【００２５】
なお、レーザ光の照射方法としては、図２に示すように、半導体レーザ（ＬＤ）を有するレーザ発生装置４０、レーザ発生装置４０から発生したレーザ光４１を誘導する多数本からなる光ファイバー４２、レーザ光４１を任意の場所に照射するためにレーザ光４１の進路を変更（４１a或いは４１b）させる反射ミラー４３からなるレーザ加熱装置を用いて、レーザ光４１ａ、４１ｂを照射する。また、レーザ光源としては、ＬＤの代わりにＹＡＧレーザ、エキシマレーザ、または炭酸ガスレーザ等を用いて間欠的にレーザ光を照射してもよい。
【００２６】
更に、この第１および第２のクリップ３０、３１を第1および第2のリード端子１４、１５とソースおよびゲート電極２１、２２とに固着・接続したリードフレーム１０を移送して、周知のモールド成形金型により、モールド樹脂５０でパワーＭＯＳＦＥＴチップ２０およびその周辺に覆う。
【００２７】
次いで、周知の打ち抜き金型により、第１乃至第３のリード端子１２、１４、１５の所定位置を切断する。以上のような方法により、図１(d)および図３に示すパワーＭＯＳＦＥＴ１が製造される。
【００２８】
本実施の形態のパワーＭＯＳＦＥＴの製造方法では、第１および第２のクリップ３０、３１を、ソース電極２１の低融点半田２３aと第２のリード端子１４の低融点半田２３c上、およびゲート電極２２の低融点半田２３bと第３のリード端子１５の低融点半田２３d上にそれぞれ載置した後、フレーム１０を移動させることなく載置した場所で、レーザ光を照射させて第１および第２のクリップ３０、３１を固着・接続させているので、クリップの位置ズレが発生する恐れがない。
【００２９】
従って、半導体装置の信頼性および組立て工程の歩留の向上が図れる。
【００３０】
（第２の実施の形態）
次に、本発明の第２の実施の形態に係わるパワーＭＯＳＦＥＴの製造方法について、図４を参照して説明する。図４はパワーＭＯＳＦＥＴの製造工程を示す拡大工程断面図である。
【００３１】
本実施の形態では、第１の実施の形態におけるクリップの固着・接続方法をランプ加熱に変更した点で異なり、それ以外の構成については同一であり、以下異なる点のみ説明する。
【００３２】
ランプ加熱方法としては、図４に示すように、楕円面鏡を有するキセノンランプ６０の角度を任意に変更させて、楕円面鏡により集光されたランプ光６１、６２を第1および第２のクリップ３０，３１の両端部にそれぞれ照射する。即ち、低融点半田２３a、２３ｃ上に位置する第１のクリップ３０、および低融点半田２３b、２３d上に位置する第２のクリップ３１にランプ光６１、６２をそれぞれ照射することにより、第１のクリップ３０と第２のリード端子１４およびソース電極２１間、第２のクリップ３１と第３のリード端子１５およびゲート電極２２間の低融点半田２３ａ、２３ｂ、２３ｃ、２３ｄをそれぞれ溶融させ、第１および第２のクリップ３０，３１の一方端部と第２および第３のリード端子１４、１５、その他方端部とソースおよびゲート電極２１、２２との双方を合金化させることにより、それぞれ固着・接続する。なお、キセノンランプに代えて、ハロゲンランプを用いてもよい。
【００３３】
本実施の形態のパワーＭＯＳＦＥＴの製造方法では、第１および第２のクリップ３０、３１を、ソース電極２１の低融点半田２３aと第２のリード端子１４の低融点半田２３c上、およびゲート電極２２の低融点半田２３bと第３のリード端子１５の低融点半田２３d上にそれぞれ載置した後、フレーム１０を移動させることなく載置した場所で、ランプ光を照射させて第１および第２のクリップ３０、３１を固着・接続させているので、クリップの位置ズレが発生する恐れがない。
【００３４】
従って、半導体装置の信頼性および組立て工程の歩留の向上が図れる。
【００３５】
本発明は、上記実施の形態に限定されるものではなく、発明の趣旨を逸脱しない範囲で、種々、変更して実施してもよい。
【００３６】
例えば、第１および第２の実施の形態においては、第１および第２のクリップ３０、３１と第２および第３のリード端子１４、１５およびソースおよびゲート電極２１、２２との固着・接続を、その第１および第２のクリップ３０，３１を載置した後、移動させることなく、その載置工程において実施しているが、第１および第２のクリップ３０，３１をソースおよびゲート電極２１、２２上、第１および第２のリード端子１４，１５上にそれぞれ載置した後に、上述の実施の形態よりも出力を抑制したレーザ光、またはランプ光を照射し、第１および第２のクリップ３０，３１が移動時に位置ズレしないように、第１および第２のクリップ３０、３１の両端部のうちの少なくとも一方を仮固定してもよい。或いは、第１および第２のクリップ３０、３１の両端部のうちの一方の端部のみ、固着・接続しただけでもよい。
【００３７】
この場合は、第１および第２のクリップ３０，３１の少なくとも一方を仮固定、または一方の端部のみを固着したフレーム１０を移送し、加熱炉による加熱固着、加熱圧着、或いは超音波併用加熱圧着等の固着装置を用いて第１および第２のクリップ３０、３１の仮固定部分を、最終的に、それぞれ固着・接続させる。或いは、仮固定、または固着・接続していない他方の端部のみを最終的に固着・接続する。
【００３８】
また、上記実施の形態では、パワーＭＯＳＦＥＴからなる半導体チップを搭載した半導体装置の製造方法について説明したが、ＩＧＢＴからなる半導体チップを搭載した半導体装置、数種類の高耐圧デバイスを搭載したパワー半導体モジュール等の製造方法にも適用できる。
【００３９】
また、第1および第２の実施形態では、板状のクリップを用いたが、リード端子および電極との接触性を向上させるために、クリップに突起を設けたり、クリップ表面をけがいたり、スリットを設けるたり、或いは多数の穴を設けたりしてもよい。
【００４０】
【発明の効果】
本発明によれば、半導体装置の信頼性および組立て工程の歩留の向上が図れる。
【図面の簡単な説明】
【図１】 本発明の第１の実施の形態に係わる半導体装置の製造工程を工程順に示す平面図。
【図２】 図１(c)のＡ−Ａ線に沿う拡大断面図。
【図３】 図１(d)のＢ−Ｂ線に沿う拡大断面図。
【図４】 本発明の第２の実施の形態に係わる半導体装置の製造工程を示す拡大断面図。
【図５】 従来の半導体装置の製造方法を説明するため平面図。
【符号の説明】
１ パワーＭＯＳＦＥＴ（半導体装置）
１０、１００ リードフレーム
１１a、１１b サイドフレーム
１２、１０１ 第１のリード端子
１３，１０２ ベッド
１４、１０３ 第２のリード端子
１５、１０４ 第３のリード端子
２０ パワーＭＯＳＦＥＴチップ（半導体チップ）
２１ ソース電極
２２ ゲート電極
２３a、２３b、２３c、２３d 低融点半田（導電性固着部材）
３０、１２０ 第１のクリップ
３１、１２１ 第２のクリップ
５０ モールド樹脂
４１、４１ａ、４１ｂ レーザ光
４０ レーザ発生装置
４２ 光ファイバー
４３ 反射ミラー
６０ キセノンランプ
６１、６２ ランプ光
１１０ 半導体チップ
１１１、１１２ 電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a power semiconductor device such as a power MOSFET or IGBT having a structure in which an electrode of a semiconductor chip and a lead terminal are connected by a plate-like connecting conductor.
[0002]
[Prior art]
In recent years, in the manufacture of power semiconductor devices such as power MOSFETs or IGBTs, a plate made of Cu or the like instead of expensive gold wires or aluminum wires is used to reduce manufacturing costs and prevent disconnection of connecting conductors. The electrode of the semiconductor chip and the lead terminal are connected by using a connection conductor (hereinafter referred to as a clip).
[0003]
As a method for manufacturing this type of semiconductor device, one shown in FIG. 5 is known (for example, see Patent Document 1).
[0004]
As shown in FIG. 5, in the method of manufacturing a semiconductor device disclosed in Patent Document 1, first, a first lead terminal 101 having a bed 102 provided at the tip and one end of the bed 102 are close to each other. A lead frame 100 having second and third lead terminals 103 and 104 arranged is prepared, and a three-terminal type having electrodes 111 and 112 on the bed 102 of the first lead terminal 101 of the lead frame 100 The semiconductor chip 110 made of the diode is fixed with high melting point solder.
[0005]
Next, low melting point solder is formed on the electrodes 111 and 112 of the semiconductor chip 110 and on one end of the second and third lead terminals 103 and 104, respectively.
[0006]
Next, the first clip 120 is positioned on one end of the second lead terminal 103 on which one end is formed of low melting point solder, and on the electrode 111 on which the other end is formed on low melting point solder. To be placed. Similarly, the second clip 121 is placed on one end of the third lead terminal 104 at one end and on the electrode 112 at the other end.
[0007]
Next, this is transported to a fixing device such as a heating furnace or a heating device, in which one end of the first clip 120 is the second lead terminal 103 and the other end is the electrode 111. Secure and connect via solder. Similarly, one end of the second clip 121 is fixed and connected to one end of the third lead terminal 104 and the other end is fixed to the electrode 112 via solder.
[0008]
[Patent Document 1]
JP-A-8-148623 (page 3-4, FIG. 2)
[0009]
[Problems to be solved by the invention]
In the semiconductor device manufacturing method described above, since the step of mounting the clip is different from the step of fixing the clip to the electrode and the lead terminal, the step of transporting is interposed between the step of mounting and the step of fixing. To do. Therefore, the displacement of the so-called clip occurs due to vibration during transportation or contact with other manufacturing equipment, etc., resulting in lower reliability of the semiconductor device and lower yield of the assembly process. In the case of a clip having a step instead of a flat surface, there is a problem that the tendency is particularly remarkable.
[0010]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the reliability of the semiconductor device and the yield of the assembly process. is there.
[0011]
[Means for Solving the Problems]
In order to solve the above-described object, a manufacturing method of one embodiment of a semiconductor device according to the present invention includes a step of fixing a semiconductor chip to one lead terminal of a plurality of lead terminals, and another lead of the lead terminals. Placing one end of the plate-like connecting conductor on the terminal via a conductive fixing member, and placing the other end on the electrode of the semiconductor chip via the conductive fixing member; and The placing step includes a step of fixing the plate-like connecting conductor to the lead terminal and the electrode by irradiating an end portion of the plate-like connecting conductor with a laser beam .
The manufacturing method according to one aspect of the semiconductor device of the present invention includes a step of fixing a semiconductor chip to one lead terminal of a plurality of lead terminals, and a plate-like connecting conductor to another lead terminal of the lead terminals. A step of placing one end portion of the semiconductor chip on the electrode of the semiconductor chip via the conductive fixing member, and a step of mounting the other end portion on the electrode of the semiconductor chip. A step of fixing the plate-like connecting conductor to the lead terminal and the electrode by irradiating light to an end of the plate-like connecting conductor, respectively.
The manufacturing method according to one aspect of the semiconductor device of the present invention includes a step of fixing a semiconductor chip to one lead terminal of a plurality of lead terminals, and a plate-like connecting conductor to another lead terminal of the lead terminals. A step of placing one end portion of the semiconductor chip through a conductive fixing member, and a step of placing the other end portion on the electrode of the semiconductor chip through the conductive fixing member; A step of temporarily fixing at least one of both end portions of the plate-like connection conductor by irradiating light to an end portion of the plate-like connection conductor; and after the temporary fixing, the plate-like connection is conveyed to a fixing device A step of fixing the conductor, the lead terminal, the plate-like connecting conductor, and the electrode, respectively.
The manufacturing method according to one aspect of the semiconductor device of the present invention includes a step of fixing a semiconductor chip to one lead terminal of a plurality of lead terminals, and a plate-like connecting conductor to another lead terminal of the lead terminals. A step of placing one end portion of the semiconductor chip on the electrode of the semiconductor chip via the conductive fixing member, and a step of mounting the other end portion on the electrode of the semiconductor chip. A step of temporarily fixing at least one of both end portions of the plate-like connection conductor by irradiating light to an end portion of the plate-like connection conductor; and after the temporary fixing, the plate-like connection is conveyed to a fixing device. A step of fixing the conductor, the lead terminal, the plate-like connecting conductor, and the electrode, respectively.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0013]
(First embodiment)
First, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. This embodiment is an example of manufacturing a power MOSFET.
[0014]
1 is a process plan view showing a manufacturing process of a power MOSFET, FIG. 2 is an enlarged sectional view taken along line AA in FIG. 1C, and FIG. 3 is an enlarged section taken along line BB in FIG. FIG.
[0015]
As shown in FIG. 1A, first, a power MOSFET chip 20 is prepared as a lead frame 10 and a semiconductor chip.
[0016]
The lead frame 10 has side frames 11a and 11b at both left and right edges along the longitudinal direction thereof. The first lead terminal 12 is provided on one side frame 11a of the side frames 11a and 11b. It is integrally formed so as to protrude inward. A bed 13 for mounting a semiconductor chip is formed at the tip of the first lead terminal 12. Further, the other side frame 11b is formed with second and third lead terminals 14 and 15 projecting inwardly, and the tip thereof is directed close to the bed 13 of the first lead terminal 12. It is arranged to fit.
[0017]
On the other hand, the power MOSFET chip 20 has a source electrode 21 and a gate electrode 22 on its upper surface, and a drain electrode on its lower surface.
[0018]
Then, after forming a high melting point solder on the bed 13 of the first lead terminal 12 of the lead frame 10, the power MOSFET chip 20 is mounted and fixed.
[0019]
The power MOSFET chip 20 and the bed 13 may be fixed by forming a metal made of BaNi / AuGe or Ti / Au on the lower surface of the power MOSFET 20 instead of the high melting point solder and fixing the metal to the bed 13.
[0020]
Next, as shown in FIG. 1B, a conductive fixing member is formed on the source electrode 21 and the gate electrode 22 of the power MOSFET chip 20 and on one end of the second and third lead terminals 14 and 15, respectively. For example, low melting point solders 23a, 23b, 23c, and 23d having a melting point of 210 ° C. or lower are formed. The low melting point solder may be any of eutectic solder such as SnPb, SnBi, SnAgCuIn, and SnZn. Also, solder bumps, Au bumps, metals, or conductive adhesives may be used instead of the low melting point solder.
[0021]
Next, as shown in FIG. 1 (c), a low-melting-point solder having an elongated rectangular plate-like connecting conductor, for example, a first clip 30 made of copper (Cu), one end of which is the second lead terminal 14 is used. The other end portion is placed on the low melting point solder 23a of the source electrode 21 of the power MOSFET chip 20 on 23c. Similarly, the second clip 31 made of Cu has one end on the low melting point solder 23d of the third lead terminal 15 and the other end on the low melting point of the gate electrode 22 of the power MOSFET chip 20. It mounts so that it may be located on the solder 23b. The clips 30 and 31 are not limited to Cu, and may be formed of Al (aluminum) or Cu alloy foil.
[0022]
Here, as a method of supplying the clips 30 and 31, for example, a plurality of clips 30 and 31 that have been bent into a predetermined shape in advance are put into different parts feeders, and the clips are temporarily arranged in a row from each parts feeder. It is possible to apply a method of discharging and further transferring the discharged clips to a predetermined position in a state where the discharged clips are individually held by suction with a suction collet or the like. Further, when the clips 30 and 31 are placed, the image processing apparatus recognizes the placement state of the clips 30 and 31 and resets the positions of the first and second clips 30 and 31 for each transfer. It is also possible.
[0023]
Subsequently, both ends of the first clip 30 positioned on the low melting point solders 23a and 23c and both ends of the second clip 31 positioned on the low melting point solders 23b and 23d are respectively irradiated with laser light. Low melting point solders 23a and 23b between the end of the first clip 30 and the second lead terminal and the 14 source electrode 21, and between the end of the second clip 31 and the third lead terminal 15 and the gate electrode 22, By melting 23c and 23d, respectively, one end of the clips 30 and 31 and the second and third lead terminals 14 and 15 and the other end and the source and gate electrodes 21 and 22 are alloyed. , Each fixed and connected.
[0024]
In the present embodiment, after the first and second clips 30 and 31 are placed, the first and second clips 30 and 31 are moved in the placement step without being moved. Since the lead terminals 14 and 15 and the source and gate electrodes 21 and 22 are fixed and connected to each other, there is no possibility that the clip is misaligned.
[0025]
As shown in FIG. 2, a laser beam irradiation method includes a laser generator 40 having a semiconductor laser (LD), a plurality of optical fibers 42 for guiding laser beams 41 generated from the laser generator 40, and a laser. In order to irradiate the light 41 to an arbitrary place, the laser light 41a and 41b are irradiated by using a laser heating device including a reflection mirror 43 that changes the path of the laser light 41 (41a or 41b). Further, as the laser light source, a laser beam may be intermittently irradiated using a YAG laser, an excimer laser, a carbon dioxide gas laser, or the like instead of the LD.
[0026]
Furthermore, the lead frame 10 in which the first and second clips 30 and 31 are fixed and connected to the first and second lead terminals 14 and 15 and the source and gate electrodes 21 and 22 is transferred to a known mold. The power MOSFET chip 20 and its periphery are covered with a molding resin 50 by a molding die.
[0027]
Next, predetermined positions of the first to third lead terminals 12, 14, 15 are cut by a known punching die. With the above method, the power MOSFET 1 shown in FIG. 1 (d) and FIG. 3 is manufactured.
[0028]
In the power MOSFET manufacturing method of the present embodiment, the first and second clips 30, 31 are placed on the low melting point solder 23 a of the source electrode 21 and the low melting point solder 23 c of the second lead terminal 14, and the gate electrode 22. The low melting point solder 23b and the third lead terminal 15 are placed on the low melting point solder 23d, respectively, and then irradiated with laser light at the place where the frame 10 is placed without being moved. Since the clips 30 and 31 are fixed and connected, there is no possibility that the clip is misaligned.
[0029]
Therefore, the reliability of the semiconductor device and the yield of the assembly process can be improved.
[0030]
(Second Embodiment)
Next, a method for manufacturing a power MOSFET according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is an enlarged process cross-sectional view showing the manufacturing process of the power MOSFET.
[0031]
The present embodiment is different in that the clip fixing / connecting method in the first embodiment is changed to lamp heating, and other configurations are the same, and only different points will be described below.
[0032]
As a lamp heating method, as shown in FIG. 4, the angle of a xenon lamp 60 having an ellipsoidal mirror is arbitrarily changed, and lamp lights 61 and 62 condensed by the ellipsoidal mirror are used as the first and second lamp lights. The both ends of the clips 30 and 31 are irradiated. That is, the first clip 30 positioned on the low melting point solders 23a and 23c and the second clip 31 positioned on the low melting point solders 23b and 23d are irradiated with the lamp lights 61 and 62, respectively. The low melting point solders 23a, 23b, 23c and 23d between the clip 30 and the second lead terminal 14 and the source electrode 21 and between the second clip 31 and the third lead terminal 15 and the gate electrode 22 are melted, respectively. The first and second clip terminals 30 and 31 and the second and third lead terminals 14 and 15 and the other end of the second clip 30 and 31 and the source and gate electrodes 21 and 22 are both alloyed. Connecting. Note that a halogen lamp may be used instead of the xenon lamp.
[0033]
In the power MOSFET manufacturing method of the present embodiment, the first and second clips 30, 31 are placed on the low melting point solder 23 a of the source electrode 21 and the low melting point solder 23 c of the second lead terminal 14, and the gate electrode 22. The low-melting-point solder 23b and the low-melting-point solder 23d of the third lead terminal 15 are mounted on the low-melting-point solder 23d. Since the clips 30 and 31 are fixed and connected, there is no possibility that the clip is misaligned.
[0034]
Therefore, the reliability of the semiconductor device and the yield of the assembly process can be improved.
[0035]
The present invention is not limited to the above-described embodiment, and various modifications may be made without departing from the spirit of the invention.
[0036]
For example, in the first and second embodiments, the first and second clips 30, 31 are fixed and connected to the second and third lead terminals 14, 15 and the source and gate electrodes 21, 22. After the first and second clips 30 and 31 are mounted, the first and second clips 30 and 31 are used in the mounting step without being moved. , 22, and the first and second lead terminals 14 and 15, respectively, and then irradiated with laser light or lamp light whose output is suppressed more than in the above-described embodiment, At least one of the both ends of the first and second clips 30 and 31 may be temporarily fixed so that the clips 30 and 31 do not shift when moving. Alternatively, only one of the two end portions of the first and second clips 30 and 31 may be fixed and connected.
[0037]
In this case, at least one of the first and second clips 30 and 31 is temporarily fixed, or the frame 10 having only one end fixed is transferred, and is fixed by heating in a heating furnace, thermocompression bonding, or ultrasonic combined heating. The temporarily fixed portions of the first and second clips 30 and 31 are finally fixed and connected, respectively, using a fixing device such as crimping. Alternatively, only the other end which is not temporarily fixed or fixed and connected is finally fixed and connected.
[0038]
In the above embodiment, a method for manufacturing a semiconductor device mounted with a semiconductor chip made of a power MOSFET has been described. However, a semiconductor device mounted with a semiconductor chip made of IGBT, a power semiconductor module mounted with several types of high voltage devices, This method can also be applied.
[0039]
In the first and second embodiments, a plate-like clip is used. However, in order to improve the contact with the lead terminal and the electrode, the clip is provided with a protrusion, the clip surface is scratched, and a slit is provided. You may provide, or you may provide many holes.
[0040]
【The invention's effect】
According to the present invention, the reliability of the semiconductor device and the yield of the assembly process can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention in order of steps.
FIG. 2 is an enlarged cross-sectional view taken along the line AA in FIG.
3 is an enlarged cross-sectional view taken along line BB in FIG. 1 (d).
FIG. 4 is an enlarged cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a plan view for explaining a conventional method of manufacturing a semiconductor device.
[Explanation of symbols]
1 Power MOSFET (semiconductor device)
10, 100 Lead frame 11a, 11b Side frame 12, 101 First lead terminal 13, 102 Bed 14, 103 Second lead terminal 15, 104 Third lead terminal 20 Power MOSFET chip (semiconductor chip)
21 Source electrode 22 Gate electrodes 23a, 23b, 23c, 23d Low melting point solder (conductive fixing member)
30, 120 First clip 31, 121 Second clip 50 Mold resin 41, 41a, 41b Laser light 40 Laser generator 42 Optical fiber 43 Reflective mirror 60 Xenon lamp 61, 62 Lamp light 110 Semiconductor chip 111, 112 Electrode

Claims (6)

複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、
前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、
この載置工程において、レーザ光を前記板状接続導体の端部に照射することにより前記板状接続導体を前記リード端子および前記電極にそれぞれ固着する工程と、
を具備することを特徴とする半導体装置の製造方法。Fixing the semiconductor chip to one of the plurality of lead terminals;
One end of the plate-like connecting conductor is placed on another lead terminal of the lead terminals via a conductive fixing member, and the other end is placed on the electrode of the semiconductor chip. A step of placing through,
In this placing step, the step of fixing the plate connection conductor to the lead terminal and the electrode by irradiating the end portion of the plate connection conductor with laser light, and
A method for manufacturing a semiconductor device, comprising: 複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、
前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、
この載置工程において、ランプ光を前記板状接続導体の端部に照射することにより前記板状接続導体を前記リード端子および前記電極にそれぞれ固着する工程と、
を具備することを特徴とする半導体装置の製造方法。Fixing the semiconductor chip to one of the plurality of lead terminals;
One end of the plate-like connecting conductor is placed on another lead terminal of the lead terminals via a conductive fixing member, and the other end is placed on the electrode of the semiconductor chip. A step of placing through,
In this placing step, the step of fixing the plate connection conductor to the lead terminal and the electrode by irradiating lamp light to the end of the plate connection conductor,
A method for manufacturing a semiconductor device, comprising: 複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、
前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、
この載置工程において、レーザ光を前記板状接続導体の端部に照射することにより前記板状接続導体の両端部うちの少なくとも一方を仮固定する工程と、
前記仮固定後、固着装置に搬送して、前記板状接続導体と前記リード端子および前記板状接続導体と前記電極をそれぞれ固着する工程と、
を具備することを特徴とする半導体装置の製造方法。Fixing the semiconductor chip to one of the plurality of lead terminals;
One end of the plate-like connecting conductor is placed on another lead terminal of the lead terminals via a conductive fixing member, and the other end is placed on the electrode of the semiconductor chip. A step of placing through,
In this placing step, a step of temporarily fixing at least one of both end portions of the plate-like connection conductor by irradiating the end portion of the plate-like connection conductor with laser light ;
After the temporary fixing, transporting to a fixing device, and fixing the plate-like connecting conductor and the lead terminal and the plate-like connecting conductor and the electrode, respectively,
A method for manufacturing a semiconductor device, comprising: 複数のリード端子のうちの１つのリード端子に半導体チップを固着する工程と、
前記リード端子のうちの他のリード端子に板状接続導体の一方端部を導電性固着部材を介して載置し、且つその他方端部を前記半導体チップの電極上に前記導電性固着部材を介して載置する工程と、
この載置工程において、ランプ光を前記板状接続導体の端部に照射することにより前記板状接続導体の両端部うちの少なくとも一方を仮固定する工程と、
前記仮固定後、固着装置に搬送して、前記板状接続導体と前記リード端子および前記板状接続導体と前記電極をそれぞれ固着する工程と、
を具備することを特徴とする半導体装置の製造方法。Fixing the semiconductor chip to one of the plurality of lead terminals;
One end of the plate-like connecting conductor is placed on another lead terminal of the lead terminals via a conductive fixing member, and the other end is placed on the electrode of the semiconductor chip. A step of placing through,
In this placing step, the step of temporarily fixing at least one of both ends of the plate-like connecting conductor by irradiating lamp light to the end of the plate-like connecting conductor;
After the temporary fixing, transporting to a fixing device, and fixing the plate-like connecting conductor and the lead terminal and the plate-like connecting conductor and the electrode, respectively,
A method for manufacturing a semiconductor device, comprising: 前記導電性固着部材は、半田、半田バンプ、Ａｕバンプ、或いは金属から選ばれた１つであることを特徴とする請求項１乃至４のいずれか１項記載の半導体装置の製造方法。The conductive fixing member, solder, solder bumps, Au bumps, or a method of manufacturing a semiconductor device of any one of claims 1 to 4, characterized in that one selected from a metal. 前記リード端子は、リードフレームにより構成されてなることを特徴とする請求項１乃至４のいずれか１項記載の半導体装置の製造方法。It said lead terminals, a method of manufacturing a semiconductor device according to any one of claims 1 to 4, characterized by being constituted by a lead frame.
JP2003099846A 2003-04-03 2003-04-03 Manufacturing method of semiconductor device Expired - Fee Related JP3739091B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003099846A JP3739091B2 (en) 2003-04-03 2003-04-03 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003099846A JP3739091B2 (en) 2003-04-03 2003-04-03 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2004311539A JP2004311539A (en) 2004-11-04
JP3739091B2 true JP3739091B2 (en) 2006-01-25

Family

ID=33464142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003099846A Expired - Fee Related JP3739091B2 (en) 2003-04-03 2003-04-03 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP3739091B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008305902A (en) * 2007-06-06 2008-12-18 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088263A (en) * 2005-09-22 2007-04-05 Toshiba Components Co Ltd Terminal-frame structure
JP4842118B2 (en) * 2006-01-24 2011-12-21 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5103863B2 (en) * 2006-10-16 2012-12-19 富士電機株式会社 Semiconductor device
JP4894528B2 (en) * 2007-01-17 2012-03-14 トヨタ自動車株式会社 Wiring bonding method of semiconductor element
JP4985012B2 (en) * 2007-03-22 2012-07-25 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP5090088B2 (en) 2007-07-05 2012-12-05 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP2009105266A (en) * 2007-10-24 2009-05-14 Fuji Electric Device Technology Co Ltd Method of manufacturing semiconductor apparatus
JP2011204886A (en) * 2010-03-25 2011-10-13 Panasonic Corp Semiconductor device and method of manufacturing the same
JP5615757B2 (en) * 2011-04-06 2014-10-29 新電元工業株式会社 Semiconductor device, connector, and manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008305902A (en) * 2007-06-06 2008-12-18 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP2004311539A (en) 2004-11-04

Similar Documents

Publication Publication Date Title
US6709967B2 (en) Laser wire bonding for wire embedded dielectrics to integrated circuits
JP3885747B2 (en) Wire bonding method
US6717100B2 (en) Apparatus and method for laser welding of ribbons
US20130273697A1 (en) Fabrication method of a mixed alloy lead frame for packaging power semiconductor devices
JP3739091B2 (en) Manufacturing method of semiconductor device
JP4722757B2 (en) Manufacturing method of semiconductor device
JPH09102571A (en) Manufacture of power semiconductor and lead frame
JP7368450B2 (en) Semiconductor device and bonding method
US9136225B2 (en) Semiconductor device manufacturing method
KR200482370Y1 (en) Clip structure for semiconductor package and semiconductor package including the same
US9076782B2 (en) Semiconductor device and method of manufacturing same
JP4028101B2 (en) Semiconductor device
JP2954110B2 (en) CSP type semiconductor device and manufacturing method thereof
WO2020045263A1 (en) Joined structure, semiconductor device, and joining method
JP3570551B2 (en) Wire bonding method
US11316292B2 (en) Semiconductor power module and method for producing a semiconductor power module
JP2002280479A (en) Surface mounting semiconductor device
JP2009224529A (en) Semiconductor device and its manufacturing method
KR20150129269A (en) Clip structure for semiconductor package and semiconductor package including the same, methods of manufacturing for the same
JP3206716B2 (en) Semiconductor device and lead frame pair
JPH06252326A (en) Multi-terminal component, wiring substrate and packaging structure of multi-terminal component
JP2798040B2 (en) Method for manufacturing semiconductor device
JPH04267385A (en) Semiconductor module
JPH11297729A (en) Semiconductor package and forming method thereof
JP2022016297A (en) Semiconductor device and manufacturing method for semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041005

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050415

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20050606

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050815

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050819

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051005

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20051028

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20051031

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081111

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091111

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101111

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101111

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111111

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121111

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131111

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees