JP2002280479A - Surface mounting semiconductor device - Google Patents

Surface mounting semiconductor device

Info

Publication number
JP2002280479A
JP2002280479A JP2001082172A JP2001082172A JP2002280479A JP 2002280479 A JP2002280479 A JP 2002280479A JP 2001082172 A JP2001082172 A JP 2001082172A JP 2001082172 A JP2001082172 A JP 2001082172A JP 2002280479 A JP2002280479 A JP 2002280479A
Authority
JP
Japan
Prior art keywords
substrate
wire
resin package
resin
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001082172A
Other languages
Japanese (ja)
Inventor
Takaaki Onizuka
崇彰 鬼塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001082172A priority Critical patent/JP2002280479A/en
Publication of JP2002280479A publication Critical patent/JP2002280479A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To provide a surface mounting semiconductor device in which the conduction structure can be preserved by enhancing the bonding strength of a substrate and a resin package and preventing solder from having effect on a bonded wire at the time of mounting by soldering. SOLUTION: A light emitting element 4 is mounted conductively on one electrode 2 out of a pair of metal electrodes 2 and 3 provided on a substrate 1 utilizing insulating resin and the light emitting element 4 is bonded to the other electrode 3 through a wire 5. When they are sealed into a resin package 6 including the wire 5, cuts 8 and 9 are made in the metal electrodes 2 and 3 to expose the substrate 1 which is then bonded to the resin package 6 through resin in order to enhance the bonding strength of the substrate 1 and the resin package 6 thus preventing solder from intruding between the substrate 1 and the resin package 6 at the time of mounting by soldering.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体発光素子ま
たは受光素子などを備える半導体装置に係り、特にプリ
ント配線基板などの表面に実装されて半田付けにより固
定される表面実装型の半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor light-emitting element or a light-receiving element, and more particularly to a surface-mounted semiconductor device which is mounted on a surface of a printed wiring board and fixed by soldering.

【0002】[0002]

【従来の技術】半導体発光素子を使用した半導体発光装
置には、リードフレームのマウント部に発光素子を実装
してワイヤボンディングするとともにエポキシ樹脂によ
り封止した砲弾型のLEDランプと、プリント配線基板
の上に半田付けにより導通実装が可能な表面実装型のも
のがある。表面実装型の半導体発光装置は、LEDラン
プに比べて小型薄型化できるため、各種の小型電子機器
に多用されている。
2. Description of the Related Art A semiconductor light emitting device using a semiconductor light emitting element includes a shell type LED lamp in which a light emitting element is mounted on a mounting portion of a lead frame, wire-bonded and sealed with an epoxy resin, and a printed wiring board. There is a surface mount type that can be electrically mounted by soldering. Surface-mount type semiconductor light emitting devices can be made smaller and thinner than LED lamps, and are therefore frequently used in various small electronic devices.

【0003】図3の(a)は従来の表面実装型の半導体
発光装置の概略を示す透視平面図、(b)はプリント配
線基板上への実装状態における(a)のC−C線断面図
である。
FIG. 3A is a perspective plan view schematically showing a conventional surface-mount type semiconductor light emitting device, and FIG. 3B is a cross-sectional view taken along line CC of FIG. 3A in a state of being mounted on a printed wiring board. It is.

【0004】表面実装型の半導体発光装置は、図示のよ
うに絶縁性のBT(Bismaleimide Tri
azine)レジン樹脂などを利用した基板1と、その
両端にAuメッキによりパターン形成された一対の金属
電極2,3と、一方の金属電極2の上にAgペースト7
を介して導通搭載された発光素子4と、この発光素子4
の上端の電極と他方の金属電極3との間をボンディング
接続するワイヤ5と、このワイヤ5を含んで封止するエ
ポキシ系の樹脂を使用した樹脂パッケージ6とから構成
されたものである。
As shown in the figure, a surface-mount type semiconductor light emitting device has an insulating BT (Bismaleimide Tri).
azine) a substrate 1 made of resin or the like, a pair of metal electrodes 2 and 3 having both ends patterned by Au plating, and an Ag paste 7 on one metal electrode 2
Light-emitting element 4 that is conductively mounted via
And a resin package 6 using an epoxy-based resin for sealing including the wire 5 between the upper end electrode and the other metal electrode 3.

【0005】このような構成の表面実装型の半導体発光
装置は、図3の(b)に示すようにプリント配線基板5
1の上に導通実装される。この導通実装はプリント配線
基板51の表面に形成された電極パターン51a,51
bに半導体発光装置の金属電極2,3を位置合わせして
搭載し、それぞれ半田52,53付けによって固定され
る。これにより、発光素子4は電源側と導通し通電によ
って発光する。
[0005] A surface-mounted type semiconductor light emitting device having such a configuration has a printed wiring board 5 as shown in FIG.
1 is electrically conductively mounted. This conductive mounting is performed by the electrode patterns 51a, 51a formed on the surface of the printed wiring board 51.
b, the metal electrodes 2 and 3 of the semiconductor light emitting device are aligned and mounted, and fixed by soldering 52 and 53, respectively. Thereby, the light emitting element 4 conducts with the power supply side and emits light when energized.

【0006】[0006]

【発明が解決しようとする課題】錫と鉛の合金による半
田52,53は、約250℃で溶融したものをソルダリ
ングして金属電極2,3をそれぞれ配線パターン51
a,51bに導通固定する。ところが、上記従来の半導
体発光装置では、樹脂パッケージ6と基板1とはそれぞ
れ樹脂同士であるため接合力が強いが、樹脂パッケージ
6と金属電極2,3とはそれぞれ樹脂と金属であるため
接合力が弱い。そのため、250℃程度の高温に樹脂パ
ッケージ6が曝されると、図3の(b)に示すように半
田52,53が樹脂パッケージ6の中まで浸潤しやす
い。
The solders 52 and 53 made of an alloy of tin and lead are melted at about 250.degree.
a, 51b. However, in the above-described conventional semiconductor light emitting device, the resin package 6 and the substrate 1 are made of resin, and therefore have high bonding strength. However, since the resin package 6 and the metal electrodes 2 and 3 are made of resin and metal, respectively, the bonding strength is high. Is weak. Therefore, when the resin package 6 is exposed to a high temperature of about 250 ° C., the solders 52 and 53 easily infiltrate into the resin package 6 as shown in FIG.

【0007】一方、ワイヤ5は発光素子4の上面の電極
にボンディングされた後に金属電極3のボンディングエ
リア3eにウェッジボンディングされる。このウェッジ
ボンディングは、ワイヤ5の一端側をボンディングエリ
ア3eの表面にこすり付けるようにして接合する手法で
ある。
On the other hand, after the wire 5 is bonded to the electrode on the upper surface of the light emitting element 4, it is wedge bonded to the bonding area 3e of the metal electrode 3. The wedge bonding is a method of bonding such that one end of the wire 5 is rubbed against the surface of the bonding area 3e.

【0008】ところが、半田53が樹脂パッケージ6の
中まで浸潤してくると、ウェッジボンディングされたワ
イヤ5の先端部分の樹脂パッケージ6の樹脂が高温にな
って軟化したり膨張したりする。このような樹脂の軟化
や膨張は、ワイヤ5のウェッジボンディングを上に持ち
上げるように作用し、ワイヤ5の先端がボンディングエ
リア3eから浮き上がってしまうことがある。このた
め、ワイヤ5と金属電極3との導通が切れてしまい、発
光素子4への通電ができなくなる。
However, when the solder 53 infiltrates into the resin package 6, the resin of the resin package 6 at the tip of the wedge-bonded wire 5 becomes hot and softens or expands. Such softening or expansion of the resin acts to lift the wedge bonding of the wire 5 upward, and the tip of the wire 5 may rise from the bonding area 3e. For this reason, the conduction between the wire 5 and the metal electrode 3 is cut off, and it becomes impossible to supply electricity to the light emitting element 4.

【0009】このように、一方の金属電極3にワイヤ5
をウェッジボンディングするものでは、プリント配線基
板51への実装時に半田53の影響を受けて発光素子4
への通電に影響を及ぼす。したがって、実装製品の歩留
りの低下などの問題を引き起こすことになる。そして、
半導体発光装置の分野だけでなく受光装置などのように
ワイヤボンディングしたものを樹脂封止して半田付けに
よって表面実装する全ての半導体装置についても同様の
問題がある。
Thus, the wire 5 is connected to one of the metal electrodes 3.
Is wedge-bonded, the light emitting element 4 is affected by the solder 53 when mounted on the printed wiring board 51.
Affects current supply to Therefore, a problem such as a decrease in the yield of mounted products is caused. And
A similar problem exists not only in the field of semiconductor light emitting devices but also in all semiconductor devices in which wire-bonded devices such as light receiving devices are resin-sealed and surface-mounted by soldering.

【0010】そこで、本発明は、基板と樹脂パッケージ
との接着強度を上げることにより、半田付けによる実装
の際に半田がボンディングされたワイヤに影響を及ぼさ
ないようにして導通構造の保全が可能な表面実装型の半
導体装置を提供することを目的とする。
Therefore, the present invention can maintain the conductive structure by increasing the adhesive strength between the substrate and the resin package so that the solder does not affect the wire bonded at the time of mounting by soldering. It is an object to provide a surface-mounted semiconductor device.

【0011】[0011]

【課題を解決するための手段】本発明の表面実装型の半
導体装置は、絶縁性の樹脂を利用した基板と、基板に形
成した一対の金属電極と、基板または一対の金属電極の
うちの一方に搭載される半導体素子と、半導体素子と金
属電極の少なくとも一方との間をボンディングするワイ
ヤと、半導体素子及びワイヤを封止する樹脂パッケージ
とを備えた半導体装置において、金属電極には、基板を
露出させた切欠部を形成したことを特徴とする。
According to the present invention, there is provided a surface mount type semiconductor device comprising: a substrate using an insulating resin; a pair of metal electrodes formed on the substrate; and one of the substrate and the pair of metal electrodes. In a semiconductor device including a semiconductor element mounted on a semiconductor element, a wire for bonding between the semiconductor element and at least one of the metal electrodes, and a resin package for sealing the semiconductor element and the wire, the metal electrode includes a substrate. An exposed notch is formed.

【0012】本発明によれば、金属電極に形成した切欠
部を介して基板と樹脂パッケージとが樹脂同士で接合さ
れるため、基板と樹脂パッケージとの接着強度を上げる
ことができ、さらに半田付けによる実装時に基板と樹脂
パッケージとの間に半田が浸入するのを防止することが
できる。
According to the present invention, the substrate and the resin package are joined together by the resin via the notch formed in the metal electrode, so that the adhesive strength between the substrate and the resin package can be increased, and furthermore, the soldering can be performed. It is possible to prevent solder from intruding between the substrate and the resin package at the time of mounting.

【0013】[0013]

【発明の実施の形態】請求項1に記載の発明は、絶縁性
の樹脂を利用した基板と、前記基板に形成した一対の金
属電極と、前記基板または前記一対の金属電極のうちの
一方に搭載される半導体素子と、前記半導体素子と前記
金属電極の少なくとも一方との間をボンディングするワ
イヤと、前記半導体素子及びワイヤを封止する樹脂パッ
ケージとを備えた半導体装置において、前記金属電極に
は、前記基板を露出させた切欠部を形成したことを特徴
とする表面実装型の半導体装置であり、切欠部によって
露出した基板と樹脂パッケージとが樹脂同士で接合され
るため、基板と樹脂パッケージとの接着強度を上げるこ
とができ、さらに半田付けによる実装時に基板と樹脂パ
ッケージとの間に半田が浸入するのを防止することがで
きる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is a method for manufacturing a substrate using an insulating resin, a pair of metal electrodes formed on the substrate, and one of the substrate and the pair of metal electrodes. In a semiconductor device including a semiconductor element to be mounted, a wire for bonding between the semiconductor element and at least one of the metal electrodes, and a resin package for sealing the semiconductor element and the wire, the metal electrode includes A surface-mount type semiconductor device, characterized in that a cutout portion exposing the substrate is formed, and the substrate and the resin package exposed by the cutout portion are joined to each other by a resin. Can be increased, and solder can be prevented from entering between the substrate and the resin package during mounting by soldering.

【0014】請求項2に記載の発明は、前記切欠部を、
前記ワイヤをボンディングする位置と前記樹脂パッケー
ジの境界との間に設けたことを特徴とする請求項1記載
の表面実装型の半導体装置であり、切欠部を挟んでワイ
ヤのボンディング点を樹脂パッケージの境界と区分けし
て、半田付けによる実装時に基板と樹脂パッケージとの
間に半田が浸入してワイヤのボンディング点に到達する
のを阻止することができる。
According to a second aspect of the present invention, the notch is
2. The surface mounting type semiconductor device according to claim 1, wherein the bonding point of the wire is provided between a position where the wire is bonded and a boundary of the resin package. By separating from the boundary, it is possible to prevent the solder from entering between the substrate and the resin package during the mounting by soldering and reaching the bonding point of the wire.

【0015】以下、本発明の実施の形態を図面に基づい
て説明する。なお、本実施の形態では半導体発光装置を
例として説明し、図3で示した従来例と同じ構成部材に
ついては共通の符号で指示する。
An embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, a semiconductor light emitting device will be described as an example, and the same components as those in the conventional example shown in FIG.

【0016】図1の(a)は本発明の実施の形態におけ
る半導体発光装置の概略を示す透視平面図、(b)は
(a)のA−A線断面図、図2の(a)はプリント配線
基板上への実装時の概略を示す透視平面図、(b)は
(a)のB−B線断面図である。
FIG. 1A is a perspective plan view schematically showing a semiconductor light emitting device according to an embodiment of the present invention, FIG. 1B is a sectional view taken along line AA of FIG. 1A, and FIG. FIG. 3B is a perspective plan view showing an outline of mounting on a printed wiring board, and FIG.

【0017】図1及び図2において、半導体発光装置は
従来例と同様に、絶縁性のBTレジン樹脂などを利用し
た基板1と、その両端にAuメッキによりパターン形成
された一対の金属電極2,3と、一方の金属電極2の上
にAgペースト7を介して導通搭載された発光素子4
と、この発光素子4の上端の電極と他方の金属電極3の
ボンディングエリア3eとの間をボンディング接続する
ワイヤ5と、このワイヤ5を含んで封止するエポキシ系
の樹脂を使用した樹脂パッケージ6とから構成されてい
る。
Referring to FIGS. 1 and 2, the semiconductor light emitting device has a substrate 1 made of an insulating BT resin and the like, and a pair of metal electrodes 2, which are patterned at both ends by Au plating. 3 and a light emitting element 4 conductively mounted on one of the metal electrodes 2 via an Ag paste 7.
A wire 5 for bonding connection between an upper end electrode of the light emitting element 4 and a bonding area 3e of the other metal electrode 3; and a resin package 6 using an epoxy resin for sealing including the wire 5. It is composed of

【0018】また、金属電極3には、ワイヤをウェッジ
ボンディングする位置であるボンディングエリア3eと
樹脂パッケージ6の境界との間の位置に切欠部8を形成
している。一方、金属電極2には、同様に発光素子4が
搭載される部分と樹脂パッケージ6の境界との間の位置
に切欠部9を形成している。切欠部8,9は、基板1が
露出する深さとなるように金属電極3をエッチングによ
って除去して形成されている。
A notch 8 is formed in the metal electrode 3 at a position between the bonding area 3 e where the wire is to be wedge bonded and the boundary of the resin package 6. On the other hand, a notch 9 is formed in the metal electrode 2 at a position between the portion where the light emitting element 4 is mounted and the boundary of the resin package 6. The notches 8 and 9 are formed by removing the metal electrode 3 by etching so that the substrate 1 is exposed.

【0019】以上の構成において、半導体発光装置を図
2のようにプリント配線基板51の上に実装搭載すると
き、金属電極2,3を配線パターン51a,51bに位
置合わせして搭載し、半田52,53によって導通固定
する。このとき、樹脂パッケージ6は250℃程度の高
温に曝されるが、基板1を露出した切欠部8,9を介し
て樹脂パッケージ6は基板1と樹脂同士で強固に接合さ
れているため、半田52,53が樹脂パッケージ6の中
に浸潤していくことが防止され、樹脂パッケージ6の樹
脂の軟化及び膨張が阻止される。また、切欠部8,9は
樹脂パッケージ6の境界近傍の位置に形成されているた
め、半田52,53が樹脂パッケージ6の中に浸潤して
きても、溶融半田の流れは切欠部8,9によって阻止さ
れる。したがって、ウェッジボンディングされているワ
イヤ5がボンディングエリア3eから浮き上がることが
なく、ワイヤ5と金属電極3との間の導通構造が確実に
保全される。
In the above configuration, when the semiconductor light emitting device is mounted and mounted on the printed wiring board 51 as shown in FIG. 2, the metal electrodes 2 and 3 are mounted in alignment with the wiring patterns 51a and 51b, and the solder 52 is mounted. , 53 for continuity. At this time, although the resin package 6 is exposed to a high temperature of about 250 ° C., the resin package 6 is firmly joined to the substrate 1 through the cutouts 8 and 9 exposing the substrate 1. 52 and 53 are prevented from infiltrating into the resin package 6, and the softening and expansion of the resin of the resin package 6 are prevented. Since the notches 8 and 9 are formed near the boundary of the resin package 6, even if the solders 52 and 53 infiltrate into the resin package 6, the flow of the molten solder is controlled by the notches 8 and 9. Will be blocked. Therefore, the wedge-bonded wire 5 does not rise from the bonding area 3e, and the conduction structure between the wire 5 and the metal electrode 3 is reliably maintained.

【0020】このように、金属電極2,3の一部の表面
に切欠部8,9を形成するだけで、発光素子4への導通
構造を確保でき、プリント配線基板51への実装後の製
品の歩留まりを大幅に向上させることができる。
As described above, a conductive structure to the light emitting element 4 can be ensured only by forming the cutouts 8 and 9 on a part of the surface of the metal electrodes 2 and 3, and the product after mounting on the printed wiring board 51. Can be greatly improved.

【0021】なお、以上の例では発光素子4を金属電極
2上に搭載した半導体発光装置について説明したが、基
板1上に絶縁性の樹脂にて搭載した後、ワイヤボンディ
ングにて金属電極2,3と導通した構造としてもよい。
また、受光素子を含むフォトカプラーやその他の半導体
装置にも本発明を適用することが可能である。
In the above example, a semiconductor light emitting device in which the light emitting element 4 is mounted on the metal electrode 2 has been described. However, after the light emitting element 4 is mounted on the substrate 1 with an insulating resin, the metal electrodes 2 and 2 are bonded by wire bonding. A structure that is electrically connected to 3 may be used.
In addition, the present invention can be applied to a photocoupler including a light receiving element and other semiconductor devices.

【0022】[0022]

【発明の効果】本発明では、金属電極に切欠部を設けて
基板を露出させ、この切欠部を介して露出した基板と樹
脂パッケージとを樹脂同士で強固に接合することがで
き、さらに半田付けによる実装時に基板と樹脂パッケー
ジとの間に半田が浸入するのを防止することができる。
According to the present invention, the substrate is exposed by providing a notch in the metal electrode, and the exposed substrate and the resin package can be firmly joined to each other through the notch by the resin. It is possible to prevent solder from intruding between the substrate and the resin package at the time of mounting.

【0023】また、本発明では、ワイヤをボンディング
する位置と樹脂パッケージの境界との間に切欠部を設
け、切欠部を挟んでワイヤのボンディング点を樹脂パッ
ケージの境界と区分けして、半田付けによる実装時に基
板と樹脂パッケージとの間に半田が浸入してワイヤのボ
ンディング点に到達するのを阻止することができる。
Further, according to the present invention, a notch is provided between the position where the wire is bonded and the boundary of the resin package, and the bonding point of the wire is separated from the boundary of the resin package with the notch interposed therebetween. It is possible to prevent solder from entering between the substrate and the resin package at the time of mounting and reaching the bonding point of the wire.

【0024】このため、樹脂パッケージでワイヤを封止
する場合にボンディング点近くでの樹脂の軟化や膨張が
なくワイヤの浮き上がりが防止される。したがって、表
面実装のときの導通構造が保全され、歩留まりの高い製
造が可能となる。
For this reason, when the wire is sealed by the resin package, the resin is not softened or expanded near the bonding point, and the floating of the wire is prevented. Therefore, the conductive structure at the time of surface mounting is preserved, and high-yield manufacturing becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明の実施の形態における半導体発
光装置の概略を示す透視平面図 (b)は(a)のA−A線断面図
1A is a perspective plan view schematically showing a semiconductor light emitting device according to an embodiment of the present invention, and FIG. 1B is a sectional view taken along line AA of FIG.

【図2】(a)はプリント配線基板上への実装時の概略
を示す透視平面図 (b)は(a)のB−B線断面図
FIG. 2A is a perspective plan view schematically showing a state of mounting on a printed wiring board, and FIG. 2B is a sectional view taken along line BB of FIG.

【図3】(a)は従来の表面実装型の半導体発光装置の
概略を示す透視平面図 (b)はプリント配線基板上への実装状態における
(a)のC−C線断面図
3A is a perspective plan view schematically showing a conventional surface-mount type semiconductor light emitting device, and FIG. 3B is a cross-sectional view taken along the line CC of FIG. 3A in a state of being mounted on a printed wiring board.

【符号の説明】[Explanation of symbols]

1 基板 2,3 金属電極 3e ボンディングエリア 4 発光素子 5 ワイヤ 6 樹脂パッケージ 7 Agペースト 8,9 切欠部 51 プリント配線基板 51a,51b 配線パターン 52,53 半田 DESCRIPTION OF SYMBOLS 1 Substrate 2, 3 Metal electrode 3e Bonding area 4 Light emitting element 5 Wire 6 Resin package 7 Ag paste 8, 9 Notch 51 Printed wiring board 51a, 51b Wiring pattern 52, 53 Solder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性の樹脂を利用した基板と、前記基
板に形成した一対の金属電極と、前記基板または前記一
対の金属電極のうちの一方に搭載される半導体素子と、
前記半導体素子と前記金属電極の少なくとも一方との間
をボンディングするワイヤと、前記半導体素子及びワイ
ヤを封止する樹脂パッケージとを備えた半導体装置にお
いて、 前記金属電極には、前記基板を露出させた切欠部を形成
したことを特徴とする表面実装型の半導体装置。
A substrate using an insulating resin; a pair of metal electrodes formed on the substrate; a semiconductor element mounted on one of the substrate and the pair of metal electrodes;
In a semiconductor device having a wire for bonding between the semiconductor element and at least one of the metal electrodes, and a resin package for sealing the semiconductor element and the wire, the metal electrode has the substrate exposed. A surface-mounted type semiconductor device, wherein a notch is formed.
【請求項2】 前記切欠部を、前記ワイヤをボンディン
グする位置と前記樹脂パッケージの境界との間に設けた
ことを特徴とする請求項1記載の表面実装型の半導体装
置。
2. The surface-mounted semiconductor device according to claim 1, wherein said cutout portion is provided between a position where said wire is bonded and a boundary of said resin package.
JP2001082172A 2001-03-22 2001-03-22 Surface mounting semiconductor device Pending JP2002280479A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001082172A JP2002280479A (en) 2001-03-22 2001-03-22 Surface mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001082172A JP2002280479A (en) 2001-03-22 2001-03-22 Surface mounting semiconductor device

Publications (1)

Publication Number Publication Date
JP2002280479A true JP2002280479A (en) 2002-09-27

Family

ID=18938157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001082172A Pending JP2002280479A (en) 2001-03-22 2001-03-22 Surface mounting semiconductor device

Country Status (1)

Country Link
JP (1) JP2002280479A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303396A (en) * 2005-04-25 2006-11-02 Matsushita Electric Works Ltd Surface-mounting light-emitting device
US9601670B2 (en) 2014-07-11 2017-03-21 Cree, Inc. Method to form primary optic with variable shapes and/or geometries without a substrate
US9711703B2 (en) 2007-02-12 2017-07-18 Cree Huizhou Opto Limited Apparatus, system and method for use in mounting electronic elements
US9722158B2 (en) 2009-01-14 2017-08-01 Cree Huizhou Solid State Lighting Company Limited Aligned multiple emitter package
JP2018067731A (en) * 2011-02-16 2018-04-26 ローム株式会社 LED module
US10622522B2 (en) 2014-09-05 2020-04-14 Theodore Lowes LED packages with chips having insulated surfaces
US10892383B2 (en) 2007-10-31 2021-01-12 Cree, Inc. Light emitting diode package and method for fabricating same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303396A (en) * 2005-04-25 2006-11-02 Matsushita Electric Works Ltd Surface-mounting light-emitting device
JP4674487B2 (en) * 2005-04-25 2011-04-20 パナソニック電工株式会社 Surface mount light emitting device
US9711703B2 (en) 2007-02-12 2017-07-18 Cree Huizhou Opto Limited Apparatus, system and method for use in mounting electronic elements
US10892383B2 (en) 2007-10-31 2021-01-12 Cree, Inc. Light emitting diode package and method for fabricating same
US11791442B2 (en) 2007-10-31 2023-10-17 Creeled, Inc. Light emitting diode package and method for fabricating same
US9722158B2 (en) 2009-01-14 2017-08-01 Cree Huizhou Solid State Lighting Company Limited Aligned multiple emitter package
JP2018067731A (en) * 2011-02-16 2018-04-26 ローム株式会社 LED module
US9601670B2 (en) 2014-07-11 2017-03-21 Cree, Inc. Method to form primary optic with variable shapes and/or geometries without a substrate
US10622522B2 (en) 2014-09-05 2020-04-14 Theodore Lowes LED packages with chips having insulated surfaces

Similar Documents

Publication Publication Date Title
JP4023723B2 (en) Surface mount type light emitting diode
US20050218494A1 (en) Semiconductor device, a method of manufacturing the same and an electronic device
JPWO2009130743A1 (en) Optical element package, semiconductor light emitting device and lighting device
US6501160B1 (en) Semiconductor device and a method of manufacturing the same and a mount structure
JP2001168393A (en) Chip type semiconductor light emitting device
JPH1050734A (en) Chip type semiconductor
US20210265214A1 (en) Methods and apparatus for an improved integrated circuit package
JPH08204239A (en) Resin sealed light emission device
JP2001196641A (en) Surface mount semiconductor device
JP2002280479A (en) Surface mounting semiconductor device
JP2001352102A (en) Optical semiconductor device
JP3864263B2 (en) Light emitting semiconductor device
JPH11112036A (en) Surface mounting semiconductor device
JP4608810B2 (en) Surface mount semiconductor device
JP2000036621A (en) Electrode structure of side-surface electronic component
JPH10150227A (en) Chip-type light emitting device
JP2005026364A (en) Hybrid integrated circuit
JP4386552B2 (en) Structure of light emitting / receiving semiconductor device
JP4409074B2 (en) Semiconductor device
JP2002076161A (en) Surface mounting type semiconductor device
JPH05129505A (en) Lead frame for electronic-circuit-element mounting use
JP2002359336A (en) Semiconductor device
JP3951693B2 (en) Semiconductor light emitting device
JPH0451056B2 (en)
JPH06334059A (en) Semiconductor mounting board and production thereof