JP3708739B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP3708739B2
JP3708739B2 JP06173499A JP6173499A JP3708739B2 JP 3708739 B2 JP3708739 B2 JP 3708739B2 JP 06173499 A JP06173499 A JP 06173499A JP 6173499 A JP6173499 A JP 6173499A JP 3708739 B2 JP3708739 B2 JP 3708739B2
Authority
JP
Japan
Prior art keywords
film
silicon dioxide
dioxide film
barrier metal
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP06173499A
Other languages
Japanese (ja)
Other versions
JP2000260810A (en
Inventor
憲 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP06173499A priority Critical patent/JP3708739B2/en
Publication of JP2000260810A publication Critical patent/JP2000260810A/en
Application granted granted Critical
Publication of JP3708739B2 publication Critical patent/JP3708739B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Description

【０００１】
【発明の属する技術分野】
本発明は、二酸化シリコン膜上にバリアメタル膜を間に介在させて電極配線を設けるようにした半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
半導体装置は、搭載する機器等の小型高性能化に伴い微細化、高集積化されてきている。また、このような中で動作の高速化において、装置におけるＣＲ遅延が問題となっており、この問題の解消のために、静電容量の低減が行われている。
【０００３】
以下、従来技術を、図２を参照して説明する。図2は要部の断面図で、図２において、１は半導体基板であり、2は半導体基板1の上面に形成された層間絶縁膜の二酸化シリコン膜で、この二酸化シリコン膜2は、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌｏｘｙｓｉａｎｅ；Ｓｉ（ＯＣ２Ｈ５）４）ガスを主原料に使用したプラズマＣＶＤ法によって所定膜厚となるように堆積させている。さらに、二酸化シリコン膜2には、誘電率を低下させることによって静電容量が低減するよう、その形成プロセスの中でフッ素（Ｆ）を膜中に残存させるようにしている。
【０００４】
また、3は二酸化シリコン膜2上に成膜されたＴｉ／ＴｉＮ系のバリアメタル膜であり、バリアメタル膜３上には、Ａｌ−Ｃｕ合金でなる電極配線４が設けられている。なお、バリアメタル膜３は図示しないが二酸化シリコン膜２側に設けられたＴｉ膜と、電極配線４側に設けられたＴｉＮ膜とでなる二重膜の構成を取っている。そして、バリアメタル膜３は積層された後にコンタクト抵抗を低減するため、所定温度での熱処理が加えられる。
【０００５】
また、電極配線４上には絶縁保護膜５が被覆されており、この絶縁保護膜５の所定位置を開孔させ、その中に露出するパッド部６に回路への給電、あるいは信号の伝達等を行うためにリードワイヤ７が接続されている。この接続はパッド部６及びリードワイヤ７に対して熱、圧力、振動などの外力が加えられ、両者の境界面に組成変形を与え、拡散接合によって行われる。
【０００６】
しかしながら上記の従来技術においては、リードワイヤ７を接合する際に、あるいは接合後において、パット部６で二酸化シリコン膜２とバリアメタル膜３との界面近傍での密着強度が低くて接合強度不足となり、パッド剥がれ等が生じる場合がある。このため、装置の信頼性を向上させる上で、二酸化シリコン膜２の誘電率を低くしながらも、二酸化シリコン膜２とバリアメタル膜３の密着性を高める必要がある。
【０００７】
そこで、その要因を究明したところ、二酸化シリコン膜２上にバリアメタル膜３を形成した後の製造過程で、例えば４００℃〜５００℃程度の温度での、多数のアニール工程を経ることになる。そして、こうしたアニール工程を経ることで、誘電率低下のために二酸化シリコン膜2の中に残存させたフッ素が、二酸化シリコン膜２とバリアメタル膜３との界面に拡散し、弗化チタン（ＴｉＦ）が形成されて両膜の密着性が低下することが判明した。
【０００８】
【発明が解決しようとする課題】
上記のような状況に鑑みて本発明はなされたもので、その目的とするところはＣＲ遅延を改善すべく二酸化シリコン膜の誘電率を低くしながら、二酸化シリコン膜とバリアメタル膜との密着性を向上させることで、パット部におけるリードワイヤ接合強度を増加させ、パッド剥がれ等が生じる虞を少なくした信頼性の高い半導体装置およびその製造方法を提供することにある。
【０００９】
【課題を解決するための手段】
本発明の半導体装置およびその製造方法は、半導体基板上に形成された二酸化シリコン膜と、この二酸化シリコン膜上に成膜されたＴｉ／ＴｉＮ系のバリアメタル膜と、このバリアメタル膜上に設けられた電極配線とを備えてなる半導体装置において、二酸化シリコン膜が、それぞれプラズマＣＶＤで成膜され、ふっ素を残存させた第1の二酸化シリコン膜と第2の二酸化シリコン膜とでなると共に、バリアメタル膜側の第2の二酸化シリコン膜が、材料ガスにＳｉＨ４ガスを用いて成膜されていることを特徴とするものであり、
また、半導体基板上にふっ素を残存させながらプラズマＣＶＤにより第１の二酸化シリコン膜を形成する工程と、第１の二酸化シリコン膜上にモノシランガスを用い、ふっ素を残存させながらプラズマＣＶＤにより第２の二酸化シリコン膜を形成する工程と、第２の二酸化シリコン膜上にＴｉ／ＴｉＮ系バリアメタル膜を形成する工程と、バリアメタル膜の形成後に所定温度で熱処理する工程とを具備することを特徴とする方法である。
【００１０】
【発明の実施の形態】
以下本発明の一実施形態を、図１を参照して説明する。図１は要部の断面図で、図１において、１１は半導体基板であり、１2は半導体基板１1の上面に形成された層間絶縁膜の二酸化シリコン膜で、膜厚が８００ｎｍとなるように成膜されている。そして、この二酸化シリコン膜１2は、第１の二酸化シリコン膜１３と第２の二酸化シリコン膜１４とで構成されており、半導体基板１１側の第１の二酸化シリコン膜１３は、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌｏｘｙｓｉａｎｅ；Ｓｉ（ＯＣ２Ｈ５）４）ガスを主原料に使用したプラズマＣＶＤ法によって形成したもので、先ず、所要の膜厚となるように堆積した後、所定の膜厚の５００ｎｍとなるよう平坦化工程を経ることにより形成されている。
【００１１】
また、第１の二酸化シリコン膜１３上に設けられた第２の二酸化シリコン膜１４は、平坦化された第１の二酸化シリコン膜１３の上面に、モノシラン（ＳｉＨ４）ガスを主原料に使用し、Ｏ２、あるいはＮ２Ｏを用いたプラズマＣＶＤ法、例えば高周波放電プラズマＣＶＤ法、マイクロ波放電プラズマＣＶＤ法によって成膜されている。そして、この成膜によって形成された第２の二酸化シリコン膜１４の膜厚は、所定膜厚の３００ｎｍとなっている。さらに、第１の二酸化シリコン膜１３と第２の二酸化シリコン膜１４とで構成された二酸化シリコン膜１2は、各膜を形成する工程の中で、静電容量を低減させるために、誘電率が低下するようフッ素（Ｆ）を各膜中に残存させるようにしている。
【００１２】
また、１５は二酸化シリコン膜１2の第２の二酸化シリコン膜１４上に成膜されたＴｉ／ＴｉＮ系のバリアメタル膜であり、バリアメタル膜１５上には、Ａｌ−Ｃｕ合金でなる電極配線１６が設けられている。なお、バリアメタル膜１５は、図示しないがＴｉ膜と、ＴｉＮ膜とでなる二重膜の構成を取っている。そしてＴｉ膜は、第２の二酸化シリコン膜１４の上に蒸着によって所定の膜厚となるように形成されており、Ｔｉ膜の上にはＴｉＮ膜が蒸着によって所定の膜厚となるように形成されている。また、バリアメタル膜１５は積層された後にコンタクト抵抗を低減するため、例えば５００℃以上の所定温度を加えての熱処理が行われる。
【００１３】
またさらに、電極配線１６上には絶縁保護膜１７が被覆されており、この絶縁保護膜１７の所定位置を開孔させ、その中に露出するパッド部１８に回路への給電、あるいは信号の伝達等を行うためにリードワイヤ１９が接続されている。この接続はパッド部１８及びリードワイヤ１９に対して熱、圧力、振動などの外力が加えられ、両者の境界面に組成変形を与え、拡散接合によって行われる。
【００１４】
このように構成することによって、ＳｉＨ４ガスを主原料に用いたプラズマＣＶＤ法で形成した第２の二酸化シリコン膜１４が、バリアメタル膜１５に隣接することになる。そして、ＳｉＨ４ガスを主原料に用いたプラズマＣＶＤ法で形成した二酸化シリコン膜の方が、ＴＥＯＳガスを主原料に用いたプラズマＣＶＤ法で形成した二酸化シリコン膜よりも膜質が密になっている。
【００１５】
このため、後続する製造過程においてアニール工程を経ても、誘電率低下のために二酸化シリコン膜１2の中に残存させたフッ素が、隣接する第２の二酸化シリコン膜１４とバリアメタル膜１５との界面に拡散し難くなり、弗化チタンが形成され難くなって両膜の密着性が向上したものとなる。この結果、リードワイヤ１９を接合する際、あるいは接合後において、パット部１８での第２の二酸化シリコン膜１４とバリアメタル膜１５との界面近傍での密着強度が向上し接合強度が増加し、パッド剥がれ等は生じ難くなって、装置の信頼性が向上したものとなる。
【００１６】
【発明の効果】
以上の説明から明らかなように、本発明によれば、二酸化シリコン膜の誘電率を低くしてＣＲ遅延の問題を改善しながら、二酸化シリコン膜とバリアメタル膜との密着性が向上してパット部におけるリードワイヤ接合強度が増加し、パッド剥がれ等が生じる虞を少なくなり、装置の信頼性が高いものとなる等の効果を奏する。
【図面の簡単な説明】
【図１】本発明の一実施形態の要部を示す断面図である。
【図２】従来例の要部を示す断面図である。
【符号の説明】
１１…半導体基板
１２…二酸化シリコン膜
１３…第1の二酸化シリコン膜
１４…第2の二酸化シリコン膜
１５…バリアメタル膜
１６…電極配線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which an electrode wiring is provided on a silicon dioxide film with a barrier metal film interposed therebetween, and a manufacturing method thereof.
[0002]
[Prior art]
Semiconductor devices have been miniaturized and highly integrated along with downsizing and higher performance of equipment and the like to be mounted. In such a situation, the CR delay in the apparatus is a problem in increasing the operation speed. In order to solve this problem, the capacitance is reduced.
[0003]
Hereinafter, the prior art will be described with reference to FIG. 2 is a cross-sectional view of the main part. In FIG. 2, 1 is a semiconductor substrate, 2 is a silicon dioxide film of an interlayer insulating film formed on the upper surface of the semiconductor substrate 1, and this silicon dioxide film 2 is TEOS ( Tetraethyloxysilane; Si (OC 2 H 5 ) 4 ) gas is deposited so as to have a predetermined film thickness by plasma CVD using a main material. Further, in the silicon dioxide film 2, fluorine (F) is left in the film during the formation process so that the electrostatic capacity is reduced by lowering the dielectric constant.
[0004]
Reference numeral 3 denotes a Ti / TiN-based barrier metal film formed on the silicon dioxide film 2. On the barrier metal film 3, an electrode wiring 4 made of an Al—Cu alloy is provided. Although not shown, the barrier metal film 3 has a double film structure including a Ti film provided on the silicon dioxide film 2 side and a TiN film provided on the electrode wiring 4 side. The barrier metal film 3 is subjected to heat treatment at a predetermined temperature in order to reduce the contact resistance after being laminated.
[0005]
In addition, an insulating protective film 5 is coated on the electrode wiring 4, and a predetermined position of the insulating protective film 5 is opened, and power is supplied to the circuit or signal is transmitted to the pad portion 6 exposed therein. The lead wire 7 is connected to perform the above. This connection is made by diffusion bonding by applying external force such as heat, pressure, vibration or the like to the pad portion 6 and the lead wire 7 to cause composition deformation on the boundary surface between them.
[0006]
However, in the above prior art, when the lead wire 7 is bonded or after bonding, the adhesive strength in the vicinity of the interface between the silicon dioxide film 2 and the barrier metal film 3 is low at the pad portion 6 and the bonding strength is insufficient. , Pad peeling or the like may occur. For this reason, in order to improve the reliability of the device, it is necessary to improve the adhesion between the silicon dioxide film 2 and the barrier metal film 3 while reducing the dielectric constant of the silicon dioxide film 2.
[0007]
Therefore, the cause was investigated, and in the manufacturing process after the formation of the barrier metal film 3 on the silicon dioxide film 2, a number of annealing processes are performed at a temperature of about 400 ° C. to 500 ° C., for example. Through such an annealing process, the fluorine remaining in the silicon dioxide film 2 due to a decrease in the dielectric constant diffuses to the interface between the silicon dioxide film 2 and the barrier metal film 3, and titanium fluoride (TiF) It was found that the adhesion between the two films was reduced.
[0008]
[Problems to be solved by the invention]
The present invention has been made in view of the above situation, and its object is to reduce the dielectric constant of the silicon dioxide film while improving the CR delay, while maintaining the adhesion between the silicon dioxide film and the barrier metal film. It is an object of the present invention to provide a highly reliable semiconductor device and a method for manufacturing the same that increase the lead wire bonding strength in the pad portion and reduce the possibility of pad peeling and the like.
[0009]
[Means for Solving the Problems]
A semiconductor device and a manufacturing method thereof according to the present invention are provided with a silicon dioxide film formed on a semiconductor substrate, a Ti / TiN-based barrier metal film formed on the silicon dioxide film, and the barrier metal film. In the semiconductor device comprising the electrode wiring formed, each of the silicon dioxide films is formed by plasma CVD, and includes a first silicon dioxide film and a second silicon dioxide film in which fluorine is left , and a barrier. The second silicon dioxide film on the metal film side is formed using SiH 4 gas as a material gas,
Also, a step of forming a first silicon dioxide film by plasma CVD while leaving fluorine on the semiconductor substrate, and a second silicon dioxide by plasma CVD using monosilane gas on the first silicon dioxide film and leaving fluorine. A step of forming a silicon film; a step of forming a Ti / TiN-based barrier metal film on the second silicon dioxide film; and a step of performing a heat treatment at a predetermined temperature after the formation of the barrier metal film. Is the method.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view of the main part. In FIG. 1, 11 is a semiconductor substrate, 12 is a silicon dioxide film of an interlayer insulating film formed on the upper surface of the semiconductor substrate 11 and has a thickness of 800 nm. It is a membrane. The silicon dioxide film 12 is composed of a first silicon dioxide film 13 and a second silicon dioxide film 14, and the first silicon dioxide film 13 on the semiconductor substrate 11 side is TEOS (Tetraethyloxysilane; Si (OC 2 H 5 ) 4 ) formed by a plasma CVD method using a gas as a main raw material, first deposited to have a required film thickness, and then planarized to a predetermined film thickness of 500 nm. It is formed by going through.
[0011]
The second silicon dioxide film 14 provided on the first silicon dioxide film 13 uses a monosilane (SiH 4 ) gas as a main material on the upper surface of the planarized first silicon dioxide film 13. , O 2 , or N 2 O using a plasma CVD method such as a high frequency discharge plasma CVD method or a microwave discharge plasma CVD method. The film thickness of the second silicon dioxide film 14 formed by this film formation is a predetermined film thickness of 300 nm. Further, the silicon dioxide film 12 composed of the first silicon dioxide film 13 and the second silicon dioxide film 14 has a dielectric constant in order to reduce capacitance in the process of forming each film. Fluorine (F) is allowed to remain in each film so as to decrease.
[0012]
Reference numeral 15 denotes a Ti / TiN-based barrier metal film formed on the second silicon dioxide film 14 of the silicon dioxide film 12. The electrode wiring 16 made of an Al-Cu alloy is formed on the barrier metal film 15. Is provided. Although not shown, the barrier metal film 15 has a double film configuration including a Ti film and a TiN film. The Ti film is formed on the second silicon dioxide film 14 to have a predetermined film thickness by vapor deposition, and the TiN film is formed on the Ti film to have a predetermined film thickness by vapor deposition. Has been. Further, in order to reduce the contact resistance after the barrier metal film 15 is laminated, a heat treatment is performed by applying a predetermined temperature of, for example, 500 ° C. or higher.
[0013]
Further, an insulating protective film 17 is coated on the electrode wiring 16, and a predetermined position of the insulating protective film 17 is opened, and power is supplied to the circuit or signal is transmitted to the pad portion 18 exposed therein. A lead wire 19 is connected to perform the above. This connection is made by diffusion bonding by applying an external force such as heat, pressure, vibration or the like to the pad portion 18 and the lead wire 19 to give a compositional deformation to the interface between them.
[0014]
With this configuration, the second silicon dioxide film 14 formed by the plasma CVD method using SiH 4 gas as the main material is adjacent to the barrier metal film 15. The silicon dioxide film formed by the plasma CVD method using SiH 4 gas as the main material has a denser film quality than the silicon dioxide film formed by the plasma CVD method using TEOS gas as the main material. .
[0015]
For this reason, even if an annealing process is performed in the subsequent manufacturing process, the fluorine remaining in the silicon dioxide film 12 due to the decrease in the dielectric constant is the interface between the adjacent second silicon dioxide film 14 and the barrier metal film 15. It becomes difficult to diffuse into titanium and titanium fluoride is hardly formed, and the adhesion between both films is improved. As a result, when the lead wire 19 is bonded or after bonding, the adhesion strength in the vicinity of the interface between the second silicon dioxide film 14 and the barrier metal film 15 at the pad portion 18 is improved and the bonding strength is increased. Pad peeling or the like hardly occurs and the reliability of the apparatus is improved.
[0016]
【The invention's effect】
As is apparent from the above description, according to the present invention, the dielectric constant of the silicon dioxide film is lowered to improve the CR delay problem, and the adhesion between the silicon dioxide film and the barrier metal film is improved. As a result, there is an effect that the lead wire bonding strength in the portion is increased, the possibility of pad peeling or the like is reduced, and the reliability of the device is increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part of an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a main part of a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Silicon dioxide film 13 ... 1st silicon dioxide film 14 ... 2nd silicon dioxide film 15 ... Barrier metal film 16 ... Electrode wiring

Claims (3)

半導体基板上に形成された二酸化シリコン膜と、この二酸化シリコン膜上に成膜されたＴｉ／ＴｉＮ系のバリアメタル膜と、このバリアメタル膜上に設けられた電極配線とを備えてなる半導体装置において、前記二酸化シリコン膜が、それぞれプラズマＣＶＤで成膜され、ふっ素を残存させた第1の二酸化シリコン膜と第2の二酸化シリコン膜とでなると共に、バリアメタル膜側の前記第2の二酸化シリコン膜が、材料ガスにＳｉＨ４ガスを用いて成膜されていることを特徴とする半導体装置。A semiconductor device comprising a silicon dioxide film formed on a semiconductor substrate, a Ti / TiN-based barrier metal film formed on the silicon dioxide film, and an electrode wiring provided on the barrier metal film And the second silicon dioxide film on the barrier metal film side is formed of a first silicon dioxide film and a second silicon dioxide film, each of which is formed by plasma CVD and has fluorine remaining. A semiconductor device, wherein the film is formed using SiH 4 gas as a material gas. 第１の二酸化シリコン膜が、材料ガスにＴＥＯＳガスを用いて成膜されていることを特徴とする請求項1記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the first silicon dioxide film is formed by using TEOS gas as a material gas . 半導体基板上にふっ素を残存させながらプラズマＣＶＤにより第１の二酸化シリコン膜を形成する工程と、前記第１の二酸化シリコン膜上にモノシランガスを用い、ふっ素を残存させながらプラズマＣＶＤにより第２の二酸化シリコン膜を形成する工程と、前記第２の二酸化シリコン膜上にＴｉ／ＴｉＮ系バリアメタル膜を形成する工程と、前記バリアメタル膜の形成後に所定温度で熱処理する工程とを具備することを特徴とする半導体装置の製造方法。Forming a first silicon dioxide film by plasma CVD while leaving fluorine on the semiconductor substrate; and using the monosilane gas on the first silicon dioxide film and second silicon dioxide by plasma CVD while leaving fluorine. A step of forming a film, a step of forming a Ti / TiN-based barrier metal film on the second silicon dioxide film, and a step of performing a heat treatment at a predetermined temperature after the formation of the barrier metal film. A method for manufacturing a semiconductor device.
JP06173499A 1999-03-09 1999-03-09 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3708739B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06173499A JP3708739B2 (en) 1999-03-09 1999-03-09 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06173499A JP3708739B2 (en) 1999-03-09 1999-03-09 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2000260810A JP2000260810A (en) 2000-09-22
JP3708739B2 true JP3708739B2 (en) 2005-10-19

Family

ID=13179736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06173499A Expired - Lifetime JP3708739B2 (en) 1999-03-09 1999-03-09 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3708739B2 (en)

Also Published As

Publication number Publication date
JP2000260810A (en) 2000-09-22

Similar Documents

Publication Publication Date Title
JP2596331B2 (en) Semiconductor device and manufacturing method thereof
JP2000340569A (en) Wiring structre of semiconductor device and formation method thereof
JP3449333B2 (en) Method for manufacturing semiconductor device
JP3708739B2 (en) Semiconductor device and manufacturing method thereof
JP2937688B2 (en) Semiconductor device
US7151052B2 (en) Multiple etch-stop layer deposition scheme and materials
KR20050019033A (en) Semiconductor device and production method therefor
JPH0316145A (en) Manufacture of semiconductor device
US20040183197A1 (en) Semiconductor device including copper interconnect line and bonding pad, and method of manufacturing the same
JP2001176875A (en) Semiconductor device
JPH11121458A (en) Semiconductor device
JPH08125016A (en) Manufacture of semiconductor device
JPH04731A (en) Semiconductor device and manufacture thereof
KR100840880B1 (en) Semiconductor device and method for manufacture thereof
JPH0629294A (en) Manufacture of semiconductor device
JPH0778789A (en) Manufature of semiconductor device
JPH02186634A (en) Manufacture of integrated circuit device
KR100283480B1 (en) Metal wiring for semiconductor devices and its manufacturing method
JPH03112135A (en) Semiconductor device and manufacture thereof
JPH03209823A (en) Resin-sealed semiconductor device
JPH07147281A (en) Manufacture of semiconductor integrated circuit device
JPH0653270A (en) Semiconductor device
JPH07263553A (en) Production process of semiconductor device
JP2003309124A (en) Semiconductor device
JPH05175196A (en) Wiring structure of semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040830

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20040901

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050512

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050517

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050711

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050802

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050804

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090812

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090812

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100812

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100812

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110812

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110812

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120812

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120812

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130812

Year of fee payment: 8

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term