JP3703864B2 - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

Info

Publication number
JP3703864B2
JP3703864B2 JP20452394A JP20452394A JP3703864B2 JP 3703864 B2 JP3703864 B2 JP 3703864B2 JP 20452394 A JP20452394 A JP 20452394A JP 20452394 A JP20452394 A JP 20452394A JP 3703864 B2 JP3703864 B2 JP 3703864B2
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
containing metal
coating
conductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP20452394A
Other languages
Japanese (ja)
Other versions
JPH0851270A (en
Inventor
博明 佐竹
理稔 日比
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP20452394A priority Critical patent/JP3703864B2/en
Publication of JPH0851270A publication Critical patent/JPH0851270A/en
Application granted granted Critical
Publication of JP3703864B2 publication Critical patent/JP3703864B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/062Etching masks consisting of metals or alloys or metallic inorganic compounds
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【0001】
【産業上の利用分野】
本発明はダミーパターンを利用したプリント配線板の製造方法に関し、特には、そのプリント配線板の最外層にSn含有金属被膜およびAu被膜を有する導体回路を有し、製造途中において銅イオン含有溶液に接触させる工程を含んでなるプリント配線板の製造方法に関する。
【0002】
【従来の技術】
近年、半導体素子の高密度化・多機能化に伴って入出力ピン数の増加が著しい。一方で、このような半導体素子やパッケージを実装する方法においても、ピンなどのリードをプリント配線板のスルーホールに対して挿入固定する方法から、FCB(フリップ・チップ・ボンディング)やBGA(ボール・グリッド・アレイ)のように半田などのバンプによって直接接続したり、QFP(クワッド・フラット・パッケージ)やTAB(テープ・オートメイテッド・ボンディング)のように半田を用いてリードを表面実装したりする方法に移行しつつある。
【0003】
また、ワイヤーボンディングによって半導体素子を直接プリント配線板に電気接続するために接続用パッドにAu被膜を被覆したり、単に腐食防止のために最終的にソルダーレジストから露出する導体回路をAu被膜によって被覆する処理も行われている。
さらに、プリント配線板の製造工程において、半田やSnやAu被膜をエッチングレジストとして用いる工法も広く使われている。
従って、現状のプリント配線板や製造途中のプリント配線板にあっては、Sn含有金属被膜とAu被膜の両者が存在する場合が多々有るのである。
【0004】
特に、プリント配線板製造工程においては、上記のようにSn含有金属被膜とAu被膜の両者が存在する状態で、銅イオン含有溶液に接触させることがしばしば有る。具体的には、バンプを形成するためのSn含有金属被膜(Snあるいは半田)とSMD用パッド防錆処理のためのAu被膜の両者を金属銅被膜をエッチング除去するためのエッチングレジストとして使用する場合である。この際のエッチング液としては、例えばNH4 OH・HCl系があり、建浴当初から銅イオンを若干添加してある場合が多い。
【0005】
このようなエッチング液中にSn含有金属被膜とAu被膜の両者が存在するプリント配線板を浸積して、金属銅被膜をエッチングするのである。したがって、エッチングが進行し、エッチングされるべき金属銅被膜が無くなって導体回路が形成された時点において、それぞれ独立した導体回路において電位のばらつきが生じ、場合によってはSnが浸食されはじめる。そして、一方では、このSnが被覆された導体回路と電気的に接続しているAu被膜を有する導体回路表面には、エッチング液中に存在する銅イオンが金属となって析出することになる。
【0006】
【発明が解決しようとする課題】
このようにSnが溶けだして銅が析出するのであるから、エッチングレジストとしての役割を果たすべきものが無くなることとなり、その下層に存在する銅などの被膜がエッチング除去されて、導体回路が断線してしまうのである。また、Sn含有金属被膜が半田である場合には、Sn/Pb合金のSnのみが溶出し、Pb含有比率が著しく上昇して溶融温度が高くなり、熱処理によってリフローさせる際に、溶融しない不具合が発生する。また、Sn含有金属被膜をバンプとして使用する際には、高さおよびSn含有金属量が不均一となって接続不良を生ずる。
【0007】
そこで本発明の目的とするところは、Sn含有金属被膜とAu被膜の両者が存在するプリント配線板を、その製造途中において銅イオン含有溶液に接触させる工程を含んでいる場合においても、エッチングレジスト等として存在するSn含有金属被膜の溶解を低減し、断線、線欠けあるいは半田溶融不良あるいはSn含有金属被膜の厚み不均一などの不具合が発生しないプリント配線板の製造方法を提供することにある。
【0008】
【課題を解決するための手段】
上記の課題を解決するために本発明が採った方法は、「互いに電気的に導通し、表面にSn含有金属被膜(90)を有する第一の導体回路と表面にAu被膜(50)を有する第二の導体回路とを最外層に有するプリント配線板を銅イオン含有溶液に接触させる工程を含んで製造する方法において、
表面にSn含有金属被膜を有し、かつ、前記第一及び第二の導体回路に電気的に接続されると共に、その面積と前記第一の導体回路の面積との合計面積が前記第二の導体回路の面積の45%以上となるダミーパターンを設け、その状態で銅イオン含有溶液に接触させること」である。
【0009】
すなわち、互いに電気的に導通する、Sn含有金属被膜(90)とAu被膜(50)の両者が存在するプリント配線板を、その製造途中において銅イオン含有溶液(例えばNH4 OH・HClなどのエッチング液)に接触させる工程を含んでいる場合において、上記のSn含有金属被膜(90)とAu被膜(50)の両者に電気的に接続されたダミーパターン(60)を形成し、このダミーパターン(60)の表面にもSn含有金属被膜(90)を形成するのである。換言すれば、Sn含有金属被膜(90)とAu被膜(50)の両者が存在する電気的に導通する導体回路網において、Sn含有金属被膜の合計面積がAu被膜の面積の所定以上となるようにSn含有金属被膜(90)を有するダミーパターン(60)を設けた状態で、銅イオン含有溶液によって処理する工程を行うのである。
【0010】
また、Sn含有金属被膜(90)を形成されたダミーパターン(60)の表面積と本来必要とされてプリント配線板表面に形成されたSn含有金属被膜(90)を有する導体回路の表面積との和が、上記Au被膜(50)を有する導体回路の表面積の45%以上となることが肝要である。
【0011】
【作用】
上記のような手段を採ることによって、以下のような作用を奏する。
すなわち、銅イオン含有溶液内において、プリント配線板の各部分において僅かな電位差が生じ、所謂電池が形成されるのであるが、ダミーパターンの形成によってSn含有金属被膜を有する導体回路の表面積が飛躍的に増大し、単位面積当たりの一定時間内に溶出するSn量が激減する。したがって、エッチングレジスト等として存在するSn含有金属被膜はほぼそのまま維持されるので、断線、線欠けは発生しない。
【0012】
そして、Sn含有金属被膜が半田である場合においても、Sn/Pb組成が殆ど変化しないことからその溶融温度も変化しないこととなる。さらに、Sn含有金属被膜をバンプとして用いる場合においても、Sn含有金属被膜の厚みは均一であり、接続不良などの不具合が発生しないのである。
【0013】
尚、ダミーパターンは、製品有効範囲内に配置されたものであってもよく、また、製品有効範囲外に配置されたものであってもよく、溶出を抑制したいSn含有金属被膜を有する導体回路と電気的に接続されて配置されたものであれば良いのである。
【0014】
【実施例】
次に、本発明に係わる実施例について説明する。本実施例のプリント配線板は、半導体素子を直接接続固定(所謂フリップチップボンディング)するための半田によって形成されたバンプと、半導体素子をプリント配線板に実装固定したのちに金線などの細線によって電気的に接続する(所謂ワイヤーボンディング)ためのAuめっき被膜が施されたパッドとを有したプリント配線板である。そして、上記半田バンプとパッドとが共に電気的に導通した同一導体回路上に存在する場合には、この導体回路と電気的に接続する半田めっき(その他のSn含有金属被膜であってもよい)によって被覆されたダミーパターンを有しているのである。さらに、このダミーパターンは、その面積と電気的に導通する半田バンプの面積との合計が、電気的に導通するAuめっき被膜が施された導体回路(パッドおよび回路)の面積の45%以上となっている。
【0015】
このプリント配線板は、半田からなるバンプを形成するに当たって、半田のSn/Pbの組成をより設計値に近く、また、均一に形成する必要があることから電界めっき法を用いている。この電界めっきも導体回路をめっきリードとして用いるものではなく、導体回路形成が終了したプリント配線板表面に無電解Cuめっきを全面に施し、この無電解Cuめっきを半田めっきのためのめっきリードとするものである。したがって、半田バンプが完成後において上記の無電解Cuめっきからなるめっきリードを、アンモニア系のエッチング液によってエッチング除去しなければならないものである。このアンモニア系のエッチング液によるCu被膜のエッチングの際に、既に形成された導体回路をエッチング液から保護するのがバンプを形成する半田めっきであり、さらに、ワイヤーボンディングのためのパッド表面およびそのた導体回路表面を被覆するAuめっき被膜なのである。
【0016】
次いで、本発明をさらに詳しく説明するために、このプリント配線板の製造方法を順を追って説明する。
(1)厚み0.2mmのガラス・エポキシ基材(10)に対してN/Cドリル加工によって貫通孔を形成し、パネルめっきを行うことによって前記貫通孔をスルーホール(20)とした(図1)。次いで、導体を選択的にエッチングすることによって導体回路(30)を形成し(図2)、表面実装のためのパッドなどを除いてソルダーレジスト(40)で被覆・保護した(図3)。
(2)次いで、ソルダーレジスト(40)から露出した導体回路(30)表面に、Ni/Auめっき(50)を施した(図4)。
【0017】
このプリント配線板は、半導体素子とフリップチップボンディングによって接続されるパッドと、半導体素子とワイヤーボンディングによって接続されるパッドとがスルーホール(20)によって電気的に接続された回路となっている。また、この回路網には表面に本発明の特徴であるSn含有金属被膜が形成されるダミーパターン(60)も接続されている。このダミーパターン(60)と半導体素子とフリップチップボンディングによって接続されるパッドとの合計面積は、半導体素子とワイヤーボンディングによって接続されるパッドの面積の45%であった。
【0018】
(3)次いで、上記プリント配線板全体に厚み0.5μmの無電解Cuめっき(70)を施し(図5)、所定の部分に感光性めっきレジスト(80)を被覆した(図6)のちに、電解半田めっき(90)を施した(図7)。
(4)次いで、半田めっき(90)のためのめっきレジスト(80)を剥離し(図8)、NH4 OH・HCl溶液によって露出している無電解Cuめっき(70)をエッチング除去した(図9)。
【0019】
以上のように製造するプリント配線板の製造方法においては、ダミーパターンの形成によってSn含有金属被膜を有する導体回路の表面積が飛躍的に増大し、単位面積当たりの一定時間内に溶出するSn量が激減する。したがって、エッチングレジスト等として存在するSn含有金属被膜はほぼそのまま維持されるので、断線、線欠けは発生しない。そして、Sn含有金属被膜が半田である場合においても、Sn/Pb組成が殆ど変化しないことからその溶融温度も変化しないこととなる。さらに、Sn含有金属被膜をバンプとして用いる場合においても、Sn含有金属被膜の厚みは均一であり、接続不良などの不具合が発生しないのである。
【0020】
このように、互いに電気的に導通する、Sn含有金属被膜とAu被膜の両者が存在するプリント配線板を、その製造途中において銅イオン含有溶液に接触させる工程を含んでいる場合において、エッチングレジスト等として存在するSn含有金属被膜の溶解を低減し、導体回路の断線や線欠けが無く、またリフローの際の半田溶融が良好で、またSn含有金属被膜の厚みが均一なプリント配線板を容易に、且つ、多額の費用を要する装置の改造をしないで提供できる。
【0021】
尚、ダミーパターンは、製品有効範囲内に配置されたものであってもよく、また、製品有効範囲外に配置されたものであってもよく、溶出を抑制したいSn含有金属被膜を有する導体回路と電気的に接続されて配置されたものであれば良いのである。
【0022】
【発明の効果】
互いに電気的に導通する、Sn含有金属被膜とAu被膜の両者が存在するプリント配線板を、その製造途中において銅イオン含有溶液に接触させる工程を含んでいる場合において、エッチングレジスト等として存在するSn含有金属被膜の溶解を低減し、導体回路の断線や線欠けが無く、またリフローの際の半田溶融が良好で、またSn含有金属被膜の厚みが均一なプリント配線板を容易に、且つ、多額の費用を要する装置の改造をしないで提供できる。
【図面の簡単な説明】
【図1】本発明の実施例の第1工程を示す部分断面図である。
【図2】本発明の実施例の第1工程を示す部分断面図である。
【図3】本発明の実施例の第1工程を示す部分断面図である。
【図4】本発明の実施例の第2工程を示す部分断面図である。
【図5】本発明の実施例の第3工程を示す部分断面図である。
【図6】本発明の実施例の第3工程を示す部分断面図である。
【図7】本発明の実施例の第4工程を示す部分断面図である。
【図8】本発明の実施例の第4工程を示す部分断面図である。
【図9】本発明の実施例によって製造されたプリント配線板を示す部分断面図である。
【符号の説明】
10----基材 20----スルーホール 30----導体回路
40----ソルダーレジスト 50----Auめっき 60----ダミーパターン
70----無電解Cuめっき 80----めっきレジスト 90----半田めっき
[0001]
[Industrial application fields]
The present invention relates to a method of manufacturing a printed wiring board using a dummy pattern, and in particular, has a conductor circuit having a Sn-containing metal film and an Au film on the outermost layer of the printed wiring board, The present invention relates to a method for manufacturing a printed wiring board including a step of contacting.
[0002]
[Prior art]
In recent years, the number of input / output pins has increased remarkably with the increase in density and functionality of semiconductor devices. On the other hand, in the method of mounting such semiconductor elements and packages, FCB (flip chip bonding) and BGA (ball Direct connection by bumps such as solder as in a grid array, or surface mounting of leads using solder such as QFP (quad flat package) or TAB (tape automated bonding) It is moving to.
[0003]
Also, an Au coating is coated on the connection pad to electrically connect the semiconductor element directly to the printed wiring board by wire bonding, or the conductor circuit finally exposed from the solder resist is simply coated with the Au coating to prevent corrosion. The process to do is also performed.
Further, a method of using solder, Sn, or Au coating as an etching resist is widely used in the manufacturing process of printed wiring boards.
Therefore, there are many cases where both the Sn-containing metal coating and the Au coating are present in the current printed wiring board and the printed wiring board being manufactured.
[0004]
In particular, in the printed wiring board manufacturing process, the copper ion-containing solution is often brought into contact with both the Sn-containing metal coating and the Au coating as described above. Specifically, when both Sn-containing metal coating (Sn or solder) for forming bumps and Au coating for SMD pad rust prevention treatment are used as etching resists for removing the metal copper coating by etching. It is. As an etchant at this time, for example, NH 4 OH · HCl is used, and copper ions are often added a little from the beginning of the bath.
[0005]
In such an etching solution, a printed wiring board in which both the Sn-containing metal coating and the Au coating are present is immersed to etch the metal copper coating. Therefore, when the etching progresses and there is no metal copper film to be etched and a conductor circuit is formed, potential variations occur in the independent conductor circuits, and Sn begins to be eroded in some cases. On the other hand, copper ions present in the etching solution are deposited as metal on the surface of the conductor circuit having the Au coating electrically connected to the conductor circuit coated with Sn.
[0006]
[Problems to be solved by the invention]
Since Sn is melted and copper is precipitated in this way, there is no longer any role to serve as an etching resist, and the copper film existing underneath is removed by etching, and the conductor circuit is disconnected. It ends up. Further, when the Sn-containing metal coating is solder, only Sn of the Sn / Pb alloy is eluted, the Pb content ratio is remarkably increased, the melting temperature is increased, and there is a problem that it does not melt when reflowed by heat treatment. appear. Further, when the Sn-containing metal coating is used as a bump, the height and the amount of Sn-containing metal are not uniform, resulting in poor connection.
[0007]
Therefore, an object of the present invention is to provide an etching resist or the like even in a case where a printed wiring board in which both a Sn-containing metal coating and an Au coating are present is brought into contact with a copper ion-containing solution during its production. It is an object of the present invention to provide a method for producing a printed wiring board that reduces the dissolution of the Sn-containing metal coating existing as described above and does not cause defects such as disconnection, wire chipping, poor solder melting, or uneven thickness of the Sn-containing metal coating.
[0008]
[Means for Solving the Problems]
The method taken by the present invention to solve the above-mentioned problems is as follows. “A first conductive circuit which is electrically connected to each other and has a Sn-containing metal coating (90) on the surface and an Au coating (50) on the surface. In the method of manufacturing including the step of bringing the printed wiring board having the second conductor circuit in the outermost layer into contact with the copper ion-containing solution,
It has a Sn-containing metal coating on the surface and is electrically connected to the first and second conductor circuits, and the total area of the area and the area of the first conductor circuit is the second area. “A dummy pattern that is 45% or more of the area of the conductor circuit is provided, and in that state, the dummy pattern is brought into contact with the copper ion-containing solution ”.
[0009]
That is, a printed wiring board in which both the Sn-containing metal coating (90) and the Au coating (50) are electrically connected to each other is etched during the production of a copper ion-containing solution (for example, NH 4 OH · HCl). A dummy pattern (60) electrically connected to both the Sn-containing metal film (90) and the Au film (50) is formed, and this dummy pattern ( The Sn-containing metal film (90) is also formed on the surface of 60). In other words, in the electrically conductive conductor network in which both the Sn-containing metal coating (90) and the Au coating (50) are present, the total area of the Sn-containing metal coating is equal to or greater than the predetermined area of the Au coating. In the state where the dummy pattern (60) having the Sn-containing metal coating (90) is provided on the substrate, the step of processing with the copper ion-containing solution is performed.
[0010]
Further, the sum of the surface area of the dummy pattern (60) formed with the Sn-containing metal film (90) and the surface area of the conductor circuit having the Sn-containing metal film (90) formed on the surface of the printed wiring board as originally required. However, it is important that the surface area of the conductor circuit having the Au coating (50) is 45% or more.
[0011]
[Action]
By taking the above-described means, the following effects are obtained.
That is, a slight potential difference occurs in each part of the printed wiring board in the copper ion-containing solution, so that a so-called battery is formed, but the surface area of the conductor circuit having the Sn-containing metal film is dramatically increased by forming the dummy pattern. The amount of Sn eluting within a certain time per unit area is drastically reduced. Therefore, since the Sn-containing metal film existing as an etching resist or the like is maintained almost as it is, no disconnection or chipping occurs.
[0012]
Even when the Sn-containing metal coating is solder, the Sn / Pb composition hardly changes, so the melting temperature does not change. Further, even when the Sn-containing metal film is used as a bump, the Sn-containing metal film has a uniform thickness and does not cause problems such as poor connection.
[0013]
The dummy pattern may be disposed within the product effective range, or may be disposed outside the product effective range, and the conductor circuit having the Sn-containing metal coating that is desired to suppress elution. As long as it is electrically connected and arranged.
[0014]
【Example】
Next, examples according to the present invention will be described. The printed wiring board of this embodiment is composed of bumps formed by solder for directly connecting and fixing semiconductor elements (so-called flip chip bonding), and fine wires such as gold wires after the semiconductor elements are mounted and fixed on the printed wiring board. It is a printed wiring board having a pad provided with an Au plating film for electrical connection (so-called wire bonding). When the solder bump and the pad are both on the same conductor circuit that is electrically conductive, solder plating (other Sn-containing metal coating may be used) that is electrically connected to the conductor circuit. It has a dummy pattern covered with. Further, the dummy pattern has a total area of 45% or more of the area of the conductive circuit (pad and circuit) coated with the electrically conductive Au plating film, and the total area of the solder bump and the electrically conductive solder bump. It has become.
[0015]
This printed wiring board uses an electroplating method because, when forming bumps made of solder, the Sn / Pb composition of the solder is closer to the design value and needs to be formed uniformly. This electric field plating does not use a conductor circuit as a plating lead, but electroless Cu plating is applied to the entire surface of the printed wiring board after the formation of the conductor circuit, and this electroless Cu plating is used as a plating lead for solder plating. Is. Therefore, after the solder bump is completed, the plating lead made of the electroless Cu plating must be removed by etching with an ammonia-based etching solution. When etching the Cu film with this ammonia-based etchant, it is solder plating that forms bumps to protect the already formed conductor circuit from the etchant. This is an Au plating film covering the surface of the conductor circuit.
[0016]
Next, in order to describe the present invention in more detail, the method for manufacturing the printed wiring board will be described step by step.
(1) A through-hole was formed by N / C drilling on a glass / epoxy substrate (10) having a thickness of 0.2 mm, and panel plating was performed to form the through-hole (20) (see FIG. 1). Next, a conductor circuit (30) was formed by selectively etching the conductor (FIG. 2), and covered and protected with a solder resist (40) except for pads for surface mounting (FIG. 3).
(2) Next, Ni / Au plating (50) was applied to the surface of the conductor circuit (30) exposed from the solder resist (40) (FIG. 4).
[0017]
This printed wiring board is a circuit in which a pad connected to a semiconductor element by flip chip bonding and a pad connected to the semiconductor element by wire bonding are electrically connected by a through hole (20). In addition, a dummy pattern (60) on which a Sn-containing metal film that is a feature of the present invention is formed is connected to the circuit network. The total area of the dummy pattern (60), the pad connected to the semiconductor element by flip chip bonding, was 45% of the area of the pad connected to the semiconductor element by wire bonding.
[0018]
(3) Next, electroless Cu plating (70) having a thickness of 0.5 μm is applied to the entire printed wiring board (FIG. 5), and a predetermined portion is coated with a photosensitive plating resist (80) (FIG. 6). Then, electrolytic solder plating (90) was performed (FIG. 7).
(4) Next, the plating resist (80) for the solder plating (90) is peeled off (FIG. 8), and the electroless Cu plating (70) exposed by the NH 4 OH / HCl solution is removed by etching (FIG. 8). 9).
[0019]
In the method for manufacturing a printed wiring board manufactured as described above, the surface area of the conductor circuit having the Sn-containing metal film increases dramatically due to the formation of the dummy pattern, and the amount of Sn eluting within a certain time per unit area is reduced. Decrease drastically. Therefore, since the Sn-containing metal film existing as an etching resist or the like is maintained almost as it is, no disconnection or chipping occurs. Even when the Sn-containing metal coating is solder, the Sn / Pb composition hardly changes, so the melting temperature does not change. Further, even when the Sn-containing metal film is used as a bump, the Sn-containing metal film has a uniform thickness and does not cause problems such as poor connection.
[0020]
Thus, in the case of including a step of bringing a printed wiring board in which both the Sn-containing metal coating and the Au coating are present, which are electrically conductive with each other, into contact with a copper ion-containing solution in the course of its manufacture, an etching resist or the like As a result, it is possible to reduce the dissolution of the Sn-containing metal coating, to prevent the breakage or chipping of the conductor circuit, to improve the solder melting during reflow, and to easily produce a printed wiring board with a uniform Sn-containing metal coating thickness. And it can provide without remodeling the apparatus which requires large expense.
[0021]
The dummy pattern may be disposed within the product effective range, or may be disposed outside the product effective range, and the conductor circuit having the Sn-containing metal coating that is desired to suppress elution. As long as it is electrically connected and arranged.
[0022]
【The invention's effect】
Sn that exists as an etching resist or the like in the case of including a step of bringing a printed wiring board that is electrically conductive with each other and in which both a Sn-containing metal coating and an Au coating are present, into contact with a copper ion-containing solution during its production Reduces the dissolution of the metal coating film, eliminates breakage or chipping of the conductor circuit, and facilitates the melting of the solder during reflow, and makes the printed wiring board with a uniform Sn-containing metal film thickness easy and expensive. It can be provided without remodeling the equipment which requires cost.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view showing a first step of an embodiment of the present invention.
FIG. 2 is a partial cross-sectional view showing a first step of an embodiment of the present invention.
FIG. 3 is a partial cross-sectional view showing a first step of an embodiment of the present invention.
FIG. 4 is a partial cross-sectional view showing a second step of the embodiment of the present invention.
FIG. 5 is a partial sectional view showing a third step in the embodiment of the present invention.
FIG. 6 is a partial sectional view showing a third step in the embodiment of the present invention.
FIG. 7 is a partial sectional view showing a fourth step in the embodiment of the present invention.
FIG. 8 is a partial sectional view showing a fourth step in the embodiment of the present invention.
FIG. 9 is a partial cross-sectional view showing a printed wiring board manufactured according to an embodiment of the present invention.
[Explanation of symbols]
10 ---- Substrate 20 ---- Through hole 30 ---- Conductor circuit
40 ---- Solder resist 50 ---- Au plating 60 ---- Dummy pattern
70 ---- Electroless Cu plating 80 ---- Plating resist 90 ---- Solder plating

Claims (1)

互いに電気的に導通し、表面にSn含有金属被膜を有する第一の導体回路と表面にAu被膜を有する第二の導体回路とを最外層に有するプリント配線板を銅イオン含有溶液に接触させる工程を含んで製造する方法において、
表面にSn含有金属被膜を有し、かつ、前記第一及び第二の導体回路に電気的に接続されると共に、その面積と前記第一の導体回路の面積との合計面積が前記第二の導体回路の面積の45%以上となるダミーパターンを設け、その状態で銅イオン含有溶液に接触させることを特徴とするプリント配線板の製造方法。
A step of bringing a printed wiring board which is electrically connected to each other and has a first conductor circuit having a Sn-containing metal coating on the surface and a second conductor circuit having an Au coating on the surface into contact with a copper ion-containing solution. In the manufacturing method including
It has a Sn-containing metal coating on the surface and is electrically connected to the first and second conductor circuits, and the total area of the area and the area of the first conductor circuit is the second area. A method for producing a printed wiring board, comprising: providing a dummy pattern that is 45% or more of an area of a conductor circuit; and bringing the dummy pattern into contact with a copper ion-containing solution in that state .
JP20452394A 1994-08-06 1994-08-06 Method for manufacturing printed wiring board Expired - Fee Related JP3703864B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20452394A JP3703864B2 (en) 1994-08-06 1994-08-06 Method for manufacturing printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20452394A JP3703864B2 (en) 1994-08-06 1994-08-06 Method for manufacturing printed wiring board

Publications (2)

Publication Number Publication Date
JPH0851270A JPH0851270A (en) 1996-02-20
JP3703864B2 true JP3703864B2 (en) 2005-10-05

Family

ID=16491950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20452394A Expired - Fee Related JP3703864B2 (en) 1994-08-06 1994-08-06 Method for manufacturing printed wiring board

Country Status (1)

Country Link
JP (1) JP3703864B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19781578C2 (en) * 1997-08-22 2001-11-15 Mitsubishi Paper Mills Ltd Imaging material, imaging method, method of making a lithographic printing plate and equipment used therefor, method of making a plate for a lithographic printing plate and method of making a printed wiring board

Also Published As

Publication number Publication date
JPH0851270A (en) 1996-02-20

Similar Documents

Publication Publication Date Title
US6864586B2 (en) Padless high density circuit board
EP0373241B1 (en) Film carrier and method of manufacturing same
US6259608B1 (en) Conductor pattern for surface mount devices and method therefor
EP0536418A1 (en) Semiconductor device and manufacturing method therefor
JPH0997791A (en) Bump structure, formation of bump and installation connection body
US5446625A (en) Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface
US5525204A (en) Method for fabricating a printed circuit for DCA semiconductor chips
JP3345529B2 (en) Wire bonding terminal, method of manufacturing the same, and method of manufacturing semiconductor mounting substrate using the wire bonding terminal
US6381837B1 (en) Method for making an electronic circuit assembly
JP2005057264A (en) Packaged electric structure and its manufacturing method
JP3703864B2 (en) Method for manufacturing printed wiring board
JP2001118872A (en) Bump-forming method
JPH09153519A (en) Structure for mounting semiconductor
US7321172B2 (en) Selective plating of package terminals
EP0042943A1 (en) Multilayer integrated circuit substrate structure and process for making such structures
KR20020042524A (en) Process for the production of solderable and functional surfaces on circuit carriers
JP2501174B2 (en) Method for manufacturing surface mount terminal
JP3191617B2 (en) Lead frame and semiconductor device using the same
JP3275413B2 (en) Lead frame and manufacturing method thereof
US6924440B2 (en) Printed wiring board, apparatus for electrically connecting an electronic element and a substrate, and method for manufacturing a printed wiring board
JP2974840B2 (en) Semiconductor element mounting method
KR100233864B1 (en) Input and output bump forming method of area array bumped semiconductor package using lead frame
JPH10294549A (en) Manufacture of printed wiring board and printed wiring board
JP2001352005A (en) Wiring board and semiconductor device
TW551011B (en) High-density circuit board without bonding pad design and the manufacturing method thereof

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20041110

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20041130

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20050128

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050128

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050128

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050705

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050721

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080729

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090729

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100729

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110729

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120729

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120729

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130729

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees