JP3697211B2

JP3697211B2 - Silicon carbide semiconductor element and method for forming insulating film thereof

Info

Publication number: JP3697211B2
Application number: JP2002003834A
Authority: JP
Inventors: 正人吉川; 久義伊藤; 真北畠; 賢哉山下; 修楠本; 正雄内田; 邦方高橋; 良子宮永
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 2002-01-10
Filing date: 2002-01-10
Publication date: 2005-09-21
Anticipated expiration: 2022-01-10
Also published as: JP2003209251A

Description

【０００１】
【発明の属する技術分野】
本発明は、炭化珪素により構成される炭化珪素半導体素子、特にパワーMOS半導体素子のゲート絶縁膜及びその形成方法に関する物で、特に、高速・高耐圧・低損失のパワー半導体素子を実現可能にするものである。
【０００２】
【従来の技術】
従来例１として述べる従来の炭化珪素により構成される絶縁ゲート型半導体素子２１は、図２のごとく、ｎ型の基板２２上にｎ型のエピタキシャル成長層（ｎ型層）２３を形成し、その一部に例えばAlの様なｐ型半導体を形成する不純物を拡散又はイオン打ち込みすることによりｐ型の部分２４を形成し、ｐ型の部分の表面近傍の一部に例えばNの様なｎ型半導体を形成する不純物を拡散又はイオン打ち込みすることによりｎ型の部分２５を形成する。上記ｎ型層２３が表面に達している部分と上記ｎ型の部分２５とに挟まれたｐ型の部分２４の表面に酸化絶縁膜２６を形成し、更にその表面にゲート電極２７aを設ける。ドレイン電極２7cは基板裏面に形成し、ソース電極２7bはｎ型の部分２５、ｐ型の部分２４にコンタクトして形成される。この絶縁ゲート型半導体素子は、ゲート電極２7aへのバイアスによってｐ型の部分２４の表面に形成される反転層がチャンネルとして作用して機能する。
【０００３】
この従来技術の内容は、例えば Silicon Carbide; A Review of Fundamental Questions and Applications to Current Device Technology, edited by W.J.Choyke,H.Matsunami, and G.Pensl, Akademie Verlag 1997 の Vol.II pp.369-388 に開示されている。炭化珪素半導体素子は、炭化珪素が有する物性の、ワイドギャップ性・高絶縁耐圧・十分な移動度・高い熱伝導性を生かして、低損失の高温でも動作する省エネルギーに寄与する半導体素子を提供することが期待されている。
【０００４】
しかし、従来の炭化珪素半導体素子、特にMOSFET等の酸化絶縁膜/炭化珪素界面を含む半導体素子は、上記酸化絶縁膜/炭化珪素界面の特性が不十分で、実用に耐えるモノではなかった。上記絶縁ゲート型半導体素子を形成する場合にチャンネル部の表面に形成される酸化絶縁膜2６は、イオン打ち込み等で素子パターンが形成された炭化珪素基板を酸化処理することにより形成される。更に、酸化絶縁膜を形成した後の酸化絶縁膜を形成した場合の温度よりも低温での酸素を含む雰囲気での処理をする再酸化アニールが、酸化絶縁膜及び酸化絶縁膜/炭化珪素界面を高性能化することは報告されている。
【０００５】
このような従来の酸化膜形成法は、例えば文献P-type SiC MOS reliability with improved oxidation procedures and aluminum or boron p-type dopants, L.A.Lipkin and J.W.Palmour , proceedings of high temperature electronics XIV-15-XIV-20にもあるように、酸化温度よりも低い温度の酸化雰囲気に、形成された酸化膜を曝し、界面近傍に存在する残留不純物を再度酸化して電気特性低下の原因となる界面準位密度を減少させようとする試み（再酸化）である。これまで再酸化に利用する温度は一種類に限られていた。
【０００６】
これらの従来の炭化珪素半導体素子の絶縁膜の形成方法は、酸化絶縁膜/炭化珪素界面の界面準位密度を減少させることは確かであるが、半導体素子として十分な界面準位密度までには、更にもう一桁以上の減少が必要で、絶縁膜の形成方法としては不十分であった。更に耐圧に関しても、１MVcm^-1以下の場合が多く、不十分であった。高耐圧素子実現のためには10MVcm^-1程度の耐圧は必要である。また、上記従来例の酸化絶縁膜/炭化珪素界面の界面準位密度Ｎｉｔは１×１０¹³ｃｍ^-2以上有り、この絶縁膜を用いて形成した図２の炭化珪素半導体素子ＭＯＳＦＥＴは、１０ｃｍ²／Ｖｓ程度の低いチャンネル移動度を示し、実用に耐えるような半導体素子のためには不十分であった。
【０００７】
【発明が解決しようとする課題】
実用に耐える炭化珪素半導体素子実現のためには、最低でも２×１０¹²ｃｍ^-2以下の界面準位密度Ｎｉｔ、１００ｃｍ²／Ｖｓ以上のチャンネル移動度が必要である。このチャンネル移動度が達成されれば、ＭＯＳＦＥＴのチャンネル抵抗が減少して、数百ボルト耐圧のパワー素子の場合のドリフト移動度とコンパラになり、パワー素子として実用に耐える半導体素子となる。
【０００８】
この従来技術の課題を克服し、本発明は、炭化珪素などのワイドギャップ半導体の性質を生かした低損失・高耐圧半導体素子を実現することを目的とする。
【０００９】
【課題を解決するための手段】
上記従来例において、酸化絶縁膜の絶縁耐圧が小さく不十分であること、および準位密度が大きく不十分であることに対して、本発明者らが検討した結果、次のようなことが明らかとなった。つまり、現在使用されている炭化珪素半導体基板の表面がα-SiC(0001)offcut面を用いており、表面にα-SiC(0001)テラスと(1-210)ステップを含むことが、絶縁耐圧が低く準位密度が大きいことの原因となっていることを、本発明者らは発見し、この発見に基づき本発明の絶縁膜の形成方法を発明した。
【００１０】
α-SiC(0001)面(Si面)と(1-210)面において、酸化速度が異なることは、例えばSilicon Carbide; A Review of Fundamental Questions and Applications to Current Device Technology, edited by W.J.Choyke,H.Matsunami, and G.Pensl, Akademie Verlag 1997 の Vol.II pp.369-388 に開示されており知られているが、酸化絶縁膜/炭化珪素界面の特性に対しての評価は不十分であった。酸化絶縁膜の形成方法に対しても、その評価に基づいた最適化はされておらず、本発明者らによって初めて明らかとなった評価結果に基づき、最適な絶縁膜の形成方法が確立され、さらにこれを用いた従来無かった炭化珪素半導体素子が発明された。
【００１１】
本発明の炭化珪素半導体素子は、２原子層（モノレイヤー）以上の高さを有するステップを含む炭化珪素基板と、上記炭化珪素基板表面に形成された酸化膜を含み、酸化膜と炭化珪素の界面準位密度Ｎｉｔが１．５×10¹²ｃｍ^-2以下であることを特徴とする。
【００１２】
上記発明の炭化珪素半導体素子において、２原子層以上の高さを有するステップを含む炭化珪素基板が、β-SiC(111)、6H,4H等のα-SiC(0001)、15R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα-SiC(1-100)及び／又はα-SiC(11-20)の内から選ばれる結晶面の１度以上のオフカット面を表面とする炭化珪素基板であると好ましい。
【００１３】
本発明の炭化珪素半導体素子の絶縁膜の形成方法は、２原子層以上の高さを有するステップを含む炭化珪素基板と、上記炭化珪素基板表面に形成された酸化膜を含む炭化珪素半導体素子を、酸素を含む雰囲気下で複数の設定温度に保ってアニール処理を施す炭化珪素半導体素子の絶縁膜の形成方法であって、１回目のアニール処理に続いて、上記１回目のアニール処理設定温度よりも低い設定温度で２回目のアニール処理を施し、少なくとも２つ以上の異なる設定温度で保たれた酸素を含む雰囲気下でのn回(n≧２)のアニール処理を含むことを特徴とする。
【００１４】
上記発明の炭化珪素半導体素子の絶縁膜の形成方法において、１回目の酸素を含む雰囲気下でのアニール処理が９００℃以上であり、設定温度が８５０℃以下であるｎ回目のアニール処理を少なくとも含むと好ましい。
【００１５】
さらに上記発明の炭化珪素半導体素子の絶縁膜の形成方法において、少なくともｎ回目の酸素を含む雰囲気下でのアニール処理がウェット酸素雰囲気であることと好ましい。
【００１６】
【発明の実施の形態】
本発明の炭化珪素半導体素子は、図１(a)の絶縁膜/炭化珪素界面の拡大図に示したような、２原子層以上の高さを有するステップ２を含む炭化珪素基板１と、上記炭化珪素基板表面に形成された酸化膜４を含み、酸化絶縁膜４と炭化珪素１の界面３での界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下であることを特徴とする絶縁膜４を含むことを特徴とする。
【００１７】
２モノレイヤー以上の高さを有するステップ２を含むオフカット炭化珪素基板１を利用した半導体素子、特に高パワー用の縦型絶縁ゲート型半導体素子(MOSFET)において、上記絶縁膜/炭化珪素の低い界面準位密度は、本発明により初めて実現されたもので、界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下の範囲でチャンネル抵抗がドリフト抵抗と同レベルとなることが初めて確認された。
【００１８】
この低界面準位密度の絶縁膜／炭化珪素界面を利用することにより、大電流制御可能なＭＯＳ半導体素子が実現できることを確認した。界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以上となると、ＭＯＳＦＥＴ半導体素子を形成した場合に、チャンネル抵抗がドリフト抵抗よりも一桁以上大きくなり、損失が大きくなり、大電流制御パワー半導体素子として適さないことを確認した。
【００１９】
上記本発明の炭化珪素半導体素子において、２原子層以上の高さを有するステップを含む炭化珪素基板が、β-SiC(111)、6H,4H等のα-SiC(0001)、１５R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα-SiC(1-100)及び／又はα-SiC(11-20)の内から選ばれる結晶面の１度以上のオフカット面を表面とする炭化珪素基板であると好ましいことを確認した。ここで、オフカットの角度が１度以下の基板に対しては良好な結晶性のエピタキシャル膜を成長させることが難しいため、好ましくなかった。また、オフカットの角度が１０度以下の基板に対して本発明の実現が容易であることを確認した。ここで炭化珪素基板の１０度以上のオフ角度については良好なエピタキシャル膜を得ることが難しく、本発明の良好な絶縁膜を形成することも難しい場合があった。
【００２０】
本発明の炭化珪素半導体素子の絶縁膜の形成方法は、炭化珪素の酸化処理中に図１(b)の様に、酸化処理温度を変化させる。通常１０００℃以上の高温での酸化処理７の後に、（再酸化）アニール処理を施す。つまり、一般に使われているSiCエピ膜は、3.5度から８度程度（１１−２０）方向へのOFF角をもった炭化珪素基板上１に成長されており、その表面３は物理的には図１(a)に示したように（０００１）面５と（１１−２０）面６から構成される。特に２原子層以上の高さを有するステップ２を含む炭化珪素基板１において、（０００１）面５からのOFF角が８度にも及ぶ基板では、図１(a)に示したように基板表面の１４％が（１１−２０）面６によって構成される。SiCエピ膜の酸化速度は、（０００１）面に比べて（１１−２０）面では３倍ほど早く厚い酸化絶縁膜が形成され、従来例の説明で述べた残留する不純物を消失させるための再酸化アニール処理における最適な酸化温度も異なっている。
【００２１】
本発明の炭化珪素半導体素子の絶縁膜の形成方法は、（０００１）面に対して酸素を含む雰囲気下での再酸化アニール処理８を行った後、（１１−２０）面に対して酸素を含む雰囲気下での再酸化アニール処理９を行う２段アニーリングを基本とする。（０００１）面は（１１−２０）面に比べ酸化されにくいため、（０００１）面に対する再酸化アニール処理は高温を必要とする。この（０００１）面に対する高温の設定温度での１回目の再酸化アニール処理８を行った後、この１回目の再酸化アニール処理８の設定温度よりも低い温度で（１１−２０）面を再酸化アニール処理９を行うことが有効であった。
【００２２】
上述の(11-20)面については、(0001)面と直交する面で有れば、例えば(1-100)面でも同様の効果が確認され、本発明は有効であった。つまり、本発明の上記２段アニール処理を施すことにより、高耐圧の準位密度の少ない炭化珪素上の酸化絶縁膜が形成可能となった。この後に、アニール処理を更に付加して、ｎ回のアニール処理を施してもｎが２以上で有れば本発明は実現できた。
【００２３】
上には、(0001)Si面のオフカット面の炭化珪素基板の場合を示したが、一般には上述の（０００１）面と（１１−２０）面、更には(0001)面と直交する例えば(1-100)面などの同等の面から構成されるオフカット面に対して本発明は有効であることを確認した。つまり、本発明の炭化珪素半導体素子およびその絶縁膜の形成方法は、表面に形成された酸化膜を含み、β-SiC(111)、6H,4H等のα-SiC(0001)、15R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα-SiC(1-100)及び／又はα-SiC(11-20)の内から選ばれる結晶面の１度以上のオフカット面を表面とする炭化珪素基板について有効であることを確認した。
【００２４】
つまり、上記オフカット面であり、図１(a)に示したように、２原子層以上の高さを有するステップ２を含む炭化珪素基板１と、上記炭化珪素基板表面３に形成された酸化膜４を含む炭化珪素半導体素子を、酸素を含む雰囲気下で複数の設定温度に保ってアニール処理を施す炭化珪素半導体素子の絶縁膜の形成方法であって、１回目のアニール処理に続いて、上記１回目のアニール処理設定温度よりも低い設定温度で２回目のアニール処理を施し、少なくとも２つ以上の異なる設定温度で保たれた酸素を含む雰囲気下でのn回(ｎ≧２)のアニール処理を含むと有効であることを確認した。
【００２５】
さらに、酸素を含む雰囲気下でのアニール処理を１０００℃以下で行うと、本発明の実現が容易であることを確認した。ここで酸素を含む雰囲気下でのアニール処理を１０００℃以上で行うと、上記アニール処理中に酸化膜/炭化珪素界面で酸化が進み、界面に残留する不純物が増加してしまい、本発明の良好な絶縁膜を形成するが出来ないことも確認した。
【００２６】
また、本発明の炭化珪素半導体素子およびその絶縁膜の形成方法は、１回目の酸素を含む雰囲気下でのアニール処理８の設定温度が９００℃以上であり、２回目以降のアニール処理９の設定温度が８５０℃以下であると好ましい。１回目の酸素を含む雰囲気下でのアニール処理８の設定温度が９００℃以下となると、（０００１）面に対して酸素を含む雰囲気下での再酸化アニールにより残留する不純物を消失させることが十分出来ず、本発明の良好な絶縁膜の形成が難しい。また、２回目以降のアニール処理９の設定温度が８５０℃以上であると、(0001)面と垂直な例えば（１１−２０）面を再酸化アニール処理を行い不純物を消失させる間に、一回目の再酸化アニールにより正常化された酸化膜/炭化珪素界面の酸化が進み界面が再びあれてしまい、本発明の良好な絶縁膜の形成が難しかった。
【００２７】
さらに、本発明の炭化珪素半導体素子およびその絶縁膜の形成方法は、１回目の酸素を含む雰囲気下でのアニール処理８がウェット酸素雰囲気であり、２回目以降のアニール処理９もウェット酸素雰囲気であると好ましい。酸素を含む雰囲気下でのアニール処理が水蒸気を含むウェット酸素雰囲気であると、上記ウェット酸素雰囲気でのアニール処理がｎ回の内の１回のみであっても、上記界面に残留する不純物の除去の効率が高くなり、有効であった。
【００２８】
上述の本発明の炭化珪素半導体素子の絶縁膜の形成方法を用いて、初めて、絶縁膜と炭化珪素の界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下である酸化絶縁膜が形成された。この低い界面準位密度（Ｎｉｔが１．５×１０¹²ｃｍ^-2以下）を有する絶縁膜は、例えば図２に示したような構造の、移動度の高い大電流を制御可能な炭化珪素半導体素子MOSFETを初めて実現した。
【００２９】
【実施例】
（実施例１）
実施例１として本発明の炭化珪素半導体素子の第一の実施例を図２を用いて説明する。本発明の炭化珪素半導体素子の実施例１の絶縁ゲート型半導体素子２１は、図２のごとく、5×10¹⁸cm^-3のドープ濃度のｎ型の基板２２上に5×10¹⁵cm^-3のドープ濃度のｎ型のエピタキシャル成長層（ｎ型層）２３を１０ミクロンの厚さで形成し、その一部にAl（ｐ型半導体を形成する不純物）イオン打ち込みすることによりｐ型の部分２４を5×10¹⁷cm^-3の濃度で２ミクロンの厚さで形成し、ｐ型の部分の表面近傍の一部にｎ型半導体を形成するN不純物をイオン打ち込みすることにより10¹⁹cm^-3のドープ濃度のｎ型の部分２５を0.3ミクロンの厚さで形成する。上記ｎ型層２３が表面に達している部分と上記ｎ型の部分２５とに挟まれたｐ型の部分の表面に、本発明の２原子層以上の高さを有するステップを含む炭化珪素基板表面に形成された酸化膜であり、上記酸化膜と炭化珪素の界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下である酸化絶縁膜２６を25nmの厚みで形成した。更にその表面にAlのゲート電極２７aを設けた。ドレイン電極２7cは基板裏面にNiを蒸着してアロイ化（熱処理１０００℃、５分）してオーミック電極として形成し、ソース電極２7bはｎ型の部分２５とｐ型の部分２４にオーミックコンタクトするようにNiにより形成された。この絶縁ゲート型半導体素子２１は、ゲート電極２7aへのバイアスによってｐ型の部分２４の表面に形成される反転層がチャンネル領域２８として作用して、ドレインからソースに向かって電流が流れ、ゲート電圧によってソース・ドレイン電流が変調されFET動作をした。
【００３０】
この場合の、本発明の炭化珪素半導体素子の実施例１として、ゲート長が２ミクロンでゲート幅が５００ミクロンの素子を形成した。ゲート電圧が10Vの時の、10V印可時のソース・ドレインの電流は20mA以上あった。一方、従来の絶縁膜つまり酸化膜と炭化珪素の界面準位密度が１０¹³ｃｍ^-2以上である炭化珪素半導体素子においては、上記本発明の第一の実施例の半導体素子の実施例１と同様の大きさの半導体素子において同様の条件で１ｍＡ以下の電流が流れるのみであることが確認された。
【００３１】
本発明者等は、本発明の半導体素子の酸化絶縁膜は、上記酸化膜と炭化珪素の界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下であることを実施例２に述べる方法により確認した。この低い界面準位密度Ｎｉｔ＝１．５×１０¹²ｃｍ^-2以上である場合には、上記ソース・ドレイン電流値が著しく減少し、１ｍＡ以下となってしまうことも確認した。つまり、上記酸化膜と炭化珪素の界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以上であると、半導体素子の性能が著しく悪化し、実用に耐えないモノになってしまうことも確認した。
【００３２】
この場合、炭化珪素半導体素子の表面は、SiC(0001)結晶面に対して８度オフカットした面であり、基板表面（絶縁膜/炭化珪素界面）に必ずステップを有する。ここで、上記絶縁膜/炭化珪素界面のステップがバンチングしており、２原子層以上の高さのステップを有する場合に、上記界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下であることが特に重要であることを確認した。本発明により、ソース・ドレイン電流の著しい増大が確認され、本発明の実用に耐える炭化珪素半導体素子が実現された。
【００３３】
また、２原子層以上の高さを有するステップを含む炭化珪素基板と、上記炭化珪素基板表面に形成された酸化膜を含み、酸化膜と炭化珪素の界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下である本発明の半導体素子において、上記実施例１の半導体素子のチャンネル部分２８にｎ型層を挿入したＡＣＣＵＦＥＴを形成した場合には、１００ｃｍ²／Ｖｓ以上のチャンネル移動度が確認された。従来の同様な炭化珪素半導体素子のチャンネル移動度は１０ｃｍ²／Ｖｓ以下であり、本発明により実用に耐える炭化珪素半導体素子が実現できることが確認された。本実施例１において形成されたＭＯＳＦＥＴは、そのｏｎ時のチャネル抵抗およびドリフト抵抗を見積もると、ほぼ同等の桁の値となっており、低損失のパワー素子が形成されていることが確認された。従来の絶縁膜/炭化珪素界面を用いて、界面準位密度が1.5×10¹²cm^-2以上と大きい場合は、チャンネル抵抗がドリフト抵抗に対して一桁以上大きな値となり、実用に耐えるものではなかった。
【００３４】
さらに、２原子層以上の高さを有するステップを含む炭化珪素基板と、上記炭化珪素基板表面に形成された酸化膜を含む半導体素子においては、酸化膜と炭化珪素の界面準位密度Ｎｉｔが１．５×１０¹²ｃｍ^-2以下であると、酸化絶縁膜の絶縁耐圧が10MVcm^-1以上となることも確認した。従来の２原子層以上の高さを有するステップを含む炭化珪素基板と上記炭化珪素基板表面に形成された界面準位密度の大きな酸化膜を含む炭化珪素半導体素子においては、絶縁耐圧が1MVcm^-1以下であり、本発明の半導体素子においてはじめて、実用に耐える十分な絶縁耐圧が達成された。
【００３５】
本発明の炭化珪素半導体素子は、炭化珪素が有する物性の、ワイドギャップ性・高絶縁耐圧・十分な移動度・高い熱伝導性を生かして、低損失の高温でも動作する省エネルギーに寄与する半導体素子を提供する。
【００３６】
実施例１においては、SiC(0001)の８度オフカット面を基板として用い、その表面に形成された炭化珪素半導体素子について述べたが、２原子層以上の高さを有するステップを含む炭化珪素基板が、他のβ-SiC(111)、6H,4H等のα-SiC(0001)、15R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα-SiC(1-100)及び／又はα-SiC(11-20)の内から選ばれる結晶面の１度以上のオフカット面を表面とする炭化珪素基板であっても本発明は有効であることを確認した。
【００３７】
（実施例２）
実施例2として本発明の炭化珪素半導体素子の絶縁膜の製造方法の実施例を図１(b)を用いて説明する。金属-酸化膜-半導体(MOS)試料を作製するために用いた単結晶ウエファは、市販のn型の4周期六方晶炭化珪素(4H-SiC)である。この単結晶ウエファは、直径2インチで(0001)面に対して8°のoff角を持っており、結晶表面には不純物濃度5×10¹⁵cm^-3のエピタキシャル膜が成長させてある。この単結晶を、5mm×5mm角に切断してMOS試料作製用の基板とした。試料作製前、基板の表面を有機洗浄した直後に1100℃の酸素中に水素を吹き込んで生成した高温水蒸気で酸化を行い(水素燃焼酸化)、その単結晶表面を犠牲酸化した。その酸化膜を3%の薄いフッ酸を用いて溶融させて洗浄表面を露出させた。この洗浄表面を有する炭化珪素4H-SiC基板のシリコン面に対して、1100℃で1時間の水素燃焼酸化を行い、25nmの厚さのゲ-ト酸化膜を形成した。
【００３８】
続いて、酸化温度を950℃まで低下させて3時間水素燃焼酸化雰囲気(酸素と水蒸気を含むウエット酸素雰囲気)での一回目アニール処理を行った。引き続いて温度を800℃まで低下させて、さらに3時間の水素燃焼酸化雰囲気(酸素と水蒸気を含むウエット酸素雰囲気)での2回目のアニール処理を行った。多段アニール処理終了後、試料を反応管から引き出し、試料温度を室温まで急速冷却してSiO₂/6H-SiC界面付近の化学反応を中断させた。ゲ-ト酸化膜を作製直後、アルミニウム(Al)を蒸着して直径0.5mmの電極を持つMOS構造を形成した。また、オ-ミック電極は、裏面表層に成長した酸化膜を除去してから、その露出した4H-SiC基板表面上にAlを蒸着して作製した。
【００３９】
4H-SiCMOS構造の容量-重量(C-V)特性は、低周波容量測定／高周波容量測定・同時測定装置(パッケ-ジ82;ケスレ-社製)を用いて、室温、暗状態で測定した。このC-V特性の取得においては、反転領域から蓄積領域へ電圧を掃引(順方向掃引)と蓄積領域から反転領域へと測定電圧を掃引する(逆方向掃引)を行った。順方向掃引においては、掃引開始前に紫外線を試料ゲ-ト電極表面に照射し、反転層を形成させた。反転層が形成された後、紫外線照射を止めてから室温、暗状態にて測定を行っている。一方、逆方向掃引を行うときは、紫外線照射は行っていない。
【００４０】
図３(a)に、ゲート酸化膜作製後に本発明の炭化珪素半導体素子の絶縁膜の形成方法のアニール処理の実施例である950℃3時間と800℃3時間の水蒸気アニール処理を続けて行ったときのC-V特性、図３(b)に、従来の炭化珪素半導体素子の絶縁膜の形成方法のアニール処理である950℃3時間の水蒸気アニ-ル処理しか行わなかったときのC-V特性を示す。
【００４１】
図３(a)では、高周波C-V曲線が−13Vから＋10Vまで掃引されている。掃引電圧が減少して行くと、容量が一旦減少(少数キャリアの再分布)する。その後電圧0V近辺から容量の増大がはじまるが、すぐに容量の増大が抑止され、折れ曲がっている(キャパシタンスレッジ)のが解る。また、準静状態C-V曲線では、キャパシタンスレッジが現れる0Vの電圧領域で、楔形の大きな容量の減少を引き起こしているのが解る。これらの事実は、SiO₂/4H-SiC界面の界面準位が少ないことを示している。
【００４２】
これに対して、図３(b)の950℃3時間の水蒸気アニール処理しか行わなかった試料では、高周波C-V特性における、少数キャリアの再分布やキャパシタンスレッジが明確ではない。また、準静状態C-V曲線の容量減少も明確ではなく、界面準位量が多いことを示している。
【００４３】
図３(a)と(b)の比較において明らかなように、本発明の炭化珪素半導体素子の絶縁膜の形成方法である多段水蒸気アニール処理には界面準位減少の効果のあることが解る。この結果は、（０００１）面に対して再酸化効果がある９５０℃で3時間の酸化雰囲気アニール処理につづいて、（１１−２０）面に対して再酸化効果がある８００℃で3時間の酸化雰囲気アニール処理を行った結果である。その結果、低周波CV特性の形状が楔形に変化しており、従来の炭化珪素半導体素子の絶縁膜の形成方法である単一温度のアニール処理よりも界面準位量の低下が計られいることが判る。
【００４４】
本発明の炭化珪素半導体素子の絶縁膜の形成方法の実施例の界面準位密度Nitは、Nit=1.09×10¹²cm^-2であり、従来の実施例の界面準位密度Nit=5.15×10¹²cm^-2に比べて非常に小さくなっており、本発明の絶縁膜の形成方法の有効性が確認された。
【００４５】
実施例２においては、4H-SiC(0001)の８度オフカット面を基板として用い、その表面に形成する炭化珪素半導体素子の絶縁膜の製造方法について述べたが、２原子層以上の高さを有するステップを含む炭化珪素基板が、他のβ-SiC(111)、6H,4H等のα-SiC(0001)、15R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα-SiC(1-100)及び／又はα-SiC(11-20)の内から選ばれる結晶面の１度以上のオフカット面を表面とする炭化珪素基板であっても本発明は有効であることを確認した。
【００４６】
本実施例２においては、アニール処理が２回の場合を述べたが、更に多くのｎ回の設定温度の変更を含むｎ回のアニール処理を施した場合であっても、本発明の２原子層以上の高さを有するステップを含む炭化珪素基板と、上記炭化珪素基板表面に形成された酸化膜を含む炭化珪素半導体素子を、酸素を含む雰囲気下で複数の設定温度に保ってアニール処理を施す炭化珪素半導体素子の絶縁膜の形成方法であって、１回目のアニール処理に続いて、上記１回目のアニール処理設定温度よりも低い設定温度で２回目のアニール処理を施し、少なくとも２つ以上の異なる設定温度で保たれた酸素を含む雰囲気下でのn回(n≧２)のアニール処理を含めば、有効であることを確認した。
【００４７】
本実施例２においては、１回目のアニール処理の設定温度が９５０℃、２回目のアニール処理の設定温度が８００℃の場合を述べたが、本発明の炭化珪素半導体素子の絶縁膜の形成方法であって、１回目の酸素を含む雰囲気下でのアニール処理が９００℃以上であり、設定温度が８５０℃以下であるｎ回目のアニール処理を少なくとも含めば、有効であることも確認した。
【００４８】
本実施例２においては、アニール処理をウェット酸素雰囲気の一種である水素燃焼酸化雰囲気で行った場合を述べたが、本発明の炭化珪素半導体素子の絶縁膜の形成方法であって、少なくともｎ回目の酸素を含む雰囲気下でのアニール処理が水蒸気と酸素を少なくとも含むウェット酸素雰囲気で行われると有効であることを確認した。
【００４９】
【発明の効果】
以上説明した通り、本発明の炭化珪素半導体素子によれば、高パワーを制御する低損失・高耐圧の制御素子を実現でき、例えば、エアコンなどを制御する高性能インバータ等に用いられる、実用に耐える省エネパワー素子を提供する。
【００５０】
また、本発明の炭化珪素半導体素子の絶縁膜の形成方法によれば、低損失パワー素子のゲート絶縁膜として応用可能な、高い絶縁耐圧・低い固定電荷密度・低い界面準位密度を有する、炭化珪素半導体素子の絶縁膜が得られ、耐圧が高く電流容量も大きい大電力用に適した高速な低損失半導体素子を形成可能とするものである。
【図面の簡単な説明】
【図１】(a)本発明の炭化珪素半導体素子の絶縁膜/炭化珪素界面の拡大図である。
(b)本発明の炭化珪素半導体素子の絶縁膜の形成方法を示す図である。
【図２】絶縁ゲート型半導体素子の構造を示す図である。
【図３】(a)本発明の炭化珪素半導体素子及びその絶縁膜の形成方法による酸化絶縁膜/炭化珪素界面のC-V特性を示す図である。
(b)従来例の絶縁膜の形成方法による酸化絶縁膜/炭化珪素界面のC-V特性を示す図である。
【符号の説明】
１基板
２ステップ
３絶縁膜/炭化珪素基板界面
４酸化絶縁膜
５ (0001)テラス面
６ (11-20)面
７酸化設定温度
８１回目のアニール設定温度
９２回目のアニール設定温度
２１絶縁ゲート型半導体素子
２２ n型基板
２３ n型エピタキシャル成長層（ｎ型層）
２４ p型の部分（ｐ型層）
２５ n+型層
２６酸化絶縁膜
２７a ゲート電極
２７b ソース電極のオーミック接合の部分
２７c ドレイン電極
２７d ソース電極のショットキー接合の部分
２８チャンネル領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device composed of silicon carbide, and more particularly to a gate insulating film of a power MOS semiconductor device and a method for forming the same, and in particular, enables a high-speed, high breakdown voltage, and low-loss power semiconductor device to be realized. Is.
[0002]
[Prior art]
As shown in FIG. 2, a conventional insulated gate semiconductor element 21 composed of conventional silicon carbide described as Conventional Example 1 includes an n-type epitaxial growth layer (n-type layer) 23 formed on an n-type substrate 22, and one of them. A p-type portion 24 is formed by diffusing or ion-implanting impurities forming a p-type semiconductor such as Al in the portion, and an n-type semiconductor such as N is formed in a part near the surface of the p-type portion. The n-type portion 25 is formed by diffusing or ion-implanting impurities forming the. An oxide insulating film 26 is formed on the surface of the p-type portion 24 sandwiched between the portion where the n-type layer 23 reaches the surface and the n-type portion 25, and a gate electrode 27a is further provided on the surface. The drain electrode 27c is formed on the back surface of the substrate, and the source electrode 27b is formed in contact with the n-type portion 25 and the p-type portion 24. In this insulated gate type semiconductor element, an inversion layer formed on the surface of the p-type portion 24 by the bias to the gate electrode 2 7a functions as a channel.
[0003]
The content of this prior art is disclosed in, for example, Silicon Carbide; A Review of Fundamental Questions and Applications to Current Device Technology, edited by WJ Choyke, H. Matsunami, and G. Pensl, Akademie Verlag 1997, Vol. II pp.369-388. Has been. The silicon carbide semiconductor element provides a semiconductor element that contributes to energy saving that operates even at a low loss and high temperature by taking advantage of the physical properties of silicon carbide, such as wide gap, high withstand voltage, sufficient mobility, and high thermal conductivity. It is expected that.
[0004]
However, conventional silicon carbide semiconductor elements, particularly semiconductor elements including an oxide insulating film / silicon carbide interface such as a MOSFET, are not suitable for practical use due to insufficient characteristics of the oxide insulating film / silicon carbide interface. When forming the insulated gate semiconductor element, the oxide insulating film 26 formed on the surface of the channel portion is formed by oxidizing a silicon carbide substrate on which an element pattern is formed by ion implantation or the like. Furthermore, after the oxide insulating film is formed, re-oxidation annealing is performed in an atmosphere containing oxygen at a temperature lower than the temperature at which the oxide insulating film is formed, and the oxide insulating film and the oxide insulating film / silicon carbide interface are formed. High performance has been reported.
[0005]
Such conventional oxide film formation methods are also described in, for example, the document P-type SiC MOS reliability with improved oxidation procedures and aluminum or boron p-type entrapments, LALipkin and JWPalmour, proceedings of high temperature electronics XIV-15-XIV-20. As shown, let the formed oxide film be exposed to an oxidizing atmosphere at a temperature lower than the oxidation temperature, and oxidize the remaining impurities in the vicinity of the interface again to reduce the interface state density that causes the deterioration of electrical characteristics. This is an attempt (reoxidation). Until now, the temperature used for reoxidation has been limited to one kind.
[0006]
Although these conventional methods for forming an insulating film of a silicon carbide semiconductor element certainly reduce the interface state density at the oxide insulating film / silicon carbide interface, the interface state density sufficient for a semiconductor element is not reached. Further, it is necessary to reduce by one digit or more, which is insufficient as a method for forming an insulating film. Furthermore, with regard to pressure resistance, 1 MVcm ^-1 In many cases, it was insufficient. 10MVcm for high voltage element ^-1 A degree of pressure resistance is necessary. Further, the interface state density Nit at the oxide insulating film / silicon carbide interface in the conventional example is 1 × 10. ¹³ cm ^-2 The silicon carbide semiconductor element MOSFET of FIG. 2 formed using this insulating film has a thickness of 10 cm. ² This is insufficient for a semiconductor device which exhibits a low channel mobility of about / Vs and can withstand practical use.
[0007]
[Problems to be solved by the invention]
In order to realize a silicon carbide semiconductor device that can withstand practical use, at least 2 × 10 ¹² cm ^-2 The following interface state density Nit, 100 cm ² A channel mobility of at least / Vs is required. If this channel mobility is achieved, the channel resistance of the MOSFET is reduced, which is comparable to the drift mobility in the case of a power device with a breakdown voltage of several hundred volts, and becomes a semiconductor device that can withstand practical use as a power device.
[0008]
The object of the present invention, which overcomes the problems of the prior art, is to realize a low-loss / high-voltage semiconductor device that takes advantage of the properties of a wide gap semiconductor such as silicon carbide.
[0009]
[Means for Solving the Problems]
In the above conventional example, the inventors have examined that the dielectric breakdown voltage of the oxide insulating film is small and insufficient, and that the level density is large and insufficient. It became. In other words, the surface of the silicon carbide semiconductor substrate currently in use uses an α-SiC (0001) offcut surface, and the surface includes an α-SiC (0001) terrace and a (1-210) step. The inventors have found that this is the cause of the low level density and the high level density, and based on this finding, invented the method for forming an insulating film of the present invention.
[0010]
α-SiC (0001) plane (Si plane) and (1-210) plane have different oxidation rates.For example, Silicon Carbide; A Review of Fundamental Questions and Applications to Current Device Technology, edited by WJ Choyke, H. Matsunami , and G. Pensl, Akademie Verlag 1997, Vol.II pp.369-388, which is known, but the evaluation of the characteristics of the oxide insulating film / silicon carbide interface was insufficient. The method for forming the oxide insulating film has not been optimized based on the evaluation, and based on the evaluation results revealed for the first time by the present inventors, the optimum method for forming the insulating film has been established. Furthermore, a silicon carbide semiconductor element that has never been used has been invented.
[0011]
A silicon carbide semiconductor element of the present invention includes a silicon carbide substrate including a step having a height of two atomic layers (monolayer) or more, and an oxide film formed on the surface of the silicon carbide substrate. Interface state density Nit is 1.5 × 10 ¹² cm ^-2 It is characterized by the following.
[0012]
In the silicon carbide semiconductor device of the above invention, a silicon carbide substrate including a step having a height of 2 atomic layers or more is formed of α-SiC (0001) such as β-SiC (111), 6H, 4H, or 15R-SiC Si. 1 degree of a crystal plane selected from α-SiC (1-100) and / or α-SiC (11-20) such as plane, β-SiC (100), β-SiC (110), 6H, 4H, etc. A silicon carbide substrate having the above-described off-cut surface as a surface is preferable.
[0013]
An insulating film forming method for a silicon carbide semiconductor device according to the present invention includes a silicon carbide substrate including a step having a height of two atomic layers or more, and a silicon carbide semiconductor device including an oxide film formed on the surface of the silicon carbide substrate. A method for forming an insulating film of a silicon carbide semiconductor element in which an annealing process is performed while maintaining an oxygen-containing atmosphere at a plurality of set temperatures, the first annealing process being followed by the first annealing process setting temperature. The second annealing process is performed at a lower set temperature, and the annealing process is performed n times (n ≧ 2) in an atmosphere containing oxygen maintained at at least two different set temperatures.
[0014]
In the method for forming an insulating film of a silicon carbide semiconductor element of the above invention, the first annealing process in an atmosphere containing oxygen is 900 ° C. or higher, and at least the n-th annealing process with a set temperature of 850 ° C. or lower is included. And preferred.
[0015]
Furthermore, in the method for forming an insulating film of a silicon carbide semiconductor element of the above invention, it is preferable that the annealing treatment in an atmosphere containing oxygen at least n times is a wet oxygen atmosphere.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The silicon carbide semiconductor element of the present invention includes a silicon carbide substrate 1 including a step 2 having a height of two atomic layers or more as shown in the enlarged view of the insulating film / silicon carbide interface in FIG. Including an oxide film 4 formed on the surface of the silicon carbide substrate, the interface state density Nit at the interface 3 between the oxide insulating film 4 and the silicon carbide 1 is 1.5 × 10 ¹² cm ^-2 It is characterized by including the insulating film 4 characterized by the following.
[0017]
In a semiconductor device using an off-cut silicon carbide substrate 1 including step 2 having a height of two monolayers or more, particularly in a vertical insulated gate semiconductor device (MOSFET) for high power, the insulating film / silicon carbide is low. The interface state density is first realized by the present invention, and the interface state density Nit is 1.5 × 10. ¹² cm ^-2 It was confirmed for the first time that the channel resistance was the same level as the drift resistance in the following range.
[0018]
It has been confirmed that a MOS semiconductor device capable of controlling a large current can be realized by utilizing this low interface state density insulating film / silicon carbide interface. Interface state density Nit is 1.5 × 10 ¹² cm ^-2 As described above, it was confirmed that when a MOSFET semiconductor element was formed, the channel resistance was larger by an order of magnitude or more than the drift resistance, the loss increased, and it was not suitable as a large current control power semiconductor element.
[0019]
In the silicon carbide semiconductor device of the present invention, a silicon carbide substrate including a step having a height of 2 atomic layers or more is formed of α-SiC (0001), 15R-SiC such as β-SiC (111), 6H, 4H, etc. One of crystal planes selected from Si-plane, β-SiC (100), β-SiC (110), α-SiC (1-100) such as 6H, 4H and / or α-SiC (11-20) It was confirmed that the silicon carbide substrate having an off-cut surface of at least the upper surface is preferable. Here, since it was difficult to grow an epitaxial film having good crystallinity on a substrate having an off-cut angle of 1 degree or less, it was not preferable. In addition, it was confirmed that the present invention is easily realized for a substrate having an off-cut angle of 10 degrees or less. Here, for an off angle of 10 degrees or more of the silicon carbide substrate, it is difficult to obtain a good epitaxial film, and it is sometimes difficult to form a good insulating film of the present invention.
[0020]
In the method for forming an insulating film of a silicon carbide semiconductor element of the present invention, the oxidation treatment temperature is changed during the oxidation treatment of silicon carbide as shown in FIG. Usually, after the oxidation treatment 7 at a high temperature of 1000 ° C. or more, (reoxidation) annealing treatment is performed. That is, a generally used SiC epi film is grown on a silicon carbide substrate 1 having an OFF angle in the direction of about 3.5 to 8 degrees (11-20), and its surface 3 is physically As shown in FIG. 1A, it is composed of a (0001) plane 5 and a (11-20) plane 6. In particular, in the silicon carbide substrate 1 including step 2 having a height of 2 atomic layers or more, the substrate surface has an OFF angle as long as 8 degrees from the (0001) plane 5 as shown in FIG. 14% is constituted by the (11-20) plane 6. The oxidation rate of the SiC epitaxial film is about 3 times faster on the (11-20) plane than on the (0001) plane, and a thick oxide insulating film is formed to eliminate the residual impurities described in the description of the conventional example. The optimum oxidation temperature in the oxidation annealing process is also different.
[0021]
In the method for forming an insulating film of a silicon carbide semiconductor element according to the present invention, after the re-oxidation annealing process 8 is performed on the (0001) plane in an atmosphere containing oxygen, oxygen is applied to the (11-20) plane. Basically, a two-stage annealing is performed in which a re-oxidation annealing treatment 9 is performed in an atmosphere containing the same. Since the (0001) plane is less oxidized than the (11-20) plane, the re-oxidation annealing process for the (0001) plane requires a high temperature. After performing the first re-oxidation annealing process 8 at a high set temperature for the (0001) plane, the (11-20) plane is re-applied at a temperature lower than the set temperature of the first re-oxidation anneal process 8. It was effective to perform the oxidation annealing treatment 9.
[0022]
As long as the above (11-20) plane is a plane orthogonal to the (0001) plane, for example, the same effect was confirmed even in the (1-100) plane, and the present invention was effective. That is, by performing the two-step annealing process of the present invention, an oxide insulating film on silicon carbide having a high breakdown voltage and a low level density can be formed. After this, an annealing treatment was further added, and even if n annealing treatments were performed, the present invention could be realized if n was 2 or more.
[0023]
In the above, the case of a silicon carbide substrate having an off-cut surface of the (0001) Si surface is shown. In general, for example, the (0001) surface and the (11-20) surface are orthogonal to the (0001) surface. It was confirmed that the present invention is effective for an off-cut surface composed of an equivalent surface such as (1-100) surface. That is, the silicon carbide semiconductor element of the present invention and the method for forming the insulating film thereof include an oxide film formed on the surface, β-SiC (111), 6H, 4H, etc. α-SiC (0001), 15R-SiC Si plane, β-SiC (100), β-SiC (110), 6H, 4H, etc., α-SiC (1-100) and / or α-SiC (11-20) It was confirmed that the silicon carbide substrate having an off-cut surface of 1 degree or more as a surface is effective.
[0024]
That is, as shown in FIG. 1 (a), the silicon carbide substrate 1 including step 2 having a height of two atomic layers or more, and the oxidation formed on the silicon carbide substrate surface 3 as shown in FIG. A method for forming an insulating film of a silicon carbide semiconductor element, in which a silicon carbide semiconductor element including a film 4 is annealed while maintaining a plurality of set temperatures in an atmosphere containing oxygen. Following the first annealing process, The second annealing process is performed at a setting temperature lower than the first annealing process setting temperature, and the annealing process is performed n times (n ≧ 2) in an atmosphere containing oxygen maintained at at least two different setting temperatures. It was confirmed that the treatment was effective.
[0025]
Furthermore, it has been confirmed that the present invention can be easily realized when the annealing treatment in an atmosphere containing oxygen is performed at 1000 ° C. or lower. Here, if the annealing treatment in an atmosphere containing oxygen is performed at 1000 ° C. or higher, the oxidation proceeds at the oxide film / silicon carbide interface during the annealing treatment, and impurities remaining at the interface increase, which is favorable for the present invention. It was also confirmed that a simple insulating film could not be formed.
[0026]
In the silicon carbide semiconductor device and the method for forming the insulating film thereof according to the present invention, the set temperature of the annealing process 8 in the atmosphere containing oxygen for the first time is 900 ° C. or higher, and the setting of the annealing process 9 for the second time and thereafter is performed. The temperature is preferably 850 ° C. or lower. When the set temperature of the annealing process 8 in the first oxygen-containing atmosphere is 900 ° C. or lower, it is sufficient to eliminate the remaining impurities by re-oxidation annealing in the oxygen-containing atmosphere with respect to the (0001) plane. It is not possible to form a good insulating film of the present invention. In addition, if the set temperature of the annealing treatment 9 after the second time is 850 ° C. or more, the first time, for example, the (11-20) plane perpendicular to the (0001) plane is subjected to the reoxidation annealing treatment to eliminate impurities. Oxidation of the oxide film / silicon carbide interface normalized by this re-oxidation annealing progressed and the interface was re-established, making it difficult to form a good insulating film of the present invention.
[0027]
Furthermore, in the method for forming the silicon carbide semiconductor element and the insulating film thereof according to the present invention, the first annealing treatment 8 in an atmosphere containing oxygen is a wet oxygen atmosphere, and the second and subsequent annealing treatments 9 are also in a wet oxygen atmosphere. Preferably there is. If the annealing treatment in an atmosphere containing oxygen is a wet oxygen atmosphere containing water vapor, removal of impurities remaining at the interface even if the annealing treatment in the wet oxygen atmosphere is performed only once in n times. The efficiency was high and effective.
[0028]
For the first time, the interface state density Nit between the insulating film and silicon carbide is 1.5 × 10 5 by using the method for forming an insulating film of the silicon carbide semiconductor element of the present invention described above. ¹² cm ^-2 The following oxide insulating film was formed. This low interface state density (Nit is 1.5 × 10 ¹² cm ^-2 For example, a silicon carbide semiconductor element MOSFET having a structure as shown in FIG. 2 and capable of controlling a high current with high mobility can be realized for the first time.
[0029]
【Example】
(Example 1)
As a first embodiment, a first embodiment of the silicon carbide semiconductor element of the present invention will be described with reference to FIG. As shown in FIG. 2, the insulated gate semiconductor device 21 of the first embodiment of the silicon carbide semiconductor device of the present invention is 5 × 10 5. ¹⁸ cm ^-3 5 × 10 5 on n-type substrate 22 with a doping concentration of ¹⁵ cm ^-3 An n-type epitaxial growth layer (n-type layer) 23 having a doping concentration of 10 μm is formed with a thickness of 10 μm, and Al (impurities forming a p-type semiconductor) ions are implanted into a part thereof to form a p-type portion 24. 5 × 10 ¹⁷ cm ^-3 By implanting an N impurity that forms an n-type semiconductor into a portion near the surface of the p-type portion by ion implantation. ¹⁹ cm ^-3 An n-type portion 25 having a doping concentration of 0.3 μm is formed with a thickness of 0.3 μm. A silicon carbide substrate including a step having a height of two or more atomic layers of the present invention on the surface of a p-type portion sandwiched between the portion where n-type layer 23 reaches the surface and n-type portion 25 An oxide film formed on the surface, and an interface state density Nit between the oxide film and silicon carbide is 1.5 × 10 ¹² cm ^-2 The following oxide insulating film 26 was formed with a thickness of 25 nm. Further, an Al gate electrode 27a was provided on the surface. The drain electrode 27c is formed as an ohmic electrode by vapor deposition of Ni on the back surface of the substrate (heat treatment 1000 [deg.] C., 5 minutes), and the source electrode 27b is in ohmic contact with the n-type portion 25 and the p-type portion 24. Formed by Ni. In this insulated gate semiconductor element 21, the inversion layer formed on the surface of the p-type portion 24 by the bias to the gate electrode 2 7a acts as the channel region 28, and current flows from the drain to the source, and the gate voltage As a result, the source / drain current is modulated and the FET operates.
[0030]
In this case, as Example 1 of the silicon carbide semiconductor element of the present invention, an element having a gate length of 2 microns and a gate width of 500 microns was formed. When the gate voltage was 10V, the source / drain current when 10V was applied was more than 20mA. On the other hand, the interface state density between a conventional insulating film, that is, an oxide film and silicon carbide is 10 ¹³ cm ^-2 In the silicon carbide semiconductor element as described above, only a current of 1 mA or less flows under the same conditions in the semiconductor element having the same size as that of the semiconductor element of the first embodiment of the present invention. confirmed.
[0031]
The inventors have determined that the oxide insulating film of the semiconductor element of the present invention has an interface state density Nit of 1.5 × 10 5 between the oxide film and silicon carbide. ¹² cm ^-2 The following was confirmed by the method described in Example 2. This low interface state density Nit = 1.5 × 10 ¹² cm ^-2 In the above case, it was also confirmed that the source / drain current value was remarkably reduced to 1 mA or less. That is, the interface state density Nit between the oxide film and silicon carbide is 1.5 × 10. ¹² cm ^-2 It was also confirmed that the performance of the semiconductor element was significantly deteriorated as described above, and the product could not withstand practical use.
[0032]
In this case, the surface of the silicon carbide semiconductor element is a surface which is off-cut by 8 degrees with respect to the SiC (0001) crystal plane, and always has a step on the substrate surface (insulating film / silicon carbide interface). Here, in the case where the step at the insulating film / silicon carbide interface is bunched and has a step having a height of two atomic layers or more, the interface state density Nit is 1.5 × 10 5. ¹² cm ^-2 It was confirmed that the following was particularly important. According to the present invention, a significant increase in the source / drain current was confirmed, and a silicon carbide semiconductor device capable of withstanding the practical use of the present invention was realized.
[0033]
The silicon carbide substrate includes a step having a height of two atomic layers or more and an oxide film formed on the surface of the silicon carbide substrate, and the interface state density Nit between the oxide film and silicon carbide is 1.5 × 10 5. ¹² cm ^-2 In the semiconductor device of the present invention as described below, when an ACCUFET having an n-type layer inserted is formed in the channel portion 28 of the semiconductor device of the first embodiment, 100 cm ² A channel mobility of more than / Vs was confirmed. The channel mobility of the conventional silicon carbide semiconductor device is 10 cm. ² It was confirmed that a silicon carbide semiconductor device that is not more than / Vs and can withstand practical use can be realized by the present invention. When the channel resistance and drift resistance when the MOSFET was turned on were estimated, the MOSFET formed in Example 1 had almost the same order of magnitude, and it was confirmed that a low-loss power element was formed. . Using a conventional insulating film / silicon carbide interface, the interface state density is 1.5 × 10 ¹² cm ^-2 When the value is larger than the above, the channel resistance is one digit or more larger than the drift resistance, which is not practical.
[0034]
Further, in a semiconductor element including a silicon carbide substrate including a step having a height of two atomic layers or more and an oxide film formed on the surface of the silicon carbide substrate, the interface state density Nit between the oxide film and silicon carbide is 1 .5x10 ¹² cm ^-2 The dielectric breakdown voltage of the oxide insulating film is 10 MVcm if ^-1 It was also confirmed that this was the case. In a conventional silicon carbide semiconductor device including a silicon carbide substrate including a step having a height of two atomic layers or more and an oxide film having a large interface state density formed on the surface of the silicon carbide substrate, the withstand voltage is 1 MVcm. ^-1 For the first time in the semiconductor element of the present invention, a sufficient withstand voltage that can withstand practical use was achieved.
[0035]
The silicon carbide semiconductor element of the present invention is a semiconductor element that contributes to energy saving that operates even at high temperatures with low loss by utilizing the physical properties of silicon carbide, such as wide gap, high dielectric strength, sufficient mobility, and high thermal conductivity. I will provide a.
[0036]
In the first embodiment, the silicon carbide semiconductor element formed on the surface of the SiC (0001) 8 ° off-cut surface is described as the substrate. However, the silicon carbide includes a step having a height of two atomic layers or more. The substrate is α-SiC (0001) such as other β-SiC (111), 6H, 4H, Si surface of 15R-SiC, β-SiC (100), β-SiC (110), 6H, 4H, etc. The present invention is effective even for a silicon carbide substrate having an off-cut surface of at least one degree of crystal plane selected from α-SiC (1-100) and / or α-SiC (11-20). I confirmed that there was.
[0037]
(Example 2)
As Example 2, an example of a method for manufacturing an insulating film of a silicon carbide semiconductor element of the present invention will be described with reference to FIG. The single crystal wafer used to fabricate the metal-oxide-semiconductor (MOS) sample is a commercially available n-type four-period hexagonal silicon carbide (4H-SiC). This single crystal wafer has an off angle of 8 ° with respect to the (0001) plane with a diameter of 2 inches, and an impurity concentration of 5 × 10 ¹⁵ cm ^-3 The epitaxial film is grown. This single crystal was cut into 5 mm × 5 mm square to form a substrate for MOS sample preparation. Before the sample preparation, immediately after organic cleaning of the surface of the substrate, oxidation was performed with high-temperature steam generated by blowing hydrogen into oxygen at 1100 ° C. (hydrogen combustion oxidation), and the single crystal surface was sacrificial oxidized. The oxide film was melted using 3% thin hydrofluoric acid to expose the cleaning surface. The silicon surface of the silicon carbide 4H—SiC substrate having the cleaned surface was subjected to hydrogen combustion oxidation at 1100 ° C. for 1 hour to form a gate oxide film having a thickness of 25 nm.
[0038]
Subsequently, the first annealing treatment was performed in a hydrogen combustion oxidizing atmosphere (wet oxygen atmosphere containing oxygen and water vapor) for 3 hours while lowering the oxidation temperature to 950 ° C. Subsequently, the temperature was lowered to 800 ° C., and a second annealing treatment was performed in a hydrogen combustion oxidation atmosphere (wet oxygen atmosphere containing oxygen and water vapor) for 3 hours. After the multi-stage annealing treatment, the sample is pulled out from the reaction tube, and the sample temperature is rapidly cooled to room temperature to obtain SiO. ₂ The chemical reaction near the / 6H-SiC interface was interrupted. Immediately after forming the gate oxide film, aluminum (Al) was deposited to form a MOS structure having an electrode with a diameter of 0.5 mm. The ohmic electrode was prepared by removing the oxide film grown on the back surface layer and then depositing Al on the exposed 4H—SiC substrate surface.
[0039]
The capacitance-weight (CV) characteristics of the 4H-SiCMOS structure were measured in a dark state at room temperature using a low frequency capacitance measurement / high frequency capacitance measurement / simultaneous measurement device (Package 82; manufactured by Kessley Co., Ltd.). In obtaining this CV characteristic, a voltage was swept from the inversion region to the accumulation region (forward sweep), and a measurement voltage was swept from the accumulation region to the inversion region (reverse direction sweep). In the forward sweep, the surface of the sample gate electrode was irradiated with ultraviolet rays before the sweep was started to form an inversion layer. After the inversion layer is formed, measurement is performed in a dark state at room temperature after the ultraviolet irradiation is stopped. On the other hand, when performing reverse sweep, ultraviolet irradiation is not performed.
[0040]
In FIG. 3 (a), after the gate oxide film is formed, the water vapor annealing process at 950 ° C. for 3 hours and 800 ° C. for 3 hours, which is an example of the annealing process of the method for forming the insulating film of the silicon carbide semiconductor device of the present invention, Fig. 3 (b) shows the CV characteristics when only the steam annealing process at 950 ° C for 3 hours, which is the annealing process of the conventional method for forming an insulating film of a silicon carbide semiconductor element, is performed. .
[0041]
In FIG. 3A, the high-frequency CV curve is swept from -13V to + 10V. As the sweep voltage decreases, the capacity once decreases (minority carrier redistribution). After that, the increase in capacitance starts from around the voltage 0V, but immediately, the increase in capacitance is suppressed, and it can be seen that it is bent (capacitance ledge). In the quasi-static CV curve, it can be seen that a large wedge-shaped capacitance decrease occurs in the voltage range of 0V where capacitance ledge appears. These facts indicate that SiO ₂ It shows that there are few interface states at the / 4H-SiC interface.
[0042]
On the other hand, in the sample in which only the steam annealing process at 950 ° C. for 3 hours in FIG. 3B was performed, the minority carrier redistribution and capacitance ledge in the high frequency CV characteristics are not clear. In addition, the capacity decrease of the quasi-static CV curve is not clear, indicating that the amount of interface states is large.
[0043]
As apparent from the comparison between FIGS. 3A and 3B, it is understood that the multi-stage water vapor annealing process, which is the method for forming the insulating film of the silicon carbide semiconductor element of the present invention, has an effect of reducing the interface state. This result shows that, following the annealing treatment at 950 ° C. for 3 hours having a reoxidation effect on the (0001) plane, the re-oxidation effect on the (11-20) plane is performed at 800 ° C. for 3 hours. It is the result of performing an oxidizing atmosphere annealing treatment. As a result, the shape of the low-frequency CV characteristics has changed to a wedge shape, and the amount of interface states has been reduced compared to the single-temperature annealing process, which is a conventional method for forming an insulating film of a silicon carbide semiconductor element. I understand.
[0044]
The interface state density Nit of the embodiment of the method for forming the insulating film of the silicon carbide semiconductor element of the present invention is Nit = 1.09 × 10 ¹² cm ^-2 The interface state density Nit = 5.15 × 10 in the conventional example. ¹² cm ^-2 The effectiveness of the method for forming an insulating film according to the present invention was confirmed.
[0045]
In the second embodiment, the method of manufacturing the insulating film of the silicon carbide semiconductor element formed on the surface using the 8H off-cut surface of 4H—SiC (0001) as the substrate has been described. A silicon carbide substrate including a step having a ratio of other β-SiC (111), 6H, 4H, etc. α-SiC (0001), 15R-SiC Si face, β-SiC (100), β-SiC (110 ), 6H, 4H, etc., a silicon carbide substrate having an off-cut surface of one or more crystal faces selected from α-SiC (1-100) and / or α-SiC (11-20). However, it was confirmed that the present invention is effective.
[0046]
In the second embodiment, the case where the annealing process is performed twice has been described. However, even when the annealing process including n times of changing the set temperature is performed more times, the two atoms of the present invention are used. An annealing treatment is performed by maintaining a silicon carbide semiconductor element including a silicon carbide substrate including a step having a height higher than a layer and an oxide film formed on the surface of the silicon carbide substrate at a plurality of set temperatures in an oxygen-containing atmosphere. A method for forming an insulating film of a silicon carbide semiconductor element to be performed, wherein a second annealing process is performed at a set temperature lower than the first annealing process setting temperature after the first annealing process, and at least two or more It was confirmed that it was effective if n times (n ≧ 2) of annealing treatments in an atmosphere containing oxygen maintained at different set temperatures were included.
[0047]
In the second embodiment, the case where the setting temperature of the first annealing treatment is 950 ° C. and the setting temperature of the second annealing treatment is 800 ° C. has been described, but the method for forming the insulating film of the silicon carbide semiconductor element of the present invention It was also confirmed that the first annealing treatment in an atmosphere containing oxygen was 900 ° C. or higher, and that at least the n-th annealing treatment with a set temperature of 850 ° C. or lower was included, it was effective.
[0048]
In the second embodiment, the case where the annealing process is performed in a hydrogen combustion oxidation atmosphere which is a kind of wet oxygen atmosphere is described. However, the method for forming an insulating film of a silicon carbide semiconductor element according to the present invention is at least nth. It was confirmed that the annealing treatment in an atmosphere containing oxygen was effective when performed in a wet oxygen atmosphere containing at least water vapor and oxygen.
[0049]
【The invention's effect】
As described above, according to the silicon carbide semiconductor element of the present invention, a low-loss / high-voltage control element that controls high power can be realized. For example, it can be used in a high-performance inverter that controls an air conditioner or the like. Provide energy-saving power elements that can withstand.
[0050]
In addition, according to the method for forming an insulating film of a silicon carbide semiconductor element of the present invention, the carbonization having a high withstand voltage, a low fixed charge density, and a low interface state density, which can be applied as a gate insulating film of a low-loss power element. An insulating film for a silicon semiconductor element can be obtained, and a high-speed, low-loss semiconductor element suitable for high power use having a high breakdown voltage and a large current capacity can be formed.
[Brief description of the drawings]
FIG. 1A is an enlarged view of an insulating film / silicon carbide interface of a silicon carbide semiconductor device of the present invention.
(b) It is a figure which shows the formation method of the insulating film of the silicon carbide semiconductor element of this invention.
FIG. 2 is a diagram showing a structure of an insulated gate semiconductor element.
FIG. 3A is a diagram showing CV characteristics of an oxide insulating film / silicon carbide interface according to the silicon carbide semiconductor element of the present invention and the method for forming the insulating film thereof.
(b) It is a figure which shows the CV characteristic of the oxide insulating film / silicon carbide interface by the formation method of the insulating film of the prior art example.
[Explanation of symbols]
1 Substrate
2 steps
3 Insulating film / silicon carbide substrate interface
4 Oxide insulating film
5 (0001) terrace
6 (11-20) sides
7 Oxidation set temperature
8 First annealing set temperature
9 Second annealing set temperature
21 Insulated gate type semiconductor device
22 n-type substrate
23 n-type epitaxial growth layer (n-type layer)
24 p-type part (p-type layer)
25 n + type layer
26 Oxide insulating film
27a Gate electrode
27b Ohmic junction of source electrode
27c drain electrode
27d Schottky junction part of source electrode
28 channel area

Claims

A silicon carbide substrate including a step having a height of 2 atomic layers or more on the surface; and an oxide insulating film formed on the surface of the silicon carbide substrate, wherein the silicon carbide substrate is formed of β-SiC (111), 6H, 4H Α-SiC (0001) such as, Si surface of 15R-SiC, α-SiC (1-100) and / or α-SiC such as β-SiC (100), β-SiC (110), 6H, 4H ( 11-20) is a silicon carbide substrate having an off-cut plane of 1 to 10 degrees of the crystal plane selected from the crystal planes, and the interface state density Nit between the oxide film and silicon carbide is 1.5 × 10 ¹² cm ^{−. 2.} A silicon carbide semiconductor element characterized by being ² or less and having a withstand voltage of 10 MVcm ⁻¹ or more.

A silicon carbide semiconductor device including a silicon carbide substrate including a step having a height of two atomic layers or more on the surface and an oxide insulating film formed on the surface of the silicon carbide substrate is set to a plurality of set temperatures in an atmosphere containing oxygen. In the method for forming an insulating film of a silicon carbide semiconductor that is annealed and maintained,
As the silicon carbide substrate, α-SiC (0001) such as β-SiC (111), 6H, 4H, Si surface of 15R-SiC, β-SiC (100), β-SiC (110), 6H, 4H, etc. A silicon carbide substrate having an off-cut plane of 1 to 10 degrees of a crystal plane selected from α-SiC (1-100) and / or α-SiC (11-20) of
The first annealing process is performed at 900 ° C. or higher in an atmosphere containing oxygen, and then the second annealing process is performed at a temperature of 850 ° C. or lower, which is a set temperature lower than the first annealing setting temperature. The interface state density Nit between the oxide film and silicon carbide is 1.5 × 10 5 including n annealings (n ≧ 2) in an atmosphere containing oxygen maintained at two or more different set temperatures. ^The method for forming an insulating film, wherein the insulating film is ¹² cm ⁻² or less and the withstand voltage is 10 MVcm ⁻¹ or more.

The method according to claim 2, wherein the annealing treatment in an atmosphere containing at least the nth oxygen is a wet oxygen atmosphere.