JP2003209251A - Silicon carbide semiconductor element and method for forming its insulation film - Google Patents

Silicon carbide semiconductor element and method for forming its insulation film

Info

Publication number
JP2003209251A
JP2003209251A JP2002003834A JP2002003834A JP2003209251A JP 2003209251 A JP2003209251 A JP 2003209251A JP 2002003834 A JP2002003834 A JP 2002003834A JP 2002003834 A JP2002003834 A JP 2002003834A JP 2003209251 A JP2003209251 A JP 2003209251A
Authority
JP
Japan
Prior art keywords
silicon carbide
insulating film
sic
semiconductor device
annealing treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002003834A
Other languages
Japanese (ja)
Other versions
JP3697211B2 (en
Inventor
Masato Yoshikawa
正人 吉川
Hisayoshi Ito
久義 伊藤
Makoto Kitahata
真 北畠
Masaya Yamashita
賢哉 山下
Osamu Kusumoto
修 楠本
Masao Uchida
正雄 内田
Kunimasa Takahashi
邦方 高橋
Ryoko Miyanaga
良子 宮永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Atomic Energy Agency
Panasonic Holdings Corp
Original Assignee
Japan Atomic Energy Research Institute
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Atomic Energy Research Institute, Matsushita Electric Industrial Co Ltd filed Critical Japan Atomic Energy Research Institute
Priority to JP2002003834A priority Critical patent/JP3697211B2/en
Publication of JP2003209251A publication Critical patent/JP2003209251A/en
Application granted granted Critical
Publication of JP3697211B2 publication Critical patent/JP3697211B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Formation Of Insulating Films (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulation film of a silicon carbide semiconductor element in which an interface state density sufficient as the semiconductor element is reduced in the insulation film/silicon carbide interface of the semiconductor element, and to provide a method for forming the same. <P>SOLUTION: The silicon carbide semiconductor element comprises a silicon carbide board having a step including a height of two atomic layers or more on a surface, and an oxide film formed on a surface of the silicon carbide board so that an interface state density of the oxide film and a silicon carbide is 1.5×10<SP>12</SP>cm<SP>-2</SP>or less. The method for forming the insulation film of the silicon carbide semiconductor element comprises the steps of holding a plurality of set temperatures in an atmosphere containing an oxygen, annealing the film, second time annealing at a temperature set lower than the first time annealing set temperature continued to the first time annealing, and annealing n times (n≥2) in the atmosphere containing the oxygen held at at least two more different temperatures. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、炭化珪素により構
成される炭化珪素半導体素子、特にパワーMOS半導体素
子のゲート絶縁膜及びその形成方法に関する物で、特
に、高速・高耐圧・低損失のパワー半導体素子を実現可
能にするものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device made of silicon carbide, particularly to a gate insulating film of a power MOS semiconductor device and a method for forming the same, and particularly to a high speed, high breakdown voltage and low loss power. This makes it possible to realize a semiconductor device.

【0002】[0002]

【従来の技術】従来例1として述べる従来の炭化珪素に
より構成される絶縁ゲート型半導体素子21は、図2の
ごとく、n型の基板22上にn型のエピタキシャル成長
層(n型層)23を形成し、その一部に例えばAlの様な
p型半導体を形成する不純物を拡散又はイオン打ち込み
することによりp型の部分24を形成し、p型の部分の
表面近傍の一部に例えばNの様なn型半導体を形成する
不純物を拡散又はイオン打ち込みすることによりn型の
部分25を形成する。上記n型層23が表面に達してい
る部分と上記n型の部分25とに挟まれたp型の部分2
4の表面に酸化絶縁膜26を形成し、更にその表面にゲ
ート電極27aを設ける。ドレイン電極27cは基板裏面
に形成し、ソース電極27bはn型の部分25、p型の部
分24にコンタクトして形成される。この絶縁ゲート型
半導体素子は、ゲート電極27aへのバイアスによってp
型の部分24の表面に形成される反転層がチャンネルと
して作用して機能する。
2. Description of the Related Art An insulated gate type semiconductor device 21 made of conventional silicon carbide described as Conventional Example 1 has an n type epitaxial growth layer (n type layer) 23 on an n type substrate 22 as shown in FIG. Then, a p-type portion 24 is formed by diffusing or ion-implanting an impurity forming a p-type semiconductor such as Al into a part of the formed p-type semiconductor. The n-type portion 25 is formed by diffusing or ion-implanting impurities forming such an n-type semiconductor. The p-type portion 2 sandwiched between the portion where the n-type layer 23 reaches the surface and the n-type portion 25.
An oxide insulating film 26 is formed on the surface of No. 4, and a gate electrode 27a is further provided on the surface. The drain electrode 27c is formed on the back surface of the substrate, and the source electrode 27b is formed in contact with the n-type portion 25 and the p-type portion 24. This insulated gate type semiconductor device is p-typed by the bias applied to the gate electrode 27a.
The inversion layer formed on the surface of the mold portion 24 functions as a channel.

【0003】この従来技術の内容は、例えば Silicon C
arbide; A Review of FundamentalQuestions and Appli
cations to Current Device Technology, edited by W.
J.Choyke,H.Matsunami, and G.Pensl, Akademie Verlag
1997 の Vol.II pp.369-388 に開示されている。炭化
珪素半導体素子は、炭化珪素が有する物性の、ワイドギ
ャップ性・高絶縁耐圧・十分な移動度・高い熱伝導性を
生かして、低損失の高温でも動作する省エネルギーに寄
与する半導体素子を提供することが期待されている。
The contents of this prior art are, for example, Silicon C
arbide; A Review of FundamentalQuestions and Appli
cations to Current Device Technology, edited by W.
J. Choyke, H. Matsunami, and G. Pensl, Akademie Verlag
It is disclosed in Vol.II pp.369-388 of 1997. A silicon carbide semiconductor element provides a semiconductor element that contributes to energy saving by operating at high temperature with low loss, by utilizing the physical properties of silicon carbide, such as wide gap property, high dielectric strength, sufficient mobility, and high thermal conductivity. Is expected.

【0004】しかし、従来の炭化珪素半導体素子、特に
MOSFET等の酸化絶縁膜/炭化珪素界面を含む半導体素子
は、上記酸化絶縁膜/炭化珪素界面の特性が不十分で、
実用に耐えるモノではなかった。上記絶縁ゲート型半導
体素子を形成する場合にチャンネル部の表面に形成され
る酸化絶縁膜26は、イオン打ち込み等で素子パターン
が形成された炭化珪素基板を酸化処理することにより形
成される。更に、酸化絶縁膜を形成した後の酸化絶縁膜
を形成した場合の温度よりも低温での酸素を含む雰囲気
での処理をする再酸化アニールが、酸化絶縁膜及び酸化
絶縁膜/炭化珪素界面を高性能化することは報告されて
いる。
However, conventional silicon carbide semiconductor devices, especially
A semiconductor element including an oxide insulating film / silicon carbide interface such as MOSFET has insufficient characteristics at the oxide insulating film / silicon carbide interface.
It wasn't practical. The oxide insulating film 26 formed on the surface of the channel portion when the above-mentioned insulated gate semiconductor element is formed is formed by oxidizing the silicon carbide substrate on which the element pattern is formed by ion implantation or the like. Further, reoxidation annealing for treating in an atmosphere containing oxygen at a temperature lower than the temperature when the oxide insulating film is formed after the oxide insulating film is formed is used to remove the oxide insulating film and the oxide insulating film / silicon carbide interface. Higher performance has been reported.

【0005】このような従来の酸化膜形成法は、例えば
文献P-type SiC MOS reliability with improved oxida
tion procedures and aluminum or boron p-type dopan
ts,L.A.Lipkin and J.W.Palmour , proceedings of hig
h temperature electronicsXIV-15-XIV-20にもあるよう
に、酸化温度よりも低い温度の酸化雰囲気に、形成され
た酸化膜を曝し、界面近傍に存在する残留不純物を再度
酸化して電気特性低下の原因となる界面準位密度を減少
させようとする試み(再酸化)である。これまで再酸化
に利用する温度は一種類に限られていた。
Such a conventional oxide film forming method is disclosed in, for example, the literature P-type SiC MOS reliability with improved oxida.
tion procedures and aluminum or boron p-type dopan
ts, LALipkin and JW Palmour, proceedings of hig
As shown in h temperature electronics XIV-15-XIV-20, the formed oxide film is exposed to an oxidizing atmosphere at a temperature lower than the oxidation temperature, and the residual impurities existing near the interface are oxidized again to reduce the electrical characteristics. This is an attempt (reoxidation) to reduce the interface state density that is the cause. Until now, the temperature used for reoxidation was limited to one type.

【0006】これらの従来の炭化珪素半導体素子の絶縁
膜の形成方法は、酸化絶縁膜/炭化珪素界面の界面準位
密度を減少させることは確かであるが、半導体素子とし
て十分な界面準位密度までには、更にもう一桁以上の減
少が必要で、絶縁膜の形成方法としては不十分であっ
た。更に耐圧に関しても、1MVcm-1以下の場合が多く、
不十分であった。高耐圧素子実現のためには10MVcm-1
度の耐圧は必要である。また、上記従来例の酸化絶縁膜
/炭化珪素界面の界面準位密度Nitは1×101 3cm
-2以上有り、この絶縁膜を用いて形成した図2の炭化珪
素半導体素子MOSFETは、10cm2/Vs程度の
低いチャンネル移動度を示し、実用に耐えるような半導
体素子のためには不十分であった。
Although these conventional methods of forming an insulating film of a silicon carbide semiconductor element certainly reduce the interface state density of the oxide insulating film / silicon carbide interface, the interface state density sufficient for a semiconductor element is obtained. By the time, it was necessary to further decrease by one digit or more, which was insufficient as a method for forming an insulating film. Furthermore, with respect to the breakdown voltage, in many cases it is less than 1MVcm -1 ,
It was insufficient. A breakdown voltage of about 10 MVcm -1 is necessary to realize a high breakdown voltage element. In addition, the oxide insulating film of the above conventional example
/ Interface state density Nit of silicon carbide interface 1 × 10 1 3 cm
-2 or more, and the silicon carbide semiconductor device MOSFET of FIG. 2 formed by using this insulating film has a low channel mobility of about 10 cm 2 / Vs, which is not sufficient for a practical semiconductor device. there were.

【0007】[0007]

【発明が解決しようとする課題】実用に耐える炭化珪素
半導体素子実現のためには、最低でも2×1012cm-2
以下の界面準位密度Nit、100cm2/Vs以上の
チャンネル移動度が必要である。このチャンネル移動度
が達成されれば、MOSFETのチャンネル抵抗が減少
して、数百ボルト耐圧のパワー素子の場合のドリフト移
動度とコンパラになり、パワー素子として実用に耐える
半導体素子となる。
SUMMARY OF THE INVENTION In order to realize a silicon carbide semiconductor device that can withstand practical use, at least 2 × 10 12 cm -2
The following interface state density Nit and channel mobility of 100 cm 2 / Vs or more are required. When this channel mobility is achieved, the channel resistance of the MOSFET is reduced to be in parallel with the drift mobility in the case of a power device with a withstand voltage of several hundreds of volts, and the semiconductor device can be practically used as a power device.

【0008】この従来技術の課題を克服し、本発明は、
炭化珪素などのワイドギャップ半導体の性質を生かした
低損失・高耐圧半導体素子を実現することを目的とす
る。
Overcoming the problems of the prior art, the present invention provides
It is an object of the present invention to realize a low loss and high breakdown voltage semiconductor element that makes use of the properties of a wide gap semiconductor such as silicon carbide.

【0009】[0009]

【課題を解決するための手段】上記従来例において、酸
化絶縁膜の絶縁耐圧が小さく不十分であること、および
準位密度が大きく不十分であることに対して、本発明者
らが検討した結果、次のようなことが明らかとなった。
つまり、現在使用されている炭化珪素半導体基板の表面
がα-SiC(0001)offcut面を用いており、表面にα-SiC(0
001)テラスと(1-210)ステップを含むことが、絶縁耐圧
が低く準位密度が大きいことの原因となっていること
を、本発明者らは発見し、この発見に基づき本発明の絶
縁膜の形成方法を発明した。
DISCLOSURE OF THE INVENTION In the above-mentioned conventional example, the present inventors have examined that the dielectric strength of the oxide insulating film is small and insufficient and that the level density is large and insufficient. As a result, the following things became clear.
That is, the surface of the silicon carbide semiconductor substrate currently used uses the α-SiC (0001) offcut surface, and the surface has α-SiC (0001) offcut surface.
The present inventors have found that the inclusion of the (001) terrace and the (1-210) step is the cause of the low withstand voltage and the high level density, and based on this finding, the insulation of the present invention was found. A method of forming a film was invented.

【0010】α-SiC(0001)面(Si面)と(1-210)面におい
て、酸化速度が異なることは、例えばSilicon Carbide;
A Review of Fundamental Questions and Application
s to Current Device Technology, edited by W.J.Choy
ke,H.Matsunami, and G.Pensl,Akademie Verlag 1997
の Vol.II pp.369-388 に開示されており知られている
が、酸化絶縁膜/炭化珪素界面の特性に対しての評価は
不十分であった。酸化絶縁膜の形成方法に対しても、そ
の評価に基づいた最適化はされておらず、本発明者らに
よって初めて明らかとなった評価結果に基づき、最適な
絶縁膜の形成方法が確立され、さらにこれを用いた従来
無かった炭化珪素半導体素子が発明された。
The difference in the oxidation rate between the α-SiC (0001) plane (Si plane) and the (1-210) plane is, for example, Silicon Carbide;
A Review of Fundamental Questions and Application
s to Current Device Technology, edited by WJChoy
ke, H.Matsunami, and G.Pensl, Akademie Verlag 1997
No. Vol.II pp.369-388, but the evaluation of the characteristics of the oxide insulating film / silicon carbide interface was insufficient. Even for the method of forming the oxide insulating film, optimization based on the evaluation has not been made, and based on the evaluation result first revealed by the present inventors, the optimum method of forming the insulating film is established. Furthermore, a silicon carbide semiconductor device using this has been invented, which has never existed in the past.

【0011】本発明の炭化珪素半導体素子は、2原子層
(モノレイヤー)以上の高さを有するステップを含む炭
化珪素基板と、上記炭化珪素基板表面に形成された酸化
膜を含み、酸化膜と炭化珪素の界面準位密度Nitが
1.5×1012cm-2以下であることを特徴とする。
A silicon carbide semiconductor device of the present invention includes a silicon carbide substrate including a step having a height of two atomic layers (monolayer) or more, and an oxide film formed on the surface of the silicon carbide substrate. The interface state density Nit of silicon carbide is 1.5 × 10 12 cm −2 or less.

【0012】上記発明の炭化珪素半導体素子において、
2原子層以上の高さを有するステップを含む炭化珪素基
板が、β-SiC(111)、6H,4H等のα-SiC(0001)、15R-SiC
のSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα-SiC
(1-100)及び/又はα-SiC(11-20)の内から選ばれる結晶
面の1度以上のオフカット面を表面とする炭化珪素基板
であると好ましい。
In the silicon carbide semiconductor device of the above invention,
Silicon carbide substrates including steps having a height of two atomic layers or more are β-SiC (111), α-SiC (0001) such as 6H, 4H, 15R-SiC
Si surface, β-SiC (100), β-SiC (110), α-SiC such as 6H, 4H
It is preferable that the silicon carbide substrate has an off-cut surface of one or more crystal faces selected from (1-100) and / or α-SiC (11-20) as a surface.

【0013】本発明の炭化珪素半導体素子の絶縁膜の形
成方法は、2原子層以上の高さを有するステップを含む
炭化珪素基板と、上記炭化珪素基板表面に形成された酸
化膜を含む炭化珪素半導体素子を、酸素を含む雰囲気下
で複数の設定温度に保ってアニール処理を施す炭化珪素
半導体素子の絶縁膜の形成方法であって、1回目のアニ
ール処理に続いて、上記1回目のアニール処理設定温度
よりも低い設定温度で2回目のアニール処理を施し、少
なくとも2つ以上の異なる設定温度で保たれた酸素を含
む雰囲気下でのn回(n≧2)のアニール処理を含むことを
特徴とする。
A method of forming an insulating film of a silicon carbide semiconductor device according to the present invention includes a silicon carbide substrate including a step having a height of two atomic layers or more, and a silicon carbide including an oxide film formed on the surface of the silicon carbide substrate. A method of forming an insulating film of a silicon carbide semiconductor element, comprising: annealing a semiconductor element at a plurality of set temperatures in an atmosphere containing oxygen, the method comprising: a first annealing treatment; Characterized by performing a second annealing treatment at a set temperature lower than the set temperature and performing n times (n ≧ 2) of the annealing treatment under an atmosphere containing oxygen kept at at least two different set temperatures. And

【0014】上記発明の炭化珪素半導体素子の絶縁膜の
形成方法において、1回目の酸素を含む雰囲気下でのア
ニール処理が900℃以上であり、設定温度が850℃
以下であるn回目のアニール処理を少なくとも含むと好
ましい。
In the method for forming an insulating film of a silicon carbide semiconductor device according to the above invention, the first annealing treatment in an atmosphere containing oxygen is 900 ° C. or higher, and the set temperature is 850 ° C.
It is preferable to include at least the following n-th annealing treatment.

【0015】さらに上記発明の炭化珪素半導体素子の絶
縁膜の形成方法において、少なくともn回目の酸素を含
む雰囲気下でのアニール処理がウェット酸素雰囲気であ
ることと好ましい。
Further, in the method for forming an insulating film of a silicon carbide semiconductor element according to the present invention, it is preferable that the annealing treatment at least n times in an atmosphere containing oxygen is a wet oxygen atmosphere.

【0016】[0016]

【発明の実施の形態】本発明の炭化珪素半導体素子は、
図1(a)の絶縁膜/炭化珪素界面の拡大図に示したよう
な、2原子層以上の高さを有するステップ2を含む炭化
珪素基板1と、上記炭化珪素基板表面に形成された酸化
膜4を含み、酸化絶縁膜4と炭化珪素1の界面3での界
面準位密度Nitが1.5×1012cm-2以下であるこ
とを特徴とする絶縁膜4を含むことを特徴とする。
BEST MODE FOR CARRYING OUT THE INVENTION The silicon carbide semiconductor device of the present invention comprises:
As shown in the enlarged view of the insulating film / silicon carbide interface in FIG. 1 (a), the silicon carbide substrate 1 including step 2 having a height of two atomic layers or more, and the oxide formed on the surface of the silicon carbide substrate. An insulating film 4 including the film 4, wherein the interface state density Nit at the interface 3 between the oxide insulating film 4 and the silicon carbide 1 is 1.5 × 10 12 cm −2 or less. To do.

【0017】2モノレイヤー以上の高さを有するステッ
プ2を含むオフカット炭化珪素基板1を利用した半導体
素子、特に高パワー用の縦型絶縁ゲート型半導体素子(M
OSFET)において、上記絶縁膜/炭化珪素の低い界面準位
密度は、本発明により初めて実現されたもので、界面準
位密度Nitが1.5×1012cm-2以下の範囲でチャ
ンネル抵抗がドリフト抵抗と同レベルとなることが初め
て確認された。
A semiconductor device using an off-cut silicon carbide substrate 1 including a step 2 having a height of two monolayers or more, particularly a vertical insulated gate semiconductor device (M) for high power.
In the case of OSFET), the low interface state density of the insulating film / silicon carbide was realized for the first time by the present invention, and the channel resistance in the range where the interface state density Nit is 1.5 × 10 12 cm −2 or less is obtained. It was confirmed for the first time that it was at the same level as the drift resistance.

【0018】この低界面準位密度の絶縁膜/炭化珪素界
面を利用することにより、大電流制御可能なMOS半導
体素子が実現できることを確認した。界面準位密度Ni
tが1.5×1012cm-2以上となると、MOSFET
半導体素子を形成した場合に、チャンネル抵抗がドリフ
ト抵抗よりも一桁以上大きくなり、損失が大きくなり、
大電流制御パワー半導体素子として適さないことを確認
した。
It was confirmed that a MOS semiconductor device capable of controlling a large current can be realized by utilizing this insulating film / silicon carbide interface having a low interface state density. Interface state density Ni
When t becomes 1.5 × 10 12 cm -2 or more, the MOSFET
When a semiconductor element is formed, the channel resistance becomes one digit or more larger than the drift resistance, and the loss becomes large.
It was confirmed that it is not suitable as a large current control power semiconductor device.

【0019】上記本発明の炭化珪素半導体素子におい
て、2原子層以上の高さを有するステップを含む炭化珪
素基板が、β-SiC(111)、6H,4H等のα-SiC(0001)、15
R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα
-SiC(1-100)及び/又はα-SiC(11-20)の内から選ばれる
結晶面の1度以上のオフカット面を表面とする炭化珪素
基板であると好ましいことを確認した。ここで、オフカ
ットの角度が1度以下の基板に対しては良好な結晶性の
エピタキシャル膜を成長させることが難しいため、好ま
しくなかった。また、オフカットの角度が10度以下の
基板に対して本発明の実現が容易であることを確認し
た。ここで炭化珪素基板の10度以上のオフ角度につい
ては良好なエピタキシャル膜を得ることが難しく、本発
明の良好な絶縁膜を形成することも難しい場合があっ
た。
In the above-described silicon carbide semiconductor device of the present invention, the silicon carbide substrate including steps having a height of two atomic layers or more is α-SiC (111), 6H, 4H or the like α-SiC (0001), 15
Si surface of R-SiC, β-SiC (100), β-SiC (110), α of 6H, 4H, etc.
It has been confirmed that a silicon carbide substrate having an off-cut surface of one or more crystal faces selected from -SiC (1-100) and / or α-SiC (11-20) as a surface is preferable. Here, since it is difficult to grow an epitaxial film having good crystallinity on a substrate having an off-cut angle of 1 degree or less, it is not preferable. Further, it was confirmed that the present invention can be easily realized for a substrate having an off-cut angle of 10 degrees or less. Here, it was difficult to obtain a good epitaxial film for the off angle of 10 degrees or more of the silicon carbide substrate, and it was sometimes difficult to form a good insulating film of the present invention.

【0020】本発明の炭化珪素半導体素子の絶縁膜の形
成方法は、炭化珪素の酸化処理中に図1(b)の様に、酸
化処理温度を変化させる。通常1000℃以上の高温で
の酸化処理7の後に、(再酸化)アニール処理を施す。
つまり、一般に使われているSiCエピ膜は、3.5度から8
度程度(11−20)方向へのOFF角をもった炭化珪素
基板上1に成長されており、その表面3は物理的には図
1(a)に示したように(0001)面5と(11−2
0)面6から構成される。特に2原子層以上の高さを有
するステップ2を含む炭化珪素基板1において、(00
01)面5からのOFF角が8度にも及ぶ基板では、図1
(a)に示したように基板表面の14%が(11−20)
面6によって構成される。SiCエピ膜の酸化速度は、
(0001)面に比べて(11−20)面では3倍ほど
早く厚い酸化絶縁膜が形成され、従来例の説明で述べた
残留する不純物を消失させるための再酸化アニール処理
における最適な酸化温度も異なっている。
In the method for forming an insulating film of a silicon carbide semiconductor element according to the present invention, the oxidation treatment temperature is changed as shown in FIG. 1 (b) during the oxidation treatment of silicon carbide. Usually, (reoxidation) annealing treatment is performed after the oxidation treatment 7 at a high temperature of 1000 ° C. or higher.
In other words, the commonly used SiC epi film is from 3.5 degrees to 8 degrees.
It is grown on a silicon carbide substrate 1 having an OFF angle in the direction of (11-20) degrees, and its surface 3 is physically (0001) plane 5 as shown in FIG. 1 (a). (11-2
0) It is composed of plane 6. In particular, in the silicon carbide substrate 1 including the step 2 having a height of 2 atomic layers or more, (00
For a substrate whose OFF angle from the (01) plane 5 reaches 8 degrees,
As shown in (a), 14% of the substrate surface is (11-20)
It is constituted by the surface 6. The oxidation rate of the SiC epi film is
A thick oxide insulating film is formed about 3 times faster in the (11-20) plane than in the (0001) plane, and the optimum oxidation temperature in the reoxidation annealing treatment for eliminating the residual impurities described in the description of the conventional example. Is also different.

【0021】本発明の炭化珪素半導体素子の絶縁膜の形
成方法は、(0001)面に対して酸素を含む雰囲気下
での再酸化アニール処理8を行った後、(11−20)
面に対して酸素を含む雰囲気下での再酸化アニール処理
9を行う2段アニーリングを基本とする。(0001)
面は(11−20)面に比べ酸化されにくいため、(0
001)面に対する再酸化アニール処理は高温を必要と
する。この(0001)面に対する高温の設定温度での
1回目の再酸化アニール処理8を行った後、この1回目
の再酸化アニール処理8の設定温度よりも低い温度で
(11−20)面を再酸化アニール処理9を行うことが
有効であった。
According to the method of forming an insulating film of a silicon carbide semiconductor element of the present invention, after performing reoxidation annealing treatment 8 on an (0001) plane in an atmosphere containing oxygen, (11-20)
It is based on a two-step annealing in which reoxidation annealing treatment 9 is performed on the surface in an atmosphere containing oxygen. (0001)
The face is less likely to be oxidized than the (11-20) face, so (0
The reoxidation annealing process for the (001) plane requires high temperature. After performing the first reoxidation annealing treatment 8 on the (0001) plane at a high set temperature, the (11-20) plane is regenerated at a temperature lower than the set temperature of the first reoxidation annealing treatment 8. It was effective to perform the oxidation annealing treatment 9.

【0022】上述の(11-20)面については、(0001)面と
直交する面で有れば、例えば(1-100)面でも同様の効果
が確認され、本発明は有効であった。つまり、本発明の
上記2段アニール処理を施すことにより、高耐圧の準位
密度の少ない炭化珪素上の酸化絶縁膜が形成可能となっ
た。この後に、アニール処理を更に付加して、n回のア
ニール処理を施してもnが2以上で有れば本発明は実現
できた。
Regarding the above-mentioned (11-20) plane, if it is a plane orthogonal to the (0001) plane, the same effect was confirmed for the (1-100) plane, and the present invention was effective. That is, by performing the above-described two-step annealing treatment of the present invention, it becomes possible to form an oxide insulating film on silicon carbide having a high breakdown voltage and a low level density. After that, even if annealing treatment is further added and annealing treatment is performed n times, the present invention can be realized as long as n is 2 or more.

【0023】上には、(0001)Si面のオフカット面の炭化
珪素基板の場合を示したが、一般には上述の(000
1)面と(11−20)面、更には(0001)面と直交する
例えば(1-100)面などの同等の面から構成されるオフカ
ット面に対して本発明は有効であることを確認した。つ
まり、本発明の炭化珪素半導体素子およびその絶縁膜の
形成方法は、表面に形成された酸化膜を含み、β-SiC(1
11)、6H,4H等のα-SiC(0001)、15R-SiCのSi面、β-SiC
(100)、β-SiC(110)、6H,4H等のα-SiC(1-100)及び/又
はα-SiC(11-20)の内から選ばれる結晶面の1度以上の
オフカット面を表面とする炭化珪素基板について有効で
あることを確認した。
The case of a silicon carbide substrate having an off-cut surface of a (0001) Si surface is shown above, but in general, the above-mentioned (000
The present invention is effective for off-cut planes composed of 1) plane, (11-20) plane, and equivalent planes such as (1-100) plane orthogonal to (0001) plane. confirmed. That is, a method for forming a silicon carbide semiconductor device and an insulating film therefor according to the present invention includes an oxide film formed on the surface of β-SiC (1
11), 6H, 4H, etc. α-SiC (0001), 15R-SiC Si surface, β-SiC
(100), β-SiC (110), 6H, 4H etc. α-SiC (1-100) and / or α-SiC (11-20) selected from the crystal planes of 1 or more off-cut plane It was confirmed to be effective for a silicon carbide substrate having a surface of.

【0024】つまり、上記オフカット面であり、図1
(a)に示したように、2原子層以上の高さを有するステ
ップ2を含む炭化珪素基板1と、上記炭化珪素基板表面
3に形成された酸化膜4を含む炭化珪素半導体素子を、
酸素を含む雰囲気下で複数の設定温度に保ってアニール
処理を施す炭化珪素半導体素子の絶縁膜の形成方法であ
って、1回目のアニール処理に続いて、上記1回目のア
ニール処理設定温度よりも低い設定温度で2回目のアニ
ール処理を施し、少なくとも2つ以上の異なる設定温度
で保たれた酸素を含む雰囲気下でのn回(n≧2)のアニ
ール処理を含むと有効であることを確認した。
That is, the above-mentioned off-cut surface is shown in FIG.
As shown in (a), a silicon carbide semiconductor device including a silicon carbide substrate 1 including step 2 having a height of two atomic layers or more, and a silicon carbide semiconductor element including an oxide film 4 formed on the surface 3 of the silicon carbide substrate,
A method of forming an insulating film of a silicon carbide semiconductor element, comprising performing annealing treatment while maintaining a plurality of preset temperatures in an atmosphere containing oxygen, wherein the first annealing treatment is followed by a temperature higher than the first annealing treatment setting temperature. Confirmed that it is effective to perform the second annealing treatment at a low set temperature and to include n times (n ≧ 2) annealing treatment in an atmosphere containing oxygen kept at at least two different set temperatures. did.

【0025】さらに、酸素を含む雰囲気下でのアニール
処理を1000℃以下で行うと、本発明の実現が容易で
あることを確認した。ここで酸素を含む雰囲気下でのア
ニール処理を1000℃以上で行うと、上記アニール処
理中に酸化膜/炭化珪素界面で酸化が進み、界面に残留
する不純物が増加してしまい、本発明の良好な絶縁膜を
形成するが出来ないことも確認した。
Further, it was confirmed that the present invention can be easily realized by carrying out the annealing treatment in an atmosphere containing oxygen at 1000 ° C. or lower. Here, if the annealing treatment in an atmosphere containing oxygen is performed at 1000 ° C. or higher, the oxidation progresses at the oxide film / silicon carbide interface during the annealing treatment, and the impurities remaining at the interface increase, which is favorable for the present invention. It was also confirmed that a good insulating film could not be formed.

【0026】また、本発明の炭化珪素半導体素子および
その絶縁膜の形成方法は、1回目の酸素を含む雰囲気下
でのアニール処理8の設定温度が900℃以上であり、
2回目以降のアニール処理9の設定温度が850℃以下
であると好ましい。1回目の酸素を含む雰囲気下でのア
ニール処理8の設定温度が900℃以下となると、(0
001)面に対して酸素を含む雰囲気下での再酸化アニ
ールにより残留する不純物を消失させることが十分出来
ず、本発明の良好な絶縁膜の形成が難しい。また、2回
目以降のアニール処理9の設定温度が850℃以上であ
ると、(0001)面と垂直な例えば(11−20)面を再酸
化アニール処理を行い不純物を消失させる間に、一回目
の再酸化アニールにより正常化された酸化膜/炭化珪素
界面の酸化が進み界面が再びあれてしまい、本発明の良
好な絶縁膜の形成が難しかった。
Further, in the method for forming a silicon carbide semiconductor device and the insulating film thereof according to the present invention, the set temperature of the first annealing treatment 8 in an atmosphere containing oxygen is 900 ° C. or higher,
It is preferable that the set temperature of the second and subsequent annealing processes 9 is 850 ° C. or lower. When the set temperature of the annealing process 8 in the first atmosphere containing oxygen becomes 900 ° C. or lower, (0
The remaining impurities cannot be sufficiently eliminated by reoxidation annealing in an atmosphere containing oxygen with respect to the (001) plane, and it is difficult to form a good insulating film of the present invention. Further, when the set temperature of the second and subsequent annealing treatments 9 is 850 ° C. or higher, for example, the first oxidation treatment is performed on the (11-20) plane perpendicular to the (0001) plane to eliminate impurities. Oxidation of the oxide film / silicon carbide interface normalized by the reoxidation anneal progresses and the interface is reopened, making it difficult to form a good insulating film of the present invention.

【0027】さらに、本発明の炭化珪素半導体素子およ
びその絶縁膜の形成方法は、1回目の酸素を含む雰囲気
下でのアニール処理8がウェット酸素雰囲気であり、2
回目以降のアニール処理9もウェット酸素雰囲気である
と好ましい。酸素を含む雰囲気下でのアニール処理が水
蒸気を含むウェット酸素雰囲気であると、上記ウェット
酸素雰囲気でのアニール処理がn回の内の1回のみであ
っても、上記界面に残留する不純物の除去の効率が高く
なり、有効であった。
Further, in the method for forming a silicon carbide semiconductor element and the insulating film thereof according to the present invention, the first annealing treatment 8 in an atmosphere containing oxygen is a wet oxygen atmosphere.
It is preferable that the annealing treatment 9 after the first time also be in a wet oxygen atmosphere. When the annealing treatment in the atmosphere containing oxygen is a wet oxygen atmosphere containing water vapor, even if the annealing treatment in the wet oxygen atmosphere is performed only once in n times, the impurities remaining at the interface are removed. Was more efficient and effective.

【0028】上述の本発明の炭化珪素半導体素子の絶縁
膜の形成方法を用いて、初めて、絶縁膜と炭化珪素の界
面準位密度Nitが1.5×1012cm-2以下である酸
化絶縁膜が形成された。この低い界面準位密度(Nit
が1.5×1012cm-2以下)を有する絶縁膜は、例え
ば図2に示したような構造の、移動度の高い大電流を制
御可能な炭化珪素半導体素子MOSFETを初めて実現した。
For the first time, using the above-described method for forming an insulating film of a silicon carbide semiconductor element according to the present invention, an oxide insulating film in which the interface state density Nit between the insulating film and silicon carbide is 1.5 × 10 12 cm −2 or less. A film was formed. This low interface state density (Nit
For the first time, an insulating film having a thickness of 1.5 × 10 12 cm −2 ) has realized a silicon carbide semiconductor device MOSFET having a structure as shown in FIG. 2 and having a high mobility and capable of controlling a large current.

【0029】[0029]

【実施例】(実施例1)実施例1として本発明の炭化珪
素半導体素子の第一の実施例を図2を用いて説明する。
本発明の炭化珪素半導体素子の実施例1の絶縁ゲート型
半導体素子21は、図2のごとく、5×1018cm-3のドー
プ濃度のn型の基板22上に5×1015cm-3のドープ濃度
のn型のエピタキシャル成長層(n型層)23を10ミ
クロンの厚さで形成し、その一部にAl(p型半導体を形
成する不純物)イオン打ち込みすることによりp型の部
分24を5×1017cm-3の濃度で2ミクロンの厚さで形成
し、p型の部分の表面近傍の一部にn型半導体を形成す
るN不純物をイオン打ち込みすることにより1019cm-3
ドープ濃度のn型の部分25を0.3ミクロンの厚さで形
成する。上記n型層23が表面に達している部分と上記
n型の部分25とに挟まれたp型の部分の表面に、本発
明の2原子層以上の高さを有するステップを含む炭化珪
素基板表面に形成された酸化膜であり、上記酸化膜と炭
化珪素の界面準位密度Nitが1.5×1012cm-2
下である酸化絶縁膜26を25nmの厚みで形成した。更に
その表面にAlのゲート電極27aを設けた。ドレイン電
極27cは基板裏面にNiを蒸着してアロイ化(熱処理10
00℃、5分)してオーミック電極として形成し、ソー
ス電極27bはn型の部分25とp型の部分24にオーミ
ックコンタクトするようにNiにより形成された。この絶
縁ゲート型半導体素子21は、ゲート電極27aへのバイ
アスによってp型の部分24の表面に形成される反転層
がチャンネル領域28として作用して、ドレインからソ
ースに向かって電流が流れ、ゲート電圧によってソース
・ドレイン電流が変調されFET動作をした。
EXAMPLES Example 1 As Example 1, a first example of the silicon carbide semiconductor device of the present invention will be described with reference to FIG.
The insulated gate semiconductor device 21 of Example 1 of the silicon carbide semiconductor device of the present invention is 5 × 10 15 cm -3 on an n-type substrate 22 having a doping concentration of 5 × 10 18 cm -3 as shown in FIG. An n-type epitaxial growth layer (n-type layer) 23 having a doping concentration of 10 μm is formed with a thickness of 10 μm, and Al (impurity forming a p-type semiconductor) ions are implanted into a part thereof to form the p-type portion 24. 5 × 10 17 cm at a concentration of -3 is formed by a 2 micron thick, by ion implantation of n dopant to form the n-type semiconductor in a portion near the surface of the p-type portion of 10 19 cm -3 An n-type portion 25 having a doping concentration is formed with a thickness of 0.3 micron. A silicon carbide substrate including a step having a height of two atomic layers or more of the present invention on the surface of a p-type portion sandwiched between the portion where the n-type layer 23 reaches the surface and the n-type portion 25. An oxide insulating film 26 formed on the surface and having an interface state density Nit of the oxide film and silicon carbide of 1.5 × 10 12 cm −2 or less was formed to a thickness of 25 nm. Further, an Al gate electrode 27a was provided on the surface thereof. The drain electrode 27c is alloyed by depositing Ni on the back surface of the substrate (heat treatment 10
The ohmic electrode was formed at 00 ° C. for 5 minutes, and the source electrode 27b was made of Ni so as to make ohmic contact with the n-type portion 25 and the p-type portion 24. In this insulated gate semiconductor device 21, the inversion layer formed on the surface of the p-type portion 24 by the bias to the gate electrode 27a acts as the channel region 28, and a current flows from the drain to the source to generate the gate voltage. The source / drain current was modulated by the FET operation.

【0030】この場合の、本発明の炭化珪素半導体素子
の実施例1として、ゲート長が2ミクロンでゲート幅が
500ミクロンの素子を形成した。ゲート電圧が10Vの
時の、10V印可時のソース・ドレインの電流は20mA以上
あった。一方、従来の絶縁膜つまり酸化膜と炭化珪素の
界面準位密度が1013cm-2以上である炭化珪素半導体
素子においては、上記本発明の第一の実施例の半導体素
子の実施例1と同様の大きさの半導体素子において同様
の条件で1mA以下の電流が流れるのみであることが確
認された。
As Example 1 of the silicon carbide semiconductor device of the present invention in this case, a device having a gate length of 2 microns and a gate width of 500 microns was formed. When the gate voltage was 10V, the source / drain current when applying 10V was more than 20mA. On the other hand, in the conventional silicon carbide semiconductor device having the interface state density of the insulating film, that is, the oxide film and silicon carbide of 10 13 cm -2 or more, the semiconductor device of Example 1 of the first embodiment of the present invention is It has been confirmed that a current of 1 mA or less only flows under the same condition in a semiconductor element having a similar size.

【0031】本発明者等は、本発明の半導体素子の酸化
絶縁膜は、上記酸化膜と炭化珪素の界面準位密度Nit
が1.5×1012cm-2以下であることを実施例2に述
べる方法により確認した。この低い界面準位密度Nit
=1.5×1012cm-2以上である場合には、上記ソー
ス・ドレイン電流値が著しく減少し、1mA以下となっ
てしまうことも確認した。つまり、上記酸化膜と炭化珪
素の界面準位密度Nitが1.5×1012cm-2以上で
あると、半導体素子の性能が著しく悪化し、実用に耐え
ないモノになってしまうことも確認した。
The present inventors have found that the oxide insulating film of the semiconductor element of the present invention is the interface state density Nit of the oxide film and silicon carbide.
Was 1.5 × 10 12 cm −2 or less by the method described in Example 2. This low interface state density Nit
= 1.5 × 10 12 cm −2 or more, it was also confirmed that the source / drain current value was remarkably reduced to 1 mA or less. That is, it was also confirmed that when the interface state density Nit of the oxide film and silicon carbide is 1.5 × 10 12 cm −2 or more, the performance of the semiconductor element is significantly deteriorated and the semiconductor element becomes unusable. did.

【0032】この場合、炭化珪素半導体素子の表面は、
SiC(0001)結晶面に対して8度オフカットした面であ
り、基板表面(絶縁膜/炭化珪素界面)に必ずステップ
を有する。ここで、上記絶縁膜/炭化珪素界面のステッ
プがバンチングしており、2原子層以上の高さのステッ
プを有する場合に、上記界面準位密度Nitが1.5×
1012cm-2以下であることが特に重要であることを確
認した。本発明により、ソース・ドレイン電流の著しい
増大が確認され、本発明の実用に耐える炭化珪素半導体
素子が実現された。
In this case, the surface of the silicon carbide semiconductor element is
The surface is off-cut by 8 degrees with respect to the SiC (0001) crystal plane, and always has a step on the substrate surface (insulating film / silicon carbide interface). Here, when the step of the insulating film / silicon carbide interface is bunching and has a step of a height of two atomic layers or more, the interface state density Nit is 1.5 ×
It has been confirmed that it is particularly important that it is 10 12 cm −2 or less. According to the present invention, a significant increase in the source / drain current was confirmed, and a silicon carbide semiconductor element that can withstand the practical use of the present invention was realized.

【0033】また、2原子層以上の高さを有するステッ
プを含む炭化珪素基板と、上記炭化珪素基板表面に形成
された酸化膜を含み、酸化膜と炭化珪素の界面準位密度
Nitが1.5×1012cm-2以下である本発明の半導
体素子において、上記実施例1の半導体素子のチャンネ
ル部分28にn型層を挿入したACCUFETを形成し
た場合には、100cm2/Vs以上のチャンネル移動
度が確認された。従来の同様な炭化珪素半導体素子のチ
ャンネル移動度は10cm2/Vs以下であり、本発明
により実用に耐える炭化珪素半導体素子が実現できるこ
とが確認された。本実施例1において形成されたMOS
FETは、そのon時のチャネル抵抗およびドリフト抵
抗を見積もると、ほぼ同等の桁の値となっており、低損
失のパワー素子が形成されていることが確認された。従来
の絶縁膜/炭化珪素界面を用いて、界面準位密度が1.5×1
012cm-2以上と大きい場合は、チャンネル抵抗がドリフト
抵抗に対して一桁以上大きな値となり、実用に耐えるも
のではなかった。
Further, it includes a silicon carbide substrate including a step having a height of two atomic layers or more, and an oxide film formed on the surface of the silicon carbide substrate, and the interface state density Nit of the oxide film and silicon carbide is 1. In the semiconductor device of the present invention having a size of 5 × 10 12 cm −2 or less, when an ACCUFET having an n-type layer inserted in the channel portion 28 of the semiconductor device of Example 1 is formed, a channel of 100 cm 2 / Vs or more is formed. Mobility was confirmed. The channel mobility of a similar conventional silicon carbide semiconductor device is 10 cm 2 / Vs or less, and it was confirmed that the present invention can realize a silicon carbide semiconductor device that can be used practically. MOS formed in the first embodiment
When the channel resistance and drift resistance of the FET were estimated to be on, the values were in the order of approximately the same, and it was confirmed that a low-loss power element was formed. The interface state density is 1.5 x 1 using the conventional insulating film / silicon carbide interface.
When it was as large as 0 12 cm -2 or more, the channel resistance was larger than the drift resistance by one digit or more, which was not practical.

【0034】さらに、2原子層以上の高さを有するステ
ップを含む炭化珪素基板と、上記炭化珪素基板表面に形
成された酸化膜を含む半導体素子においては、酸化膜と
炭化珪素の界面準位密度Nitが1.5×1012cm-2
以下であると、酸化絶縁膜の絶縁耐圧が10MVcm-1以上と
なることも確認した。従来の2原子層以上の高さを有す
るステップを含む炭化珪素基板と上記炭化珪素基板表面
に形成された界面準位密度の大きな酸化膜を含む炭化珪
素半導体素子においては、絶縁耐圧が1MVcm-1以下であ
り、本発明の半導体素子においてはじめて、実用に耐え
る十分な絶縁耐圧が達成された。
Further, in a semiconductor device including a silicon carbide substrate including a step having a height of two atomic layers or more and an oxide film formed on the surface of the silicon carbide substrate, the interface state density between the oxide film and silicon carbide is Nit is 1.5 × 10 12 cm -2
It was also confirmed that the dielectric strength of the oxide insulating film was 10 MVcm -1 or more when it was below. In a conventional silicon carbide semiconductor device including a silicon carbide substrate including a step having a height of two atomic layers or more and an oxide film having a large interface state density formed on the surface of the silicon carbide substrate, a withstand voltage is 1 MVcm −1. This is the following, and for the first time in the semiconductor device of the present invention, sufficient withstand voltage that can be practically used was achieved.

【0035】本発明の炭化珪素半導体素子は、炭化珪素
が有する物性の、ワイドギャップ性・高絶縁耐圧・十分
な移動度・高い熱伝導性を生かして、低損失の高温でも
動作する省エネルギーに寄与する半導体素子を提供す
る。
The silicon carbide semiconductor device of the present invention contributes to energy saving by operating at high temperature with low loss, by utilizing the physical properties of silicon carbide such as wide gap property, high dielectric strength, sufficient mobility and high thermal conductivity. Provided is a semiconductor device.

【0036】実施例1においては、SiC(0001)の8度オ
フカット面を基板として用い、その表面に形成された炭
化珪素半導体素子について述べたが、2原子層以上の高
さを有するステップを含む炭化珪素基板が、他のβ-SiC
(111)、6H,4H等のα-SiC(0001)、15R-SiCのSi面、β-Si
C(100)、β-SiC(110)、6H,4H等のα-SiC(1-100)及び/
又はα-SiC(11-20)の内から選ばれる結晶面の1度以上
のオフカット面を表面とする炭化珪素基板であっても本
発明は有効であることを確認した。
In Example 1, the 8 ° off-cut surface of SiC (0001) was used as the substrate, and the silicon carbide semiconductor element formed on the surface was described. However, a step having a height of 2 atomic layers or more was used. Silicon carbide substrate containing other β-SiC
Α-SiC (0001) such as (111), 6H, 4H, Si surface of 15R-SiC, β-Si
C (100), β-SiC (110), α-SiC (1-100) such as 6H, 4H and /
Alternatively, it was confirmed that the present invention is effective even for a silicon carbide substrate having an off-cut surface of one or more crystal faces selected from α-SiC (11-20) as a surface.

【0037】(実施例2)実施例2として本発明の炭化
珪素半導体素子の絶縁膜の製造方法の実施例を図1(b)
を用いて説明する。金属-酸化膜-半導体(MOS)試料を作
製するために用いた単結晶ウエファは、市販のn型の4周
期六方晶炭化珪素(4H-SiC)である。この単結晶ウエファ
は、直径2インチで(0001)面に対して8°のoff角を持って
おり、結晶表面には不純物濃度5×1015cm-3のエピタキシ
ャル膜が成長させてある。この単結晶を、5mm×5mm角に切
断してMOS試料作製用の基板とした。試料作製前、基板の
表面を有機洗浄した直後に1100℃の酸素中に水素を吹き
込んで生成した高温水蒸気で酸化を行い(水素燃焼酸
化)、その単結晶表面を犠牲酸化した。その酸化膜を3%の
薄いフッ酸を用いて溶融させて洗浄表面を露出させた。
この洗浄表面を有する炭化珪素4H-SiC基板のシリコン面
に対して、1100℃で1時間の水素燃焼酸化を行い、25nmの
厚さのゲ-ト酸化膜を形成した。
(Embodiment 2) As an embodiment 2, an embodiment of a method for manufacturing an insulating film of a silicon carbide semiconductor device of the present invention is shown in FIG.
Will be explained. The single crystal wafer used to prepare the metal-oxide-semiconductor (MOS) sample is commercially available n-type 4-period hexagonal silicon carbide (4H-SiC). This single crystal wafer has a diameter of 2 inches and an off angle of 8 ° with respect to the (0001) plane, and an epitaxial film having an impurity concentration of 5 × 10 15 cm −3 is grown on the crystal surface. This single crystal was cut into a 5 mm × 5 mm square and used as a substrate for preparing a MOS sample. Before sample preparation, immediately after the surface of the substrate was organically cleaned, hydrogen was blown into oxygen at 1100 ° C to oxidize it with high-temperature steam generated (hydrogen combustion oxidation) to sacrifice the surface of the single crystal. The oxide film was melted with 3% thin hydrofluoric acid to expose the cleaned surface.
The silicon surface of the silicon carbide 4H-SiC substrate having this cleaned surface was subjected to hydrogen combustion oxidation at 1100 ° C for 1 hour to form a gate oxide film having a thickness of 25 nm.

【0038】続いて、酸化温度を950℃まで低下させて3
時間水素燃焼酸化雰囲気(酸素と水蒸気を含むウエット
酸素雰囲気)での一回目アニール処理を行った。 引き続
いて温度を800℃まで低下させて、さらに3時間の水素燃
焼酸化雰囲気(酸素と水蒸気を含むウエット酸素雰囲気)
での2回目のアニール処理を行った。多段アニール処理終
了後、試料を反応管から引き出し、試料温度を室温まで急
速冷却してSiO2/6H-SiC界面付近の化学反応を中断させ
た。ゲ-ト酸化膜を作製直後、アルミニウム(Al)を蒸着し
て直径0.5mmの電極を持つMOS構造を形成した。また、オ-
ミック電極は、裏面表層に成長した酸化膜を除去してか
ら、その露出した4H-SiC基板表面上にAlを蒸着して作製
した。
Then, the oxidation temperature is lowered to 950 ° C.
The first annealing treatment was performed in a hydrogen combustion oxidizing atmosphere (wet oxygen atmosphere containing oxygen and water vapor) for a time. Then, lower the temperature to 800 ° C and continue for 3 hours in a hydrogen combustion oxidizing atmosphere (wet oxygen atmosphere containing oxygen and water vapor).
The second annealing treatment was performed. After completion of the multi-stage annealing treatment, the sample was pulled out from the reaction tube, and the sample temperature was rapidly cooled to room temperature to interrupt the chemical reaction near the SiO 2 / 6H-SiC interface. Immediately after forming the gate oxide film, aluminum (Al) was vapor-deposited to form a MOS structure having an electrode with a diameter of 0.5 mm. Also,
The Mick electrode was prepared by removing the oxide film grown on the back surface and then depositing Al on the exposed surface of the 4H-SiC substrate.

【0039】4H-SiCMOS構造の容量-重量(C-V)特性は、低
周波容量測定/高周波容量測定・同時測定装置(パッケ-
ジ82;ケスレ-社製)を用いて、室温、暗状態で測定した。こ
のC-V特性の取得においては、反転領域から蓄積領域へ電
圧を掃引(順方向掃引)と蓄積領域から反転領域へと測定
電圧を掃引する(逆方向掃引)を行った。順方向掃引にお
いては、掃引開始前に紫外線を試料ゲ-ト電極表面に照射
し、反転層を形成させた。反転層が形成された後、紫外線
照射を止めてから室温、暗状態にて測定を行っている。一
方、逆方向掃引を行うときは、紫外線照射は行っていな
い。
The capacitance-weight (CV) characteristic of the 4H-SiCMOS structure is measured by a low frequency capacitance measurement / high frequency capacitance measurement / simultaneous measurement device (package
The measurement was performed at room temperature in the dark. In acquiring this CV characteristic, a voltage was swept from the inversion region to the accumulation region (forward sweep) and a measurement voltage was swept from the accumulation region to the inversion region (reverse sweep). In the forward sweep, the sample gate electrode surface was irradiated with ultraviolet rays before the sweep was started to form an inversion layer. After the inversion layer is formed, the ultraviolet irradiation is stopped, and then the measurement is performed at room temperature and in a dark state. On the other hand, when performing the backward sweep, ultraviolet irradiation is not performed.

【0040】図3(a)に、ゲート酸化膜作製後に本発明の
炭化珪素半導体素子の絶縁膜の形成方法のアニール処理
の実施例である950℃3時間と800℃3時間の水蒸気アニー
ル処理を続けて行ったときのC-V特性、図3(b)に、従来の
炭化珪素半導体素子の絶縁膜の形成方法のアニール処理
である950℃3時間の水蒸気アニ-ル処理しか行わなかっ
たときのC-V特性を示す。
FIG. 3A shows a steam annealing treatment at 950 ° C. for 3 hours and 800 ° C. for 3 hours, which is an example of the annealing treatment in the method for forming the insulating film of the silicon carbide semiconductor element of the present invention after the gate oxide film is formed. CV characteristics when continuously performed, and FIG. 3 (b) shows CV when only the steam annealing treatment at 950 ° C. for 3 hours, which is the annealing treatment of the conventional method for forming the insulating film of the silicon carbide semiconductor element, is performed. Show the characteristics.

【0041】図3(a)では、高周波C-V曲線が−13Vから+
10Vまで掃引されている。掃引電圧が減少して行くと、容
量が一旦減少(少数キャリアの再分布)する。その後電圧0
V近辺から容量の増大がはじまるが、すぐに容量の増大が
抑止され、折れ曲がっている(キャパシタンスレッジ)の
が解る。また、準静状態C-V曲線では、 キャパシタンスレ
ッジが現れる0Vの電圧領域で、楔形の大きな容量の減少
を引き起こしているのが解る。これらの事実は、SiO2/4H-
SiC界面の界面準位が少ないことを示している。
In FIG. 3 (a), the high frequency CV curve changes from -13V to +
It is swept up to 10V. As the sweep voltage decreases, the capacity temporarily decreases (redistribution of minority carriers). Then voltage 0
The capacitance starts to increase from around V, but immediately it is understood that the capacitance is suppressed and bent (capacitance ledge). Also, in the quasi-static CV curve, it can be seen that a large wedge-shaped capacitance decrease is caused in the 0 V voltage region where the capacitance ledge appears. These facts mean that SiO 2 / 4H-
This indicates that the interface state of the SiC interface is small.

【0042】これに対して、図3(b)の950℃3時間の水蒸
気アニール処理しか行わなかった試料では、高周波C-V特
性における、少数キャリアの再分布やキャパシタンスレ
ッジが明確ではない。また、準静状態C-V曲線の容量減少
も明確ではなく、界面準位量が多いことを示している。
On the other hand, in the sample subjected to only the steam annealing treatment at 950 ° C. for 3 hours in FIG. 3B, the redistribution of minority carriers and the capacitance ledge in the high frequency CV characteristic are not clear. In addition, the capacity decrease of the quasi-static CV curve is not clear, indicating that the interface state quantity is large.

【0043】図3(a)と(b)の比較において明らかなよう
に、本発明の炭化珪素半導体素子の絶縁膜の形成方法で
ある多段水蒸気アニール処理には界面準位減少の効果の
あることが解る。この結果は、(0001)面に対して
再酸化効果がある950℃で3時間の酸化雰囲気アニー
ル処理につづいて、(11−20)面に対して再酸化効
果がある800℃で3時間の酸化雰囲気アニール処理を
行った結果である。その結果、低周波CV特性の形状が楔
形に変化しており、従来の炭化珪素半導体素子の絶縁膜
の形成方法である単一温度のアニール処理よりも界面準
位量の低下が計られいることが判る。
As is clear from the comparison between FIGS. 3 (a) and 3 (b), the multistage steam annealing treatment, which is the method of forming the insulating film of the silicon carbide semiconductor device of the present invention, has the effect of reducing the interface state. Understand. This result shows that the oxidization atmosphere annealing treatment at 950 ° C. for 3 hours, which has a reoxidation effect on the (0001) plane, is followed by 800 ° C. for 3 hours, which has a reoxidation effect on the (11-20) plane. This is the result of performing the annealing treatment in the oxidizing atmosphere. As a result, the shape of the low-frequency CV characteristics has changed to a wedge shape, and the interface state amount has been reduced compared to the single-temperature annealing treatment that is the conventional method of forming an insulating film of a silicon carbide semiconductor device. I understand.

【0044】本発明の炭化珪素半導体素子の絶縁膜の形
成方法の実施例の界面準位密度Nitは、Nit=1.09×1012c
m-2であり、従来の実施例の界面準位密度Nit=5.15×10
12cm -2に比べて非常に小さくなっており、本発明の絶縁
膜の形成方法の有効性が確認された。
Shape of Insulating Film of Silicon Carbide Semiconductor Element of the Present Invention
The interface state density Nit in the example of the forming method is Nit = 1.09 × 10.12c
m-2And the interface state density Nit = 5.15 × 10 in the conventional example.
12cm -2Is much smaller than that of the insulation of the present invention.
The effectiveness of the film forming method was confirmed.

【0045】実施例2においては、4H-SiC(0001)の8度
オフカット面を基板として用い、その表面に形成する炭
化珪素半導体素子の絶縁膜の製造方法について述べた
が、2原子層以上の高さを有するステップを含む炭化珪
素基板が、他のβ-SiC(111)、6H,4H等のα-SiC(0001)、
15R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等の
α-SiC(1-100)及び/又はα-SiC(11-20)の内から選ばれ
る結晶面の1度以上のオフカット面を表面とする炭化珪
素基板であっても本発明は有効であることを確認した。
In the second embodiment, the method of manufacturing the insulating film of the silicon carbide semiconductor device formed on the surface of the 8H off-cut surface of 4H-SiC (0001) is described. Silicon carbide substrate including a step having a height of other β-SiC (111), 6H, 4H α-SiC (0001),
15R-SiC Si face, β-SiC (100), β-SiC (110), α-SiC (1-100) such as 6H, 4H and / or α-SiC (11-20) It has been confirmed that the present invention is effective even for a silicon carbide substrate whose surface is an off-cut surface of one or more crystal planes.

【0046】本実施例2においては、アニール処理が2
回の場合を述べたが、更に多くのn回の設定温度の変更
を含むn回のアニール処理を施した場合であっても、本
発明の2原子層以上の高さを有するステップを含む炭化
珪素基板と、上記炭化珪素基板表面に形成された酸化膜
を含む炭化珪素半導体素子を、酸素を含む雰囲気下で複
数の設定温度に保ってアニール処理を施す炭化珪素半導
体素子の絶縁膜の形成方法であって、1回目のアニール
処理に続いて、上記1回目のアニール処理設定温度より
も低い設定温度で2回目のアニール処理を施し、少なく
とも2つ以上の異なる設定温度で保たれた酸素を含む雰
囲気下でのn回(n≧2)のアニール処理を含めば、有効で
あることを確認した。
In the second embodiment, the annealing treatment is 2 times.
Although the case of the number of times of annealing has been described, the carbonization including the step having a height of two atomic layers or more according to the present invention is performed even when the annealing is performed n times including changing the set temperature more times. Method for forming insulating film of silicon carbide semiconductor element, in which silicon carbide semiconductor element including silicon substrate and oxide film formed on the surface of silicon carbide substrate is annealed at a plurality of set temperatures in an atmosphere containing oxygen That is, following the first annealing treatment, the second annealing treatment is performed at a setting temperature lower than the first annealing treatment setting temperature, and oxygen containing at least two or more different setting temperatures is included. It was confirmed that it is effective if the annealing treatment of n times (n ≧ 2) in the atmosphere is included.

【0047】本実施例2においては、1回目のアニール
処理の設定温度が950℃、2回目のアニール処理の設
定温度が800℃の場合を述べたが、本発明の炭化珪素
半導体素子の絶縁膜の形成方法であって、1回目の酸素
を含む雰囲気下でのアニール処理が900℃以上であ
り、設定温度が850℃以下であるn回目のアニール処
理を少なくとも含めば、有効であることも確認した。
In the second embodiment, the case where the set temperature of the first annealing process is 950 ° C. and the set temperature of the second annealing process is 800 ° C. is described. However, the insulating film of the silicon carbide semiconductor device of the present invention is described. It is also confirmed that it is effective if the first annealing treatment in an atmosphere containing oxygen is 900 ° C. or higher and at least the nth annealing treatment whose set temperature is 850 ° C. or lower is included. did.

【0048】本実施例2においては、アニール処理をウ
ェット酸素雰囲気の一種である水素燃焼酸化雰囲気で行
った場合を述べたが、本発明の炭化珪素半導体素子の絶
縁膜の形成方法であって、少なくともn回目の酸素を含
む雰囲気下でのアニール処理が水蒸気と酸素を少なくと
も含むウェット酸素雰囲気で行われると有効であること
を確認した。
In the second embodiment, the case where the annealing treatment is performed in the hydrogen burning oxidation atmosphere which is a kind of the wet oxygen atmosphere has been described, but it is the method of forming the insulating film of the silicon carbide semiconductor element of the present invention. It was confirmed that at least the n-th annealing treatment in an atmosphere containing oxygen was effective when performed in a wet oxygen atmosphere containing at least water vapor and oxygen.

【0049】[0049]

【発明の効果】以上説明した通り、本発明の炭化珪素半
導体素子によれば、高パワーを制御する低損失・高耐圧
の制御素子を実現でき、例えば、エアコンなどを制御す
る高性能インバータ等に用いられる、実用に耐える省エ
ネパワー素子を提供する。
As described above, according to the silicon carbide semiconductor device of the present invention, it is possible to realize a control device having a low loss and a high breakdown voltage for controlling a high power, for example, a high performance inverter for controlling an air conditioner or the like. Provide an energy-saving power element that can be used for practical use.

【0050】また、本発明の炭化珪素半導体素子の絶縁
膜の形成方法によれば、低損失パワー素子のゲート絶縁
膜として応用可能な、高い絶縁耐圧・低い固定電荷密度
・低い界面準位密度を有する、炭化珪素半導体素子の絶
縁膜が得られ、耐圧が高く電流容量も大きい大電力用に
適した高速な低損失半導体素子を形成可能とするもので
ある。
Further, according to the method for forming an insulating film of a silicon carbide semiconductor element of the present invention, a high withstand voltage, a low fixed charge density, and a low interface state density applicable to a gate insulating film of a low loss power element can be obtained. It is possible to obtain an insulating film of a silicon carbide semiconductor device, and to form a high-speed low-loss semiconductor device suitable for large power having a high breakdown voltage and a large current capacity.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)本発明の炭化珪素半導体素子の絶縁膜/炭化
珪素界面の拡大図である。 (b)本発明の炭化珪素半導体素子の絶縁膜の形成方法を
示す図である。
FIG. 1 (a) is an enlarged view of an insulating film / silicon carbide interface of a silicon carbide semiconductor device of the present invention. (b) It is a figure which shows the formation method of the insulating film of the silicon carbide semiconductor element of this invention.

【図2】絶縁ゲート型半導体素子の構造を示す図であ
る。
FIG. 2 is a diagram showing a structure of an insulated gate semiconductor device.

【図3】(a)本発明の炭化珪素半導体素子及びその絶縁
膜の形成方法による酸化絶縁膜/炭化珪素界面のC-V特性
を示す図である。 (b)従来例の絶縁膜の形成方法による酸化絶縁膜/炭化珪
素界面 のC-V特性を示す図である。
FIG. 3 (a) is a diagram showing CV characteristics of an oxide insulating film / silicon carbide interface by the method for forming a silicon carbide semiconductor device and an insulating film thereof according to the present invention. (b) is a diagram showing CV characteristics of an oxide insulating film / silicon carbide interface by an insulating film forming method of a conventional example.

【符号の説明】[Explanation of symbols]

1 基板 2 ステップ 3 絶縁膜/炭化珪素基板界面 4 酸化絶縁膜 5 (0001)テラス面 6 (11-20)面 7 酸化設定温度 8 1回目のアニール設定温度 9 2回目のアニール設定温度 21 絶縁ゲート型半導体素子 22 n型基板 23 n型エピタキシャル成長層(n型層) 24 p型の部分(p型層) 25 n+型層 26 酸化絶縁膜 27a ゲート電極 27b ソース電極のオーミック接合の部分 27c ドレイン電極 27d ソース電極のショットキー接合の部分 28 チャンネル領域 1 substrate Two steps 3 Insulating film / silicon carbide substrate interface 4 Oxide insulation film 5 (0001) Terrace surface 6 (11-20) side 7 Oxidation set temperature 8 1st annealing set temperature 9 Second annealing set temperature 21 Insulated gate type semiconductor device 22 n type substrate 23 n-type epitaxial growth layer (n-type layer) 24 p-type part (p-type layer) 25 n + type layer 26 Oxide insulation film 27a Gate electrode 27b Source electrode ohmic junction 27c drain electrode 27d Schottky junction of source electrode 28 channel area

───────────────────────────────────────────────────── フロントページの続き (72)発明者 伊藤 久義 群馬県高崎市綿貫町1233番地 日本原子力 研究所高崎研究所内 (72)発明者 北畠 真 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 山下 賢哉 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 楠本 修 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 内田 正雄 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 高橋 邦方 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 宮永 良子 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5F058 BA20 BC02 BF56 BF63 BH03 BH20 BJ01    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hisayoshi Ito             1233 Watanuki-cho, Takasaki-shi, Gunma Japan Nuclear Power             Research Institute Takasaki Research Center (72) Inventor Makoto Kitahata             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Kenya Yamashita             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Osamu Kusumoto             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Masao Uchida             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Kunikata Takahashi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Ryoko Miyanaga             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5F058 BA20 BC02 BF56 BF63 BH03                       BH20 BJ01

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 表面に2原子層以上の高さを有するステ
ップを含む炭化珪素基板と、上記炭化珪素基板表面に形
成された酸化膜を含み、酸化膜と炭化珪素の界面準位密
度Nitが1.5×1012cm-2以下であることを特徴
とする、炭化珪素半導体素子。
1. A silicon carbide substrate including a step having a height of two atomic layers or more on a surface thereof, and an oxide film formed on the surface of the silicon carbide substrate, wherein an interface state density Nit of the oxide film and the silicon carbide is A silicon carbide semiconductor device having a size of 1.5 × 10 12 cm −2 or less.
【請求項2】 請求項1記載の炭化珪素半導体素子であ
って、2原子層以上の高さを有するステップを含む炭化
珪素基板が、β-SiC(111)、6H,4H等のα-SiC(0001)、15
R-SiCのSi面、β-SiC(100)、β-SiC(110)、6H,4H等のα
-SiC(1-100)及び/又はα-SiC(11-20)の内から選ばれる
結晶面の1度以上のオフカット面を表面とする炭化珪素
基板であることを特徴とする、炭化珪素半導体素子。
2. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide substrate including a step having a height of two atomic layers or more is α-SiC such as β-SiC (111), 6H, 4H. (0001), 15
Si surface of R-SiC, β-SiC (100), β-SiC (110), α of 6H, 4H, etc.
-SiC (1-100) and / or α-SiC (11-20), which is a silicon carbide substrate having an off-cut surface of one or more crystal planes selected from the surface thereof as a surface. Semiconductor device.
【請求項3】 表面に2原子層以上の高さを有するステ
ップを含む炭化珪素基板と、上記炭化珪素基板表面に形
成された酸化膜を含む炭化珪素半導体素子を、酸素を含
む雰囲気下で複数の設定温度に保ってアニール処理を施
す炭化珪素半導体素子の絶縁膜の形成方法であって、1
回目のアニール処理に続いて、上記1回目のアニール処
理設定温度よりも低い設定温度で2回目のアニール処理
を施し、少なくとも2つ以上の異なる設定温度で保たれ
た酸素を含む雰囲気下でのn回(n≧2)のアニール処理を
含むことを特徴とする、炭化珪素半導体素子の絶縁膜の
形成方法。
3. A plurality of silicon carbide substrates including a step having a height of two atomic layers or more on the surface and a silicon carbide semiconductor element including an oxide film formed on the surface of the silicon carbide substrate in an atmosphere containing oxygen. A method of forming an insulating film of a silicon carbide semiconductor element, which comprises performing annealing treatment while maintaining the set temperature of
Subsequent to the first annealing treatment, the second annealing treatment is performed at a setting temperature lower than the first annealing treatment setting temperature, and n in an atmosphere containing oxygen kept at at least two different setting temperatures is used. A method for forming an insulating film of a silicon carbide semiconductor element, characterized in that the method includes a step (n ≧ 2) of annealing treatments.
【請求項4】 請求項3記載の炭化珪素半導体素子の絶
縁膜の形成方法であって、1回目の酸素を含む雰囲気下
でのアニール処理が900℃以上であり、設定温度が8
50℃以下であるn回目のアニール処理を少なくとも含
むことを特徴とする炭化珪素半導体素子の絶縁膜の形成
方法。
4. The method for forming an insulating film of a silicon carbide semiconductor device according to claim 3, wherein the first annealing treatment in an atmosphere containing oxygen is 900 ° C. or higher, and the set temperature is 8.
A method for forming an insulating film of a silicon carbide semiconductor device, comprising at least an n-th annealing treatment at 50 ° C. or lower.
【請求項5】 請求項3記載の炭化珪素半導体素子の絶
縁膜の形成方法であって、少なくともn回目の酸素を含
む雰囲気下でのアニール処理がウェット酸素雰囲気であ
ることを特徴とする炭化珪素半導体素子の絶縁膜の形成
方法。
5. The method for forming an insulating film of a silicon carbide semiconductor device according to claim 3, wherein the annealing treatment in an atmosphere containing oxygen at least n times is a wet oxygen atmosphere. Method for forming insulating film of semiconductor element.
JP2002003834A 2002-01-10 2002-01-10 Silicon carbide semiconductor element and method for forming insulating film thereof Expired - Lifetime JP3697211B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002003834A JP3697211B2 (en) 2002-01-10 2002-01-10 Silicon carbide semiconductor element and method for forming insulating film thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002003834A JP3697211B2 (en) 2002-01-10 2002-01-10 Silicon carbide semiconductor element and method for forming insulating film thereof

Publications (2)

Publication Number Publication Date
JP2003209251A true JP2003209251A (en) 2003-07-25
JP3697211B2 JP3697211B2 (en) 2005-09-21

Family

ID=27643321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002003834A Expired - Lifetime JP3697211B2 (en) 2002-01-10 2002-01-10 Silicon carbide semiconductor element and method for forming insulating film thereof

Country Status (1)

Country Link
JP (1) JP3697211B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005053034A1 (en) * 2003-11-25 2005-06-09 Matsushita Electric Industrial Co., Ltd. Semiconductor element
JP2005310886A (en) * 2004-04-19 2005-11-04 Denso Corp Silicon carbide semiconductor device and its manufacturing method
JP2011091186A (en) * 2009-10-22 2011-05-06 Mitsubishi Electric Corp Method of fabricating silicon carbide semiconductor device
JP2012049491A (en) * 2010-07-26 2012-03-08 Sumitomo Electric Ind Ltd Semiconductor device
CN113035709A (en) * 2021-03-01 2021-06-25 同辉电子科技股份有限公司 Method for improving interface characteristics of SiC device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005053034A1 (en) * 2003-11-25 2005-06-09 Matsushita Electric Industrial Co., Ltd. Semiconductor element
US7214984B2 (en) 2003-11-25 2007-05-08 Matsushita Electric Industrial Co., Ltd. High-breakdown-voltage insulated gate semiconductor device
US7381993B2 (en) 2003-11-25 2008-06-03 Matsushita Electric Industrial Co., Ltd. High-breakdown-voltage insulated gate semiconductor device
JP2005310886A (en) * 2004-04-19 2005-11-04 Denso Corp Silicon carbide semiconductor device and its manufacturing method
JP4635470B2 (en) * 2004-04-19 2011-02-23 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP2011091186A (en) * 2009-10-22 2011-05-06 Mitsubishi Electric Corp Method of fabricating silicon carbide semiconductor device
JP2012049491A (en) * 2010-07-26 2012-03-08 Sumitomo Electric Ind Ltd Semiconductor device
CN113035709A (en) * 2021-03-01 2021-06-25 同辉电子科技股份有限公司 Method for improving interface characteristics of SiC device
CN113035709B (en) * 2021-03-01 2022-11-08 同辉电子科技股份有限公司 Method for improving interface characteristics of SiC device

Also Published As

Publication number Publication date
JP3697211B2 (en) 2005-09-21

Similar Documents

Publication Publication Date Title
JP5603008B2 (en) Method for forming SiCMOSFET having large inversion layer mobility
JP4843854B2 (en) MOS device
TWI404131B (en) Methods of fabricating silicon carbide devices having smooth channels
JP5306193B2 (en) Silicon carbide switching device including p-type channel and method of forming the same
TWI330894B (en) Vertical jfet limited silicon carbide power metal-oxide semiconductor field effect transistors and methods of fabricating vertical jfet limited silicon carbide metal-oxide semiconductor field effect transistors
EP2740148B1 (en) Forming sic mosfets with high channel mobility by treating the oxide interface with cesium ions
JP2007115875A (en) Silicon carbide semiconductor device and manufacturing method thereof
JP4188637B2 (en) Semiconductor device
JP2005166930A (en) Sic-misfet and its manufacturing method
EP3756225B1 (en) A vertical silicon carbide power mosfet and igbt and a method of manufacturing the same
TW201108388A (en) Insulated gate field effect transistor
JP4957005B2 (en) Method for manufacturing silicon carbide semiconductor element
JPH09321323A (en) Silicon carbide substrate, manufacture thereof and silicon carbide semiconductor device using the same substrate
JP3697211B2 (en) Silicon carbide semiconductor element and method for forming insulating film thereof
JP2003517204A (en) Method for obtaining higher inversion layer mobility in silicon carbide semiconductor device
EP4016644A1 (en) Power semiconductor device and method for manufacturing a power semiconductor device
EP1908118B1 (en) Method for producing a semiconductor device
Chowdhury et al. Effect of carrier lifetime enhancement on the performance of ultra-high voltage 4H-SiC PiN diodes
KR20230076967A (en) Manufacturing method of semiconductor with reduced surface roughness using functionalized graphene nanosheets

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040219

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040224

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040406

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050603

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050701

R150 Certificate of patent or registration of utility model

Ref document number: 3697211

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090708

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090708

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100708

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100708

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110708

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110708

Year of fee payment: 6

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110708

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120708

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120708

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130708

Year of fee payment: 8

EXPY Cancellation because of completion of term