JP3674986B2 - Manufacturing method of semiconductor device - Google Patents

Description

以上により、ゲートパターニングされ、かつＬＤＤ領域１４ａ，１４ｂが形成された図５の構造が得られる。
【００６０】
（ｅ）ＬＤＤサイドウォール形成用に、ＬＰ−ＴＥＯＳ酸化膜形成を、次の条件で再度行う。
条件
ガス ＴＥＯＳ＝３００ｓｃｃｍ
圧力 ９３Ｐａ
温度 ７００℃
膜厚 ２５０ｎｍ
全面エッチバックを行い、サイドウォール１６ａ，１６ｂを形成し、次の条件でのソース／ドレインイオン注入、及び１０００℃１０秒の活性化熱処理を行う。

以上により、ソース／ドレイン１３ａ，１３ｂが形成された図６の構造とする。
【００６１】
（ｆ）全面に下記条件でＴｉを形成した後、２ステップ熱処理でソース／ドレイン１３ａ，１３ｂ上にＴｉサリサイドを形成する。
Ｔｉ形成条件
パワー １ｋＷ
成膜温度 １５０℃
ガス Ａｒ＝１００ｓｃｃｍ
膜厚 ３０ｎｍ
圧力 ０．４７Ｐａ
２ステップ熱処理は、まず６００℃の熱処理を加え、ＴｉＳｉ₂ を形成する。更に、アンモニア−過酸化水素水混合液に浸すことで未反応のＴｉを選択的に除去する。更に８００℃の熱処理で安定したＴｉＳｉ₂ を形成させる。これによりシリサイド層１０ａ，１０ｂを形成してサリサイド構造として図７の構造を得る。
【００６２】
（ｇ）ＳｉＯ₂ 層間膜の成膜を下記のようにして行う。
条件
ガス ＴＥＯＳ＝５０ｓｃｃｍ
温度 ７２０℃
圧力 ４０Ｐａ
膜厚 ６００ｎｍ
レジストパターニングを行い、下記条件のドライエッチングによって接続孔２０を形成する。
ドライエッチング条件
ガス Ｃ₄ Ｆ₈ ＝５０ｓｃｃｍ
ＲＦパワー １２００Ｗ
圧力 ２Ｐａ
以上により、層間膜１８に接続孔２０（コンタクトホール）が形成された図８の構造を得る。
【００６３】
（ｈ）配線材料を形成させる。即ちここでは、接続孔２０内の埋め込みはブランケットＷを埋め込み材２１として形成する。
埋め込みに先立ち、Ｗ用密着層としてＴｉＮ／Ｔｉを形成させる。まず、次の条件でＴｉを形成する。
Ｔｉ形成条件
パワー ８ｋＷ
成膜温度 １５０℃
ガス Ａｒ＝１００ｓｃｃｍ
膜厚 １０ｎｍ
圧力 ０．４７Ｐａ
更に、次の条件でＴｉＮを形成させる。
ＴｉＮ形成条件
パワー ５ｋＷ
ガス Ａｒ／Ｎ₂ ＝４０／２０ｓｃｃｍ
圧力 ０．４７Ｐａ
膜厚 ７０ｎｍ
次いで、下記条件でブランケットＷを形成する。
Ｗ形成条件
ガス Ａｒ／Ｎ₂ ／Ｈ₂ ／ＷＦ₆ ＝２２００／３００／５００／７５ｓｃｃｍ
温度 ４５０℃
圧力 １０６４０Ｐａ
膜厚 ４００ｎｍ
Ｗを下記条件でエッチバックして、接続孔２０内にのみＷを残す。
エッチバック条件
ガス ＳＦ₆ ＝５０ｓｃｃｍ
ＲＦパワー １５０Ｗ
圧力 １．３３Ｐａ
以上により、接続孔２０が埋め込まれる。
【００６４】
次に、上層配線として、下記のようにしてＡｌ／Ｔｉの配線を形成させる。まず、Ｔｉを成膜する。
Ｔｉ成膜条件
パワー ４ｋＷ
成膜温度 １５０℃
ガス Ａｒ＝１００ｓｃｃｍ
膜厚 ３０ｎｍ
圧力 ０．４７Ｐａ
更に、Ａｌを下記条件で成膜する。（Ａｌとしては、Ａｌ−１ｗｔ％Ｓｉや、Ａｌ−Ｓｉ−ＣｕのようなＡｌ系合金材料でもよい。）
Ａｌ成膜条件
パワー ２２．５ｋＷ
成膜温度 １５０℃
ガス Ａｒ＝５０ｓｃｃｍ
膜厚 ０．５μｍ
圧力 ０．４７Ｐａ
その後、レジストパターニング及び下記条件のドライエッチングでパターニングを行って、Ａｌ／Ｔｉ配線層を形成させる。
条件
ガス ＢＣｌ₃ ／Ｃｌ₂ ＝６０／９０ｓｃｃｍ
マイクロ波パワー １０００Ｗ
ＲＦパワー ５０Ｗ
圧力 ０．０１６Ｐａ
【００６５】
本実施例では、次の具体的効果が得られる。
▲１▼トランジスタルールが縮小しても、薄膜Ｗポリサイドゲートを剥がれなく形成でき、高集積度、高周波数、低電圧、低消費電力のＬＳＩを安定して作ることができる。
▲２▼従来のプロセスの延長線上で実現できることより、ＬＳＩ作製コストは上昇しない。
▲３▼ＷＳｉ剥がれがＬＳＩ製造中に発生しないので、パーティクルが発生せず、ＬＳＩの製造歩留が向上する。
▲４▼狭いところも安定してＷポリサイド構造を形成できる。
【００６６】
実施例２
この実施例も、実施例１と同様のトランジスタについて本発明を適用したものであるが、ここでは熱処理工程に工夫を施した。即ちここでは、ＬＰ−ＴＥＯＳ／ＳｉＮ／ＷＳｉ構造を形成直後に、即ちパターニングは行わず、全面に被着している状態で水分等が完全に抜ける温度で、予め、熱処理を十分に行い、気相中に脱ガスを行う。これによりその後のプロセス中の熱処理で脱ガスを発生させないようにした。即ち本実施例のデバイス製造プロセスにおいては、半導体基板１上に第１の膜２と第２の膜３を積層して形成した成膜構造（図１１）を備え、第１の膜２は温度上昇により脱ガスしてガスを発生する膜であり、第２の膜３は該第１の膜から発生するガスと反応を生じない膜であり、該第２の膜を第１の膜の下地に形成させて半導体装置を製造する場合に、第２の膜３上に第１の膜２を形成させた後、図１１に示すように第１の膜２から十分に脱ガスを施せる熱処理を加える構成とする。ここではまた、下地にはＳｉＮを形成しているので、脱ガス中に、下地ＷＳｉと脱ガス成分の反応は発生しない。
【００６７】
本実施例では、以下の（ａ）〜（ｃ）の工程を行う（爾後の工程は実施例１と同じである）。図９ないし図１１を参照する。
（ａ）実施例１と同様にして素子分離領域１２としてＬＯＣＯＳ形成を行い、ゲート酸化を施してゲート絶縁膜１７を形成し、ゲート配線のためのＷＳｉ１５ｂ／ＰｏｌｙＳｉ１５ａを全面に成膜する。これにより図９の構造とする。
【００６８】
（ｂ）全面にＬＰ−ＳｉＮを下記条件で形成する。
形成条件
ガス ＳｉＨ₂ Ｃｌ₂ ／ＮＨ₃ ／Ｎ₂ ＝９０／６００／１０００ｓｃｃｍ
圧力 ５３Ｐａ
温度 ７００℃
膜厚 ５０ｎｍ
これにより第２の膜３とするＳｉＮ膜が形成される（図１０）。
【００６９】
（ｃ）全面にＬＰ−ＴＥＯＳによるＳｉＯ₂ を下記条件で形成する。
形成条件
ガス ＴＥＯＳ＝３００ｓｃｃｍ
圧力 ９３Ｐａ
温度 ７００℃
膜厚 ２００ｎｍ
これによりオフセット膜とする第１の膜２としてＴＥＯＳ−ＳｉＯ₂ が図１１のように形成された構造が得られる。
【００７０】
その後、窒素雰囲気中で、８００℃、３０分の熱処理を施す。これにより、脱ガスする第１の膜３であるＬＰ−ＴＥＯＳ中のガスが、この段階で放出される。脱ガスを模式図に矢印で示す。このとき、この放出されるガスは下地の第２の膜３（ＳｉＮ）とは反応しないので、剥離等の問題は生じない。
【００７１】
以下工程（ｄ）以降は、実施例１と同様である。予め上記のように第１の膜２（オフセット膜）からはガスが放出されているので、その後の工程で脱ガスが生じることはなく、よって脱ガスによる不都合も生じない。
【００７２】
実施例３
本実施例では、実施例１と同様の対象について、ＷＳｉ／ＰｏｌｙＳｉ成膜後、全面酸化を施すことで、ＷＳｉ表面に薄い熱酸化膜を形成させる。その上に、ＬＰ−ＴＥＯＳを形成する。ＷＳｉ表面の熱酸化膜が第１の膜２からのガスと反応しない第２の膜３ａとして機能して、ＬＰ−ＴＥＯＳ（第１の膜２）からの脱ガス成分との反応を防止する（ＷＳｉ酸化に関しては、“Ｏｘｉｄａｔｉｏｎｍｅｃｈａｎｉｓｍｓ ｉｎ ＷＳｉ₂ ｔｈｉｎ ｆｉｌｍｓ”，Ｓ．Ｚｉｒｉｎｓｋｙ，ｅｔ．ａｌ．，Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．３３（１），１Ｊｕｌｙ １９７８，７６頁参照）。
【００７３】
以下本実施例について詳述する。図１２ないし図１４を参照する。
（ａ）実施例１と同様にして素子分離領域１２としてＬＯＣＯＳ形成を行い、ゲート酸化を施してゲート絶縁膜１７を形成し、ゲート配線のためのＷＳｉ１５ｂ／ＰｏｌｙＳｉ１５ａを全面に成膜する（図１２）。
【００７４】
（ｂ）全面酸化を施す。例えば下記条件でＷＳｉ１５ｂの表面酸化を行うことができる。これにより第２の膜３ａとして熱酸化膜が形成された図１３の構造を得る。
酸化条件
ガス Ｈ₂ Ｏ／Ｏ₂ 混合ガス＝１．０リットル／ｍｉｎ．
温度 ９００℃
時間 １０分
膜厚 ５０ｎｍ
【００７５】
（ｃ）全面にＬＰ−ＴＥＯＳによるＳｉＯ₂ を下記条件で形成する。
形成条件
ガス ＴＥＯＳ＝３００ｓｃｃｍ
圧力 ９３Ｐａ
温度 ７００℃
膜厚 ２００ｎｍ
これによりオフセット膜とする第１の膜２としてＴＥＯＳ−ＳｉＯ₂ が図１４に示すように形成された構造が得られる。ここで、ＴＥＯＳ−ＳｉＯ₂ の成膜中、あるいは成膜後の各種熱処理工程などでこの膜２から脱ガスが発生しても、前記熱酸化膜３はこのガスと反応しないので、下地を保護する保護膜の役割を果たす。図１４中、矢印で脱ガスを模式的に示す。
【００７６】
以下実施例１の工程（ｄ）以降と同一の工程を行う。上記したように各種工程で脱ガスが生じても、熱酸化膜により悪影響は遮断される。
【００７７】
実施例４
本実施例は、実施例１と同様の対象について、オフセット絶縁膜として、Ｈ₂ Ｏ等の脱ガスの発生しない膜を用いる場合である。例えば、ＬＰ−ＳｉＮを用いる。即ち本実施例の半導体装置は、図１７に示すように、半導体基板上のゲート配線１５上にオフセット膜４を積層して形成した成膜構造を備え、該オフセット膜４は温度上昇によりガスを発生しない膜（脱ガスしない膜。ここではＳｉＮ）であるものである。
【００７８】
以下図１５ないし図１７を参照して、本実施例のデバイスプロセスを詳述する。
（ａ）実施例１と同様にして素子分離領域１２としてＬＯＣＯＳ形成を行い、ゲート酸化を施してゲート絶縁膜１７を形成し、ゲート配線のためのＷＳｉ１５ｂ／ＰｏｌｙＳｉ１５ａを全面に成膜する（図１５）。
【００７９】
（ｂ）全面にオフセット絶縁膜とするＬＰ−ＳｉＮを下記条件で形成する。これにより脱ガスしない膜４を上記ＷＳｉ１５ｂ／ＰｏｌｙＳｉ１５ａ上に形成する。以上で図１６の構造とする。
形成条件
ガス ＳｉＨ₂ Ｃｌ₂ ／ＮＨ₃ ／Ｎ₂ ＝９０／６００／１０００ｓｃｃｍ
圧力 ５３Ｐａ
温度 ７００℃
膜厚 ５０ｎｍ
【００８０】
（ｃ）ゲートパターニングを下記条件でドライエッチングにより行う。まずＳｉＮから成る脱ガスしない膜４（オフセット膜）を次のようにパターニングする。エッチング条件
ガス ＣＨＦ₃ ／Ｏ₂ ＝４５／５ｓｃｃｍ
ＲＦパワー １０００Ｗ
圧力 ２．７Ｐａ
次にゲート材（ＷＳｉ１５ｂ、ＰｏｌｙＳｉ１５ａ）のドライエッチングを下記条件で施す。これによりゲートパターニングを行う。
条件
ガス Ｃｌ₂ ／Ｏ₂ ＝７５／２ｓｃｃｍ
圧力 ０．４Ｐａ
マイクロ波パワー ７５０Ｗ
ＲＦバイアス ８０Ｗ
オーバーエッチング条件
ガス ＨＢｒ／Ｏ₂ ＝１２０／４ｓｃｃｍ
圧力 １．３Ｐａ
マイクロ波パワー ７５０Ｗ
ＲＦバイアス ３０Ｗ
【００８１】
更に、下記条件でＬＤＤイオン注入を施す（図１７）。ＬＤＤ領域を１４ａ，１４ｂで示す。

【００８２】
以下実施例１の工程（ｅ）以降と同様に工程を進める。本実施例ではガスを発生しない膜４であるＳｉＮを用いたので、脱ガスによる不都合は生じず、剥がれの問題も起きない。
【００８３】
実施例５
本実施例においては、予め、ゲート配線部のみをパターニングする。その後全面酸化を施す。更にＬＰ−ＴＥＯＳ酸化膜を形成させ、ゲートサイドウォール余裕も合わせてＬＰ−ＴＥＯＳ酸化膜をパターニングする。ゲートサイドウォールと、オフセット酸化膜を同時に形成する。同時形成とするので、その分、熱履歴は少なくてすむ。よって放出脱ガス成分は少ない。更に、ＷＳｉ表面部領域を熱酸化膜でカバーしているので、ＬＰ−ＴＥＯＳ酸化膜からの脱ガスとの反応は進行しない利点を有する。
【００８４】
以下に、具体的に説明する。図１８ないし図２２を参照する。
（ａ）実施例１と同様にして素子分離領域１２としてＬＯＣＯＳ形成を行い、ゲート酸化を施してゲート絶縁膜１７を形成し、ゲート配線のためのＷＳｉ１５ｂ／ＰｏｌｙＳｉ１５ａを全面に成膜する（図１８）。
【００８５】
（ｂ）ゲートパターニングを下記条件でドライエッチングにより行う。
条件
ガス Ｃｌ₂ ／Ｏ₂ ＝７５／２ｓｃｃｍ
圧力 ０．４Ｐａ
マイクロ波パワー ７５０Ｗ
ＲＦバイアス ８０Ｗ
オーバーエッチング条件
ガス ＨＢｒ／Ｏ₂ ＝１２０／４ｓｃｃｍ
圧力 １．３Ｐａ
マイクロ波パワー ７５０Ｗ
ＲＦバイアス ３０Ｗ
【００８６】
上記によりパターニングを行ってゲート構造１５を形成した後、更に、下記条件でＬＤＤイオン注入を施す（図１９）。ＬＤＤ領域を符号１４ａ，１４ｂで示す。

【００８７】
（ｃ）次に本実施例では下記条件で全面酸化を施す。これにより図２０に示すように、ゲート構造１５の上面と側面、及びＬＤＤ領域１４ａ，１４ｂ上を含む全面に酸化膜５が形成された構造を得る。
条件
ガス Ｈ₂ Ｏ／Ｏ₂ 混合ガス＝１．０リットル／ｍｉｎ．
温度 ９００℃
時間 １０分
膜厚 ５０ｎｍ
【００８８】
（ｄ）次に全面に、オフセット膜とする脱ガスの可能性のある第１の膜２としてＬＰ−ＴＥＯＳによるＳｉＯ₂ を下記条件で形成する。
形成条件
ガス ＴＥＯＳ＝３００ｓｃｃｍ
圧力 ９３Ｐａ
温度 ７００℃
膜厚 ３００ｎｍ
【００８９】
（ｅ）ゲートサイドウォール分も考慮して、下記ドライエッチング条件で、上記で成膜した第１の膜２（ＴＥＯＳ酸化膜）のパターニングを行う。
ドライエッチング条件
ガス ＣＨＦ₃ ／Ｏ₂ ＝４５／５ｓｃｃｍ
ＲＦパワー １０００Ｗ
圧力 ２．７Ｐａ
【００９０】
更に、下記条件でソース／ドレインイオン注入を行い、１０００℃１０秒の活性化熱処理を行って、ソース／ドレイン１３ａ，１３ｂを形成する（図２２）。

【００９１】
以下実施例１の工程（ｆ）以降と同様の工程を行う。本実施例では、第２の膜として機能する熱酸化膜５を介して、ゲート１５特にＷＳｉ１５ｂ上に第１の膜２（ＴＥＯＳ酸化膜）を形成したので、脱ガスの影響は遮断され、剥がれ等の問題は生じない。
【００９２】
実施例６（変形例）
上記各実施例は、上述した目的が達成されるのであるなら、他の手段を用いてもかまわない。特に上記各実施例では、ゲート材料としてＷポリサイドを有する構造に適用したが、その他のシリサイドを有する構造、例えば、Ｔｉシリサイド、Ｃｏシリサイド、Ｎｉシリサイド等の遷移金属シリサイドにも勿論適用でき、この実施例（変形例）では、これら各種のシリサイドを用いたゲート構造で実施して、同様の作用効果を得た。また、シリサイドと直接接している絶縁膜の材料として、上記各実施例ではＳｉＮや熱酸化膜を用いているが、このような材料以外の、熱処理で脱ガスが少ない材料も用いることができる。例えば、オキシナイトライド等の絶縁膜でも適応できる。この実施例（変形例）では、ＳｉＯｘＮｙを用いて実施して、良好な結果を得た。また、上記各実施例は半導体構造として、ＭＯＳＦＥＴを例にしたが、バイポーラトランジスタ、ＣＣＤ等のデバイス等の、上記問題が生じる可能性の有するデバイスにも本発明は汎用できるものであり、この実施例（変形例）では、これらのデバイスにも適して実施したが、やはり同様に良好な結果が得られた。
【００９３】
【発明の効果】
上記詳述したように、本発明の半導体装置の製造方法によれば、脱ガスに伴う膜剥がれ等各種のを解決することができ、この効果は温度上昇により脱ガスしてガスを発生する膜を用いる場合も発揮されるものである。
【図面の簡単な説明】
【図１】 実施例１の成膜構造及び半導体装置を示す断面図である。
【図２】 実施例１の工程を順に断面図で示すものである（１）。
【図３】 実施例１の工程を順に断面図で示すものである（２）。
【図４】 実施例１の工程を順に断面図で示すものである（３）。
【図５】 実施例１の工程を順に断面図で示すものである（４）。
【図６】 実施例１の工程を順に断面図で示すものである（５）。
【図７】 実施例１の工程を順に断面図で示すものである（６）。
【図８】 実施例１の工程を順に断面図で示すものである（７）。
【図９】 実施例２の工程を順に断面図で示すものである（１）。
【図１０】 実施例２の工程を順に断面図で示すものである（２）。
【図１１】 実施例２の工程を順に断面図で示すものである（３）。
【図１２】 実施例３の工程を順に断面図で示すものである（１）。
【図１３】 実施例３の工程を順に断面図で示すものである（２）。
【図１４】 実施例３の工程を順に断面図で示すものである（３）。
【図１５】 実施例４の工程を順に断面図で示すものである（１）。
【図１６】 実施例４の工程を順に断面図で示すものである（２）。
【図１７】 実施例４の工程を順に断面図で示すものであり（３）、実施例４の半導体装置の断面図である。
【図１８】 実施例５の工程を順に断面図で示すものである（１）。
【図１９】 実施例５の工程を順に断面図で示すものである（２）。
【図２０】 実施例５の工程を順に断面図で示すものである（３）。
【図２１】 実施例５の工程を順に断面図で示すものである（４）。
【図２２】 実施例５の工程を順に断面図で示すものである（５）。
【図２３】 従来例の工程を順に断面図で示すものである（１）。
【図２４】 従来例の工程を順に断面図で示すものである（２）。
【図２５】 従来例の工程を順に断面図で示すものである（３）。
【図２６】 従来例の工程を順に断面図で示すものである（４）。
【図２７】 従来例の工程を順に断面図で示すものである（５）。
【図２８】 図２６のＡ部拡大略示図で、従来技術の問題点を示す図である。
【符号の説明】
１ 半導体基板（Ｓｉ基板）
１２ 素子分離領域
１３ａ，１３ｂ ソース／ドレイン領域
１４ａ，１４ｂ ＬＤＤ領域
１５ ゲート配線
１５ａ ＰｏｌｙＳｉ（ゲート材）
１５ｂ ＷＳｉ（ゲート材）
１６ａ，１６ｂ ゲートサイドウォール
１７ ゲート酸化膜
１８ ＳｉＯ₂
２２ ＴｉＮ／Ｔｉ
２１ Ｗ
２３ Ａｌ−Ｓｉ
１０ａ，１０ｂ ＴｉＳｉ₂
２ 第１の膜（オフセット膜、ＬＰ−ＴＥＯＳ酸化膜）
３ 第２の膜（ガスと反応しない膜、ＬＰ−ＳｉＮ）
３ａ 第２の膜（ガスと反応しない膜、熱ＳｉＯ₂ ）
４ 脱ガスを生じない膜（熱酸化膜）
４ 脱ガスを生じない膜（ＬＰ−ＳｉＮ）
５ ガスと反応しない膜（熱酸化膜）[0001]
  The present inventionThe present invention relates to a method for manufacturing a semiconductor device. The present invention includes a film forming structure.It can be used for various semiconductor devices.
[0002]
[Prior art and its problems]
Miniaturization is progressing in the field of various electronic materials using the film formation structure, and in particular, in the field of semiconductor devices, for example, the miniaturization of elements is further progressing. Along with this, for example, the gate wiring width in the MOS transistor is also reduced. Furthermore, the sheet resistance of the source / drain tends to increase as the diffusion layer becomes shallower. As a result, there arises a problem that the response speed of the element deteriorates. If the gate delay time is τpd,
Operating frequency f ~ l / τpd
As a result, the improvement of the operating frequency cannot be expected. This is disadvantageous particularly for a microprocessor, particularly an MPU that requires high-speed operation.
[0003]
Therefore, as a countermeasure, silicide having a low resistance selectively only on the source / drain, particularly TiSi.₂Attention has been focused on the SALICIDE technology for forming the film.
[0004]
In the current MOS transistor manufacturing process, transistors are manufactured by the following process.
[0005]
(A) Refer to FIG. An element isolation region 12 (LOCOS-SiO) is formed on a semiconductor substrate 1 (here, Si substrate).₂). Next, the oxide film 17a (SiO2) used as the gate insulating film 17 is formed.₂23), and further, each layer of polycrystalline Si 15a and tungsten silicide (hereinafter also referred to as WSi) 15b constituting the gate wiring is laminated on the entire surface to form the WSi / PolySi structure 15. The structure is as follows.
[0006]
(B) Furthermore, LP-TEOS-SiO for offset oxide film₂A film 2 is formed (FIG. 24).
[0007]
(C) Gate patterning is performed by a photolithography technique to form the offset oxide film 2, the gate structure 15, and the gate insulating film 17, and LDD ion implantation is performed. Thereby, the structure of FIG. 25 is obtained. The LDD region is indicated by reference numerals 14a and 14b.
[0008]
(D) LP-TEOS-SiO for LDD sidewall formation₂The film is formed again. The entire surface is etched back to form side walls 16a and 16b. Source / drain formation ion implantation and activation heat treatment are performed to form source / drains 13a and 13b (FIG. 26).
[0009]
(E) Ti is formed on the entire surface, and a reaction between Ti and Si is caused by heat treatment, for example, two-step heat treatment to form Ti salicides 10a and 10b on the source / drains 13a and 13b.
[0010]
In the above process, a MOS transistor having a W polycide structure made of WSi / PolySi and a Ti salicide structure on the source / drains 13a and 13b is formed (FIG. 27).
[0011]
Here, there is a problem that the LP-TEOS oxide film 2 for offset oxide film is in direct contact with the WSi 15b. Considering the thermal history of FIG. 24 and subsequent figures in which LP-TEOS2 is formed on WSi 15b, the temperature is about 700 ° C. at the time of forming LP-TEOS for the LDD sidewall, and before performing source / drain ion implantation, In order to prevent channeling, a heat treatment at about 800 ° C. accompanying the entire surface oxidation and a high temperature heat treatment at about 1000 ° C. accompanying the activation heat treatment for source / drain ion implantation are performed. By these heat treatments, the following degassing occurs from the LP-TEOS oxide film 2 directly formed on the WSi.
-Si-O-C₂H_Five→ -Si-O₂-O-H + C₂H_Five-C₂H_Five(Ki)
-(Si-OH)₂  → -Si-OSi- + H₂O
Under the influence of this degassing, for example, the following reaction proceeds between the lower layer WSi and the generated gas. That is
aWSi₂+ BH₂O → cWO + dSiO₂+ ...
(A, b, c, d are integers)
And other reactions are promoted. In particular, at about 800 ° C., WO sublimes.
[0012]
As a result, the LP-TEOS oxide film 2 and the like on the WSi 15b are peeled off (shown by reference numeral 2A) as schematically shown in FIG. The problem that causes the problem occurs. Such peeling occurs particularly remarkably in a fine gate pattern. For example, in a relatively large pattern of about 2 μm, even if degassing occurs in a part of the pattern (for example, a swelling of 0.2 μm occurs), the LP-TEOS oxide film may be the other part of the underlying WSi. However, in a fine pattern (for example, in the case of 0.3 μm), the LP-TEOS oxide film peels off with a bulge of 0.2 μm.
[0013]
This problem causes a significant decrease in MOSFET yield. (In addition, H generated by heat from degassing, especially P-TEOS, etc.₂As a result of analyzing O, refer to FIG. 5 of IEDM94, pp120, and as a general theory of a structure using WSi, Semiconductor World 1984.2, “Low-pressure CVD tungsten silicide for IC process” and 1978 American Institute of Physics, pp76- “ OxidationMechanism in WSi₂  thin films ").
[0014]
The problem of peeling and reaction due to gas as described above is a problem in any case when using a film that generates gas by degassing due to temperature rise. In addition to TEOS (tetraethoxysilane), degassing also occurs from a film formed by other organic silicon sources such as DADBS (diacetoxyditertiarybutoxysilane), DES (diethylsilane), or the like.
[0015]
[Problems to be solved by the invention]
  The present invention has been made in view of the above circumstances,When using a film that generates gas by degassing due to temperature rise, no degassing occurs.An object is to provide a method for manufacturing a semiconductor device.
[0016]
[Means for Solving the Problems]
  A method for manufacturing a semiconductor device of the present invention includes:
  A film formation structure formed by laminating a first film and a second film on a semiconductor substrate is provided, the first film is a film that generates gas by degassing due to a temperature rise, and the second film is A method of manufacturing a semiconductor device, which is a film that does not react with a gas generated from the first film and has a film formation structure in which the second film is formed on a base of the first film,
  In the method of manufacturing a semiconductor device, after the first film is formed on the second film, heat treatment is performed to sufficiently degas the first film.
  The semiconductor device is a MOS type semiconductor device, wherein a gate wiring is formed, the entire surface is oxidized, an offset film is then formed as a first film, and degassing is generated by heat treatment. Production method
It is.
  In addition, a method for manufacturing a semiconductor device of the present invention includes:
  A film formation structure formed by laminating a first film and a second film on a semiconductor substrate is provided, the first film is a film that generates gas by degassing due to a temperature rise, and the second film is A method of manufacturing a semiconductor device, which is a film that does not react with a gas generated from the first film and has a film formation structure in which the second film is formed on a base of the first film,
  In the method of manufacturing a semiconductor device, after the first film is formed on the second film, heat treatment is performed to sufficiently degas the first film.
  The semiconductor device MOS A gate wiring having a refractory metal silicide is formed, and the entire surface is oxidized to obtain a surface oxide film of the refractory metal silicide, which is used as a second film, and then the first film. As an offset film CVD A method of manufacturing a semiconductor device, characterized by forming an oxide film and causing degassing by heat treatment
Is.
[0021]
In carrying out the present invention, the following various aspects can be taken.
[0022]
(1) A second film that does not react with the gas generated from the first film to be formed in the structure having the first film that generates gas by degassing by applying temperature on the film formation substrate. A film forming structure in which is formed on the first film base.
[0023]
(2) In the case where the first film is formed on the deposition substrate, the formed first film is formed with a first film that releases a kind of gas that does not react with the gas generated by the heat treatment and the base. Membrane structure.
[0024]
(3) A film forming structure in which, when an offset film is formed on a wiring, a film that does not react with a gas generated by heat from the offset film to be formed is formed on the wiring.
[0025]
(4) A film forming structure in which the first film shown in (2) is an offset film.
[0026]
(5) A film forming structure in which the substrate shown in the above (1) and (2) is a substrate structure having a gate wiring structure in a MOSFET.
[0027]
(6) A film forming structure in which the first film shown in the above (1) and (2) and the offset film shown in (3) and (4) are used as insulating films.
[0028]
(7) A film forming structure in which the second film shown in (1) is an insulating film.
[0029]
(8) In the structure shown in the above (1) to (4), after an offset film or the like as the first film is formed on the second film, sufficient degassing can be performed from the first film. A method for manufacturing a film-formed structure to which heat treatment is applied.
[0030]
(9) A method of manufacturing a semiconductor device in which a gate wiring in a MOSFET is formed, the entire surface is oxidized, an offset film is formed as a first film, and degassing is caused by heat treatment.
[0031]
(10) In the MOSFET, on the gate wiring having WSi, for example, SiN (silicon nitride) that does not cause degassing and does not react with the gas generated by degassing is formed, and a CVD oxide film is further formed. A wiring structure having a CVD / SiN offset oxide film.
[0032]
(11) In the MOSFET, on the gate wiring having WSi, for example, SiN, which is a material that does not cause degassing and does not react with the gas generated by degassing, is formed, and a CVD oxide film is further formed. A method for manufacturing a semiconductor device in which a heat treatment for degassing is subsequently performed from a CVD oxide film, and a wiring structure having a CVD film / SiN offset oxide film.
[0033]
(12) A transition metal silicide (TiSi) such as a polycide structure is used as a base film or a gate wiring structure.₂Or CoSi₂Etc.) or a wiring structure having a refractory metal such as W or Mo.
[0034]
(13) As the first insulating film, LP-TEOS, SiH_FourSiO₂LP-SiN, P-SiN, thermal SiO as a second insulating film₂A structure that has such as.
[0035]
Note that in this specification, the word MOS is not limited to a metal-oxide-semiconductor, but is used as a general term for a structure having a conductive material-insulating material-semiconductor structure.
[0036]
[Action]
According to the present invention, the first film to be degassed is such that the gas generated from it does not react with the base (for example, the second film to be formed in particular), and therefore, inconvenience such as film peeling due to reaction with the gas. Can be prevented. As a result, even if it is applied to a fine structure (for example, even if the transistor rule is reduced), the lower layer wiring such as a thin-film polycide gate can be formed without peeling, and it has high integration, high frequency, low voltage, and low power consumption. A semiconductor device (LSI or the like) can be stably manufactured. Alternatively, similar effects can be obtained by using a film that does not cause degassing.
[0037]
Further, since the means of the present invention can be realized on an extension of the conventional process, the manufacturing cost of a semiconductor such as an LSI does not increase.
[0038]
【Example】
Examples of the present invention will be specifically described below. However, as a matter of course, the present invention is not limited by the examples described below.
[0039]
Example 1
This embodiment embodies the present invention as a transistor structure capable of stably forming a W polycide gate structure having an offset oxide film and a manufacturing method thereof for a fine MOSFET.
[0040]
As described as a problem of the prior art, the occurrence of the problem is the use of a film that generates gas due to a temperature rise, specifically, for example, degassing from an LP-TEOS oxide film, and further degassing. The seed is to react with the underlying, eg, the underlying WSi. Therefore, this embodiment is a structure and manufacturing method that prevents such degassing and / or prevents the reaction between the degassing species and the underlying Si.
[0041]
In this embodiment, the offset insulating film structure is formed from the top of the LP-TEOS / SiN / WSi so that degassing occurs in the upper LP-TEOS oxide film and gas does not react with the underlying WSi. The structure. FIG. 1 shows the structure of this embodiment, and FIGS. 2 to 8 show the steps of this embodiment. Refer to each figure.
[0042]
As shown in FIG. 1, the film formation structure of the present embodiment forms a first film 2 on a substrate 1 (here, a Si substrate), and the first film 2 is degassed due to a temperature rise. A gas generating film (specifically, the first film 2 of this embodiment is an LP-TEOS oxide film), and the gas generated by the first film 2 is a kind of gas that does not react with the base. is there. In this embodiment, the base is a formed SiN film.
[0043]
In particular, in this embodiment, an offset film, which is a film that generates gas by degassing due to a temperature rise, is formed as the first film 2 on the substrate 1, and the gas generated by the offset film does not react with the base. It was made to be gas.
[0044]
More particularly, in this embodiment, in the film formation structure formed by laminating the first film 2 and the second film 3 on the substrate 1, the first film 2 is degassed due to a temperature rise to generate gas. The second film 3 is a film that does not react with the gas generated from the first film 2 (SiN film), and the second film 3 is the first film 2. The film formation structure is formed on the underlayer.
[0045]
In this embodiment, in particular, an offset film 2 (TEOS oxide film) is formed as a first film on a wiring (here, the gate wiring 15) formed on the substrate 1, and a gas generated by heat from the offset film 2 is formed. A film that does not react with the film was formed on the wiring 15 as the second film 3 (SiN film).
[0046]
This embodiment shows a semiconductor device. A first film 2 is formed on a semiconductor substrate 1, and the first film 2 is a film that generates gas by degassing due to a temperature rise. 1 shows a semiconductor device having a structure in which the gas generated by the first film 2 is a kind of gas that does not react with the base.
[0047]
In particular, this semiconductor device has a film-forming structure formed by laminating a first film 2 and a second film 3 on a semiconductor substrate 1, and the first film 2 generates gas by degassing due to temperature rise. The second film 3 is a film that does not react with the gas generated from the first film 2, and the second film 3 is formed on the base of the first film 2. A semiconductor device having a structure.
[0048]
In the case of this embodiment, the first film 2 in this semiconductor device is an offset film.
[0049]
Further, the offset film 2 in the semiconductor device of this embodiment is an insulating film.
[0050]
In the present embodiment, the second film 3 is an insulating film (particularly an SiN film).
[0051]
The device manufacturing process of the present embodiment includes a film formation structure (FIG. 1) formed by laminating a first film 2 and a second film 3 on a semiconductor substrate 1, and the first film 2 has a temperature rise. The second film 3 is a film that does not react with the gas generated from the first film, and the second film is used as an underlayer for the first film. In the case of manufacturing a semiconductor device by forming, the first film 2 was formed on the second film 3 (FIG. 4) and then patterned to form a MOS transistor (FIG. 1).
[0052]
In particular, this embodiment is a method for manufacturing a MOS type semiconductor device, in which a gate wiring 15 is formed, the entire surface is oxidized, an offset film is then formed as the first film 2, and degassing is caused by heat treatment. And
[0053]
In this embodiment, the gate wiring 15 has WSi 15b, SiN (second film 3) is formed on the gate wiring 15, and a CVD oxide film (first film 2) is further formed as an offset film.
[0054]
More specifically, in this embodiment, the following steps (a) to (h) are performed. Please refer to FIG. 1 and FIGS.
(A) LOCOS formation and gate oxidation are performed as the element isolation region 12 to form a gate insulating film 17, and WSi / PolySi for gate wiring is formed on the entire surface. Here, the thickness of PolySi 15a is 100 nm, and the thickness of WSi 15b (corresponding to a film that may react with the LP-TEOS oxide film as the first film 2 to be degassed) is 100 nm.
[0055]
(B) LP-SiN is formed on the entire surface under the following conditions.
Formation conditions
Gas SiH₂Cl₂/ NH_Three/ N₂= 90/600 / 1000sccm
Pressure 53Pa
700 ° C
Film thickness 50nm
Thereby, a SiN film as the second film 3 is formed, and the structure shown in FIG. 3 is obtained.
[0056]
(C) SiO by LP-TEOS on the entire surface₂Is formed under the following conditions.
Formation conditions
Gas TEOS = 300sccm
Pressure 93Pa
700 ° C
Film thickness 200nm
As a result, TEOS-SiO is formed as the first film 2 as an offset film.₂Are formed to obtain the structure of FIG.
[0057]
(D) Gate patterning is performed by dry etching. First, TEOS-SiO as the first film 3 under the following conditions:₂Is etched to pattern the offset film.
Etching conditions
Gas CHF_Three/ CO = 60 / 240sccm
RF power 1200W
Pressure 5.3Pa
[0058]
Next, dry etching of the gate material (WSi15b, PolySi15a) is performed under the following conditions. Thereby, gate patterning is performed.
conditions
Gas Cl₂/ O₂= 75 / 2sccm
Pressure 0.4Pa
Microwave power 750W
RF bias 80W
Over-etching conditions
Gas HBr / O₂= 120 / 4sccm
Pressure 1.3Pa
Microwave power 750W
RF bias 30W
[0059]
Further, LDD ion implantation is performed under the following conditions.

Thus, the structure of FIG. 5 in which the gate patterning and the LDD regions 14a and 14b are formed is obtained.
[0060]
(E) LP-TEOS oxide film formation is performed again under the following conditions for forming LDD sidewalls.
conditions
Gas TEOS = 300sccm
Pressure 93Pa
700 ° C
Film thickness 250nm
The entire surface is etched back to form sidewalls 16a and 16b, and source / drain ion implantation under the following conditions and activation heat treatment at 1000 ° C. for 10 seconds are performed.

Thus, the structure of FIG. 6 in which the source / drains 13a and 13b are formed is obtained.
[0061]
(F) After Ti is formed on the entire surface under the following conditions, Ti salicide is formed on the source / drains 13a and 13b by two-step heat treatment.
Ti formation conditions
Power 1kW
Deposition temperature 150 ° C
Gas Ar = 100sccm
Film thickness 30nm
Pressure 0.47Pa
In the two-step heat treatment, first, heat treatment at 600 ° C. is applied, and TiSi₂Form. Furthermore, unreacted Ti is selectively removed by dipping in an ammonia-hydrogen peroxide solution mixture. Furthermore, TiSi stabilized by heat treatment at 800 ° C₂To form. As a result, silicide layers 10a and 10b are formed to obtain the salicide structure shown in FIG.
[0062]
(G) SiO₂The interlayer film is formed as follows.
conditions
Gas TEOS = 50sccm
Temperature 720 ° C
Pressure 40Pa
Film thickness 600nm
Resist patterning is performed, and the connection hole 20 is formed by dry etching under the following conditions.
Dry etching conditions
Gas C_FourF₈= 50sccm
RF power 1200W
Pressure 2Pa
Thus, the structure of FIG. 8 in which the connection hole 20 (contact hole) is formed in the interlayer film 18 is obtained.
[0063]
(H) A wiring material is formed. That is, here, the blanket W is formed as the filling material 21 in the connection hole 20.
Prior to embedding, TiN / Ti is formed as a W adhesion layer. First, Ti is formed under the following conditions.
Ti formation conditions
Power 8kW
Deposition temperature 150 ° C
Gas Ar = 100sccm
Film thickness 10nm
Pressure 0.47Pa
Further, TiN is formed under the following conditions.
TiN formation conditions
Power 5kW
Gas Ar / N₂= 40 / 20sccm
Pressure 0.47Pa
Film thickness 70nm
Next, the blanket W is formed under the following conditions.
W formation conditions
Gas Ar / N₂/ H₂/ WF₆= 2200/300/500 / 75sccm
450 ° C
Pressure 10640Pa
Film thickness 400nm
W is etched back under the following conditions, leaving W only in the connection hole 20.
Etch back condition
Gas SF₆= 50sccm
RF power 150W
Pressure 1.33Pa
Thus, the connection hole 20 is embedded.
[0064]
Next, as an upper layer wiring, an Al / Ti wiring is formed as follows. First, Ti is deposited.
Ti film forming conditions
Power 4kW
Deposition temperature 150 ° C
Gas Ar = 100sccm
Film thickness 30nm
Pressure 0.47Pa
Further, Al is deposited under the following conditions. (Al may be an Al-based alloy material such as Al-1 wt% Si or Al-Si-Cu.)
Al film formation conditions
Power 22.5kW
Deposition temperature 150 ° C
Gas Ar = 50sccm
Film thickness 0.5μm
Pressure 0.47Pa
Thereafter, patterning is performed by resist patterning and dry etching under the following conditions to form an Al / Ti wiring layer.
conditions
Gas BCl_Three/ Cl₂= 60 / 90sccm
Microwave power 1000W
RF power 50W
Pressure 0.016Pa
[0065]
In this embodiment, the following specific effects can be obtained.
(1) Even if the transistor rule is reduced, the thin film W polycide gate can be formed without peeling, and an LSI with high integration, high frequency, low voltage and low power consumption can be stably produced.
(2) LSI manufacturing cost does not increase because it can be realized on the extension of the conventional process.
(3) Since WSi peeling does not occur during LSI manufacturing, no particles are generated and the manufacturing yield of LSI is improved.
(4) A W polycide structure can be formed stably even in a narrow space.
[0066]
Example 2
In this example as well, the present invention is applied to the same transistor as in Example 1, but the heat treatment process is devised here. That is, here, immediately after formation of the LP-TEOS / SiN / WSi structure, that is, without patterning, a heat treatment is sufficiently performed in advance at a temperature at which moisture and the like are completely removed while being deposited on the entire surface. Degassing during the phase. As a result, degassing was not generated by the heat treatment in the subsequent process. That is, the device manufacturing process of the present embodiment has a film formation structure (FIG. 11) formed by laminating the first film 2 and the second film 3 on the semiconductor substrate 1, and the first film 2 has the temperature The second film 3 is a film that does not react with the gas generated from the first film, and the second film is used as a base of the first film. In the case of manufacturing the semiconductor device by forming the first film 2 on the second film 3, after the first film 2 is formed on the second film 3, a heat treatment that can sufficiently degas the first film 2 as shown in FIG. 11 is performed. It is set as the structure to add. Here, since SiN is formed on the underlayer, the reaction between the underlayer WSi and the degassing component does not occur during degassing.
[0067]
In this example, the following steps (a) to (c) are performed (the subsequent steps are the same as those in Example 1). Please refer to FIG. 9 to FIG.
(A) LOCOS is formed as the element isolation region 12 in the same manner as in Example 1, gate oxidation is performed to form the gate insulating film 17, and WSi15b / PolySi15a for gate wiring is formed on the entire surface. Thus, the structure of FIG. 9 is obtained.
[0068]
(B) LP-SiN is formed on the entire surface under the following conditions.
Formation conditions
Gas SiH₂Cl₂/ NH_Three/ N₂= 90/600 / 1000sccm
Pressure 53Pa
700 ° C
Film thickness 50nm
Thereby, a SiN film as the second film 3 is formed (FIG. 10).
[0069]
(C) SiO by LP-TEOS on the entire surface₂Is formed under the following conditions.
Formation conditions
Gas TEOS = 300sccm
Pressure 93Pa
700 ° C
Film thickness 200nm
As a result, TEOS-SiO is formed as the first film 2 as an offset film.₂Is obtained as shown in FIG.
[0070]
Thereafter, heat treatment is performed at 800 ° C. for 30 minutes in a nitrogen atmosphere. Thereby, the gas in LP-TEOS which is the first film 3 to be degassed is released at this stage. Degassing is indicated by arrows in the schematic diagram. At this time, since the released gas does not react with the underlying second film 3 (SiN), problems such as peeling do not occur.
[0071]
The subsequent steps (d) and thereafter are the same as those in Example 1. As described above, since the gas is released from the first film 2 (offset film) in advance, degassing does not occur in the subsequent steps, and therefore there is no inconvenience due to degassing.
[0072]
Example 3
In this example, a thin thermal oxide film is formed on the surface of the WSi by subjecting the same target as in Example 1 to the entire surface after the WSi / PolySi film is formed. On top of that, LP-TEOS is formed. The thermal oxide film on the surface of the WSi functions as the second film 3a that does not react with the gas from the first film 2 to prevent the reaction with the degassing component from the LP-TEOS (first film 2) ( Regarding WSi oxidation, “Oxidation machinery in WSi₂  thin films ", S. Zirinsky, et.al., Appl.Phys.Lett.33 (1), 1 July 1978, page 76).
[0073]
This embodiment will be described in detail below. Please refer to FIG. 12 to FIG.
(A) LOCOS is formed as the element isolation region 12 in the same manner as in Example 1, gate oxidation is performed to form the gate insulating film 17, and WSi15b / PolySi15a for gate wiring is formed on the entire surface (FIG. 12). ).
[0074]
(B) Oxidizing the entire surface. For example, the surface oxidation of WSi15b can be performed under the following conditions. As a result, the structure of FIG. 13 in which a thermal oxide film is formed as the second film 3a is obtained.
Oxidation conditions
Gas H₂O / O₂Mixed gas = 1.0 liter / min.
Temperature 900 ° C
10 minutes
Film thickness 50nm
[0075]
(C) SiO by LP-TEOS on the entire surface₂Is formed under the following conditions.
Formation conditions
Gas TEOS = 300sccm
Pressure 93Pa
700 ° C
Film thickness 200nm
As a result, TEOS-SiO is formed as the first film 2 as an offset film.₂Is obtained as shown in FIG. Where TEOS-SiO₂Even if degassing is generated from the film 2 during the film formation or during various heat treatment steps after the film formation, the thermal oxide film 3 does not react with the gas, and thus serves as a protective film for protecting the base. . In FIG. 14, degassing is schematically indicated by arrows.
[0076]
Thereafter, the same steps as those in the step (d) of the first embodiment are performed. As described above, even if degassing occurs in various processes, adverse effects are blocked by the thermal oxide film.
[0077]
Example 4
In this example, as an offset insulating film, H₂This is the case where a film such as O that does not degas is used. For example, LP-SiN is used. That is, as shown in FIG. 17, the semiconductor device of this embodiment has a film formation structure in which an offset film 4 is formed on a gate wiring 15 on a semiconductor substrate. It is a film that does not occur (a film that does not degas. Here, SiN).
[0078]
Hereinafter, the device process of this embodiment will be described in detail with reference to FIGS.
(A) LOCOS is formed as the element isolation region 12 in the same manner as in Example 1, gate oxidation is performed to form the gate insulating film 17, and WSi15b / PolySi 15a for gate wiring is formed on the entire surface (FIG. 15). ).
[0079]
(B) LP-SiN as an offset insulating film is formed on the entire surface under the following conditions. As a result, a film 4 that does not degas is formed on the WSi15b / PolySi15a. The structure shown in FIG.
Formation conditions
Gas SiH₂Cl₂/ NH_Three/ N₂= 90/600 / 1000sccm
Pressure 53Pa
700 ° C
Film thickness 50nm
[0080]
(C) Gate patterning is performed by dry etching under the following conditions. First, the non-degassing film 4 (offset film) made of SiN is patterned as follows. Etching conditions
Gas CHF_Three/ O₂= 45 / 5sccm
RF power 1000W
Pressure 2.7Pa
Next, dry etching of the gate material (WSi15b, PolySi15a) is performed under the following conditions. Thereby, gate patterning is performed.
conditions
Gas Cl₂/ O₂= 75 / 2sccm
Pressure 0.4Pa
Microwave power 750W
RF bias 80W
Over-etching conditions
Gas HBr / O₂= 120 / 4sccm
Pressure 1.3Pa
Microwave power 750W
RF bias 30W
[0081]
Further, LDD ion implantation is performed under the following conditions (FIG. 17). The LDD regions are indicated by 14a and 14b.

[0082]
Hereinafter, the process proceeds in the same manner as in the process (e) and subsequent steps in the first embodiment. In this embodiment, SiN, which is a film 4 that does not generate gas, is used, so there is no inconvenience due to degassing and no problem of peeling occurs.
[0083]
Example 5
In this embodiment, only the gate wiring portion is patterned in advance. Thereafter, the entire surface is oxidized. Further, an LP-TEOS oxide film is formed, and the LP-TEOS oxide film is patterned with a gate sidewall margin. A gate sidewall and an offset oxide film are formed simultaneously. Since it is formed at the same time, the heat history can be reduced accordingly. Therefore, there are few discharge | release degassing components. Further, since the WSi surface region is covered with the thermal oxide film, there is an advantage that the reaction with degassing from the LP-TEOS oxide film does not proceed.
[0084]
This will be specifically described below. Please refer to FIG. 18 to FIG.
(A) LOCOS is formed as the element isolation region 12 in the same manner as in Example 1, gate oxidation is performed to form the gate insulating film 17, and WSi15b / PolySi15a for gate wiring is formed on the entire surface (FIG. 18). ).
[0085]
(B) Gate patterning is performed by dry etching under the following conditions.
conditions
Gas Cl₂/ O₂= 75 / 2sccm
Pressure 0.4Pa
Microwave power 750W
RF bias 80W
Over-etching conditions
Gas HBr / O₂= 120 / 4sccm
Pressure 1.3Pa
Microwave power 750W
RF bias 30W
[0086]
After patterning as described above to form the gate structure 15, LDD ion implantation is further performed under the following conditions (FIG. 19). The LDD region is indicated by reference numerals 14a and 14b.

[0087]
(C) Next, in this embodiment, the entire surface is oxidized under the following conditions. As a result, as shown in FIG. 20, a structure is obtained in which the oxide film 5 is formed on the entire upper surface and side surfaces of the gate structure 15 and the LDD regions 14a and 14b.
conditions
Gas H₂O / O₂Mixed gas = 1.0 liter / min.
Temperature 900 ° C
10 minutes
Film thickness 50nm
[0088]
(D) Next, on the entire surface, as the first film 2 with the possibility of degassing as an offset film, SiO by LP-TEOS is used.₂Is formed under the following conditions.
Formation conditions
Gas TEOS = 300sccm
Pressure 93Pa
700 ° C
Film thickness 300nm
[0089]
(E) The first film 2 (TEOS oxide film) formed as described above is patterned under the following dry etching conditions in consideration of the gate sidewall.
Dry etching conditions
Gas CHF_Three/ O₂= 45 / 5sccm
RF power 1000W
Pressure 2.7Pa
[0090]
Further, source / drain ion implantation is performed under the following conditions, and activation heat treatment is performed at 1000 ° C. for 10 seconds to form source / drains 13a and 13b (FIG. 22).

[0091]
Thereafter, the same processes as those after the process (f) in the first embodiment are performed. In this embodiment, since the first film 2 (TEOS oxide film) is formed on the gate 15, especially the WSi 15 b, via the thermal oxide film 5 functioning as the second film, the influence of degassing is cut off and peeled off. Such a problem does not occur.
[0092]
Example 6 (Modification)
In each of the above embodiments, other means may be used as long as the above-described object is achieved. In particular, in each of the above embodiments, the present invention is applied to a structure having W polycide as a gate material. However, the present invention can be applied to other structures having silicide, for example, transition metal silicide such as Ti silicide, Co silicide, Ni silicide, etc. In the example (modified example), the same operation and effect were obtained by performing the gate structure using these various silicides. Further, in each of the above embodiments, SiN or a thermal oxide film is used as the material for the insulating film that is in direct contact with the silicide. For example, an insulating film such as oxynitride can be applied. In this example (modification example), good results were obtained by using SiOxNy. Moreover, although each said Example took MOSFET as an example as a semiconductor structure, this invention can be used universally also to the device which has the possibility of producing the said problem, such as devices, such as a bipolar transistor and CCD. In the example (variation example), the present invention was also suitable for these devices, but good results were obtained as well.
[0093]
【The invention's effect】
  As detailed above,According to the method for manufacturing a semiconductor device of the present invention,Various problems such as film peeling due to degassing can be solved, and this effect is also exhibited in the case of using a film that generates gas by degassing due to temperature rise.
[Brief description of the drawings]
1 is a cross-sectional view showing a film forming structure and a semiconductor device of Example 1. FIG.
FIG. 2 is a cross-sectional view sequentially showing the steps of Example 1 (1).
FIG. 3 is a cross-sectional view showing the steps of Example 1 in order (2).
FIG. 4 is a cross-sectional view showing the steps of Example 1 in order (3).
FIG. 5 is a sectional view sequentially showing the steps of Example 1 (4).
FIG. 6 is a cross-sectional view showing the steps of Example 1 in order (5).
FIG. 7 is a sectional view sequentially showing the steps of Example 1 (6).
FIG. 8 shows sectional views of the steps of Example 1 in order (7).
FIG. 9 is a cross-sectional view sequentially showing the steps of Example 2 (1).
FIG. 10 is a sectional view sequentially showing the steps of Example 2 (2).
FIG. 11 is a sectional view sequentially showing the steps of Example 2 (3).
FIG. 12 is a cross-sectional view sequentially showing the steps of Example 3 (1).
FIG. 13 is a sectional view sequentially showing the steps of Example 3 (2).
FIG. 14 is a sectional view sequentially showing the steps of Example 3 (3).
FIG. 15 is a sectional view sequentially showing the steps of Example 4 (1).
FIG. 16 is a cross-sectional view sequentially showing the steps of Example 4 (2).
17 is a cross-sectional view of the steps of Example 4 in order (3), and is a cross-sectional view of the semiconductor device of Example 4. FIG.
FIG. 18 is a sectional view sequentially showing the steps of Example 5 (1).
FIG. 19 is a cross-sectional view sequentially showing the steps of Example 5 (2).
FIG. 20 is a cross-sectional view sequentially showing the steps of Example 5 (3).
FIG. 21 shows sectional views of the steps of Example 5 in order (4).
FIG. 22 shows sectional views of the steps of Example 5 in order (5).
FIG. 23 is a cross-sectional view showing the steps of a conventional example in order (1).
FIG. 24 is a sectional view showing steps of a conventional example in order (2).
FIG. 25 is a sectional view showing the steps of a conventional example in order (3).
FIG. 26 is a sectional view showing steps of a conventional example in order (4).
FIG. 27 is a sectional view showing steps of a conventional example in order (5).
FIG. 28 is an enlarged schematic view of a part A in FIG. 26 and is a diagram showing problems of the prior art.
[Explanation of symbols]
1 Semiconductor substrate (Si substrate)
12 Device isolation region
13a, 13b Source / drain regions
14a, 14b LDD region
15 Gate wiring
15a PolySi (gate material)
15b WSi (Gate material)
16a, 16b Gate sidewall
17 Gate oxide film
18 SiO₂
22 TiN / Ti
21 W
23 Al-Si
10a, 10b TiSi₂
2 First film (offset film, LP-TEOS oxide film)
3 Second film (film that does not react with gas, LP-SiN)
3a Second film (film that does not react with gas, thermal SiO₂)
4 Film that does not degas (thermal oxide film)
4 Film that does not degas (LP-SiN)
5 Film that does not react with gas (thermal oxide film)

Claims (2)

A film formation structure formed by laminating a first film and a second film on a semiconductor substrate is provided, the first film is a film that generates gas by degassing due to a temperature rise, and the second film is A method of manufacturing a semiconductor device, which is a film that does not react with a gas generated from the first film and has a film formation structure in which the second film is formed on a base of the first film,
In the method of manufacturing a semiconductor device, after the first film is formed on the second film, heat treatment is performed to sufficiently degas the first film.
The semiconductor device is a MOS type semiconductor device, wherein a gate wiring is formed, the entire surface is oxidized, an offset film is then formed as a first film, and degassing is generated by heat treatment. Production method. A film formation structure formed by laminating a first film and a second film on a semiconductor substrate is provided, the first film is a film that generates gas by degassing due to a temperature rise, and the second film is A method of manufacturing a semiconductor device, which is a film that does not react with a gas generated from the first film and has a film formation structure in which the second film is formed on a base of the first film,
In the method of manufacturing a semiconductor device, after the first film is formed on the second film, heat treatment is performed to sufficiently degas the first film.
The semiconductor device is a MOS type semiconductor device, a gate wiring having a refractory metal silicide is formed, the entire surface is oxidized to obtain a surface oxide film of the refractory metal silicide, and this is used as a second film, and then a second film is formed. A method of manufacturing a semiconductor device, comprising: forming a CVD oxide film as an offset film, which is a film 1; and causing degassing by heat treatment .

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