JP3941135B2 - Method for manufacturing transistor element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present inventionMethod for manufacturing transistor elementAbout.
[0002]
[Prior art]
  With the high integration of semiconductor devices, the dimensional rules of semiconductor manufacturing processes are also becoming finer. For this reason, even in the element isolation technology, the conventional LOCOS method cannot cope with miniaturization due to the influence of the bird's peak. Therefore, an SOI (Semiconductor On Insulator) technique has attracted attention as an element isolation technique in a 0.1 μm rule semiconductor element. Transistor elements using this SOI technology are highly resistant to α rays. Further, since there is no generation of parasitic capacitance between the source / drain portions and the semiconductor substrate, which is a problem in a transistor element manufactured using a bulk semiconductor substrate, high-speed operation of the transistor element can be obtained. Thus, in a transistor element using SOI technology, high reliability and high speed operation can be obtained.
[0003]
  Hereinafter, a method for manufacturing a MOS transistor using conventional SOI technology will be described.FIG.as well asFIG.This will be briefly described with reference to FIG.
[0004]
    [Step-10]
  First, the groove 20 is formed in one surface 10A of the first semiconductor substrate 10 made of silicon (FIG.(See (A)).
[0005]
    [Step-20]
  Next, an insulating layer 121 made of silicon oxide is deposited in the groove 20 and on one surface 10A of the first semiconductor substrate 10, and after a polysilicon layer 23 is further deposited on the insulating layer 121, The surface of the silicon layer 23 is planarized (FIG.(See (B)).
[0006]
    [Step-30]
  Thereafter, the polysilicon layer 23 formed above the one surface 10A of the first semiconductor substrate 10 is bonded to the second semiconductor substrate 11 made of silicon (FIG.(See (C)).
[0007]
    [Step-40]
  Next, the back surface side 10B of the first semiconductor substrate 10 is polished to expose the bottom surface 20A of the groove 20 (FIG.(See (D)). As a result, the semiconductor layer 30 made of silicon is exposed between the adjacent groove portions 20. Each of the semiconductor layers 30 is electrically separated by the groove 20 and the insulating layer 121. The semiconductor layer 30 is composed of the first semiconductor substrate 10.
[0008]
    [Step-50]
  Thereafter, a gate electrode part 41, a gate side wall 44, a channel part 45, a source part 46 and a drain part 47 are formed in the semiconductor layer 30 by a conventional method (FIG.(See (A)). Thus, a MOS transistor is manufactured.
[0009]
    [Step-60]
  Next, after an interlayer insulating layer 60 is deposited on the entire surface, an opening 61 is provided in the interlayer insulating layer 60 above the source part 46 and the drain part 47, and a metal is formed on the interlayer insulating layer 60 including the inside of the opening 61. A wiring material layer 62 is formed (FIG.(See (B)). As a result, a contact hole is formed. Thereafter, the metal wiring material layer 62 is patterned to form wiring.
[0010]
[Problems to be solved by the invention]
  In the MOS transistor having the SOI structure, the source part 46, the channel part 45, and the drain part 47 are formed on the insulating layer 121. Therefore, when the transistor element is on and holes or electrons move in the semiconductor layer 30, silicon atoms in the region where the holes or electrons move are ionized, and in the semiconductor layer 30 (particularly in the channel portion 45). To deposit. For this reason, breakdown voltage degradation between the source part / drain part occurs, or problems such as a short channel effect occur. In a normal MOS transistor, such a problem does not occur because the well is grounded through the semiconductor substrate.
[0011]
  As one means for solving this problem, the surface of the source part and the drain part (hereinafter sometimes collectively referred to as the source / drain part) has a salicide structure, and ions accumulated in the channel part are passed through the salicide structure. The grounding technology is described, for example, in the document "SUPPRESSION OF LATCH IN SOI MOSFETs BY SILICIDATION OF SOURCE", LJ McDAID, et al., ELECTRONICS LETTERS, 23rd May 1991, vol. 27 No. 11, pp1003-1005 . The salicide structure is formed by depositing a metal layer on the entire surface after forming the source part 46 and the drain part 47 in [Step-50]. Then, by heat-treating the metal layer, the element that forms the metal layer reacts with Si that forms the source / drain portion to form a silicide layer on the surface of the source / drain portion. However, even if such a salicide structure is formed, the ions accumulated in the channel part are not completely grounded, and the breakdown voltage between the source part / drain part is insufficiently improved.
[0012]
  When the dimension rule is 0.5 μm, the required thickness of the semiconductor layer 30 is about 100 nm, and when the dimension rule is 0.35 μm, the required thickness of the semiconductor layer 30 is about 70 nm. is there. As described above, the sheet resistance of the source part 46 and the drain part 47 increases as the semiconductor layer 30 becomes thinner. For example, when the thickness of the semiconductor layer 30 is about 100 nm, the sheet resistance is about 70 Ω / □, but when the thickness of the semiconductor layer 30 is about 70 nm, the sheet resistance increases to 100 Ω / □ or more. In the future, as the thickness of the semiconductor layer 30 is further reduced, the sheet resistance of the source part 46 and the drain part 47 will increase. Such an increase in sheet resistance increases the parasitic resistance of the transistor element and degrades the element characteristics.
[0013]
  By forming the silicide layer constituting the salicide structure in the source / drain portion, the resistance of the source / drain portion can be reduced. However, when titanium silicide is used, if the dimensional rule is 0.5 μm or less, aggregation is likely to occur during the formation of titanium silicide, and there is a problem that the resistance value of the formed titanium silicide layer increases. When aggregation occurs during the formation of titanium silicide, for example, the bulk resistivity of titanium silicide increases to about 16 μΩ · cm. Such a phenomenon occurs even when the silicide layer is thin. That is, as the thickness of the semiconductor layer 30 is reduced, the thickness of the silicide layer to be formed is also reduced. Accordingly, there is a problem that the sheet resistance of the silicide layer increases.
[0014]
  Further, when forming cobalt silicide, in order to promote a stable reaction between Si and Co constituting the source / drain portion, Ti (titanium) and Co (cobalt) are sequentially arranged on the source / drain portion from the bottom. By depositing and heat-treating the Co / Ti layer, Co and Si constituting the source / drain part are reacted through the Ti layer as a reducing material, thereby forming a cobalt silicide layer on the surface of the source / drain part. Technology is also known. However, for example, in the SOI structure, Si / SiO₂A layer structure is formed and SiO₂When a silicide layer is formed by reacting all of the silicon semiconductor layer on the layer with Co / Ti, the underlying SiO₂As a result, there is a problem that a high-resistance silicide layer is formed or a void is partially generated.
[0015]
  In Japanese Patent Application No. Hei 6-18991 (see Japanese Patent Application Laid-Open No. 7-2111916), the present applicant is a transistor element in which a channel part, a source part and a drain part are formed in a semiconductor layer formed on an insulating layer. (B) a gate electrode part; (b) a channel part formed under the gate electrode part; (c) a source part formed in contact with one side of the channel part; A first conductive region made of a metal or a metal compound formed in a semiconductor layer outside the source portion; (e) a drain portion formed in contact with the other side of the channel portion; and (f) the drain. A transistor element comprising a second conductive region formed on a semiconductor layer outside the portion and made of a metal or a metal compound, and a method for manufacturing the transistor element have been proposed.
[0016]
  In such a transistor element, since the first and second conductive regions are formed outside the source part and the drain part, it is possible to avoid the problem that the breakdown voltage between the source part and the drain part occurs. In addition, since the first and second conductive regions are formed, the sheet resistance of the source and drain portions is reduced by two to four digits compared to the conventional transistor element even if the semiconductor layer is thinned. Thus, the response speed of the transistor element can be improved.
[0017]
  However, when forming the first and second conductive regions, the elements constituting the first and second conductive regions react with the elements constituting the insulating layer, and as a result, the first conductive region or the second conductive region is formed. It has been found that voids may occur in the conductive region. When voids are generated in the first conductive region or the second conductive region in this manner, the resistance value varies and the reliability of the transistor element is lowered.
[0018]
  Accordingly, an object of the present invention is to improve the breakdown voltage between the source part / drain part, and the thickness of the semiconductor layer in which the channel part, the source part, and the drain part are to be formed with the miniaturization of the dimension rule. Even if the thickness is reduced, an increase in sheet resistance of the source and drain portions can be suppressed, and furthermore, an SOI structure that can suppress the occurrence of variation in resistance value is provided.Method for manufacturing transistor elementIs to provide.
[0019]
[Means for Solving the Problems]
  In order to achieve the above object, a method for manufacturing a transistor element according to the first aspect of the present invention includes:
  (A) After forming a groove in the first semiconductor substrate, filling the groove with an insulating material, and forming an element isolation region,
  (B) A part of the first conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the source part is to be formed and in the thickness direction from the surface. In addition, a part of the second conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the drain part is to be formed and in the thickness direction from the surface. And then
  (C) An insulating layer made of silicon nitride or silicon oxynitride is formed on the entire surface, and then
  (D) The first semiconductor substrate is bonded to the second semiconductor substrate through the insulating layer, and then polished from the back surface of the first semiconductor substrate, and the bottom of the groove formed in the first semiconductor substrate. After exposing
  (E) The remaining portion of the region outside the first semiconductor substrate region where the source portion is to be formed, in which the first conductive region has already been formed, is made of a metal or metal compound. In addition to the first conductive region, a region outside the region of the first semiconductor substrate where the drain portion is to be formed, the second conductive region below the region where the second conductive region has already been formed Forming a second conductive region of metal or metal compound, then
  (F) forming a gate electrode portion on the exposed region of the first semiconductor substrate, and then forming a source portion and a drain portion in the exposed region of the first semiconductor substrate;
It is characterized by that.
[0020]
  In addition, a method for manufacturing a transistor element according to the second aspect of the present invention for achieving the above object is as follows.
  (A) After forming a groove in the first semiconductor substrate, filling the groove with an insulating material, and forming an element isolation region,
  (B) A part of the first conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the source part is to be formed and in the thickness direction from the surface. In addition, a part of the second conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the drain part is to be formed and in the thickness direction from the surface. And then
  (C) An insulating layer made of silicon nitride or silicon oxynitride is formed on the entire surface, and then
  (D) The first semiconductor substrate is bonded to the second semiconductor substrate through the insulating layer, and then polished from the back surface of the first semiconductor substrate, and the bottom of the groove formed in the first semiconductor substrate. After exposing
  (E) forming a gate electrode portion on the exposed region of the first semiconductor substrate, then forming a source portion and a drain portion in the exposed region of the first semiconductor substrate, and then insulating the sidewall of the gate electrode portion; Forming a gate sidewall made of material, then
  (F) A region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate in which the source portion is to be formed and in which the first conductive region is already formed below. In addition to the first conductive region, a region outside the region of the first semiconductor substrate where the drain portion is to be formed, the second conductive region below the region where the second conductive region has already been formed Forming a second conductive region of metal or metal compound;
It is characterized by that.
[0021]
  Of the present invention1st aspect orIn the method for manufacturing the transistor element according to the second aspectThe process (b), Source and drain should be formedFirst semiconductor substrateOf the area outside the area ofsurfaceabove,First semiconductor substrateAfter forming a metal layer composed of an element that reacts with an element that constitutes the element, heat treatment is performed, and the element that constitutes the metal layerFirst semiconductor substrateAnd a step of forming a first conductive region and a second conductive region made of a metal compound.preferable.
[0022]
  Of the present invention1st aspect orIn the method for manufacturing the transistor element according to the second aspect,(B)so,First semiconductor substrateInstead of forming the first and second conductive regions in all the thickness directions ofFirst semiconductor substrateUp to a certain depth from one side ofFirst semiconductor substrateForming first and second conductive regions on the substrate;In the manufacturing method of the transistor element according to the first aspect of the present invention, in the step (e), and in the manufacturing method of the transistor element according to the second aspect of the present invention, in the process (f),Furthermore, the source part should be formedFirst semiconductor substrateThe remaining portion (in the thickness direction) of the first conductive region made of the metal compound is formed in the region outside the region, and the drain portion should be formed at the same timeFirst semiconductor substrateThe remaining portion (in the thickness direction) of the second conductive region made of a metal compound is placed outside the region ofForm. theseIn the process ofIs, At least outside the source partFirst semiconductor substrateAnd outside the drainFirst semiconductor substrateOn the other side ofFirst semiconductor substrateAfter depositing a metal layer composed of an element that reacts with an element that constitutes the element, heat treatment is performed, and the element that constitutes the metal layerFirst semiconductor substrateAnd the remaining portions of the first conductive region and the second conductive region made of the metal compound are reacted with each other.Form. Alternatively, the region outside the source portion and the drain portion can be formed by CVD.First semiconductor substrateIs replaced with a metal layer, so that the first conductive region and the second conductive region made of metal are replaced withForm.
[0023]
  Of the present inventionFirst aspectIn the manufacturing method of the transistor element according to the above,(F)After that, a gate side wall made of an insulating material is formed on the side wall of the gate electrode portion.ProcessMay be included. In this case, the process(B)so,First semiconductor substrateInstead of forming the first and second conductive regions in all the thickness directions ofFirst semiconductor substrateUp to a certain depth from one side ofFirst semiconductor substrateFirst and second conductive regions are formed on the gate sidewalls.ProcessTo the outside of the source sectionFirst semiconductor substrateForming a first conductive region made of a metal or a metal compound on the outer side of the drain portion.First semiconductor substrateForming a second conductive region made of a metal or metal compound on the substrate(E) is included. This process(E)Even at least outside the source partFirst semiconductor substrateAnd outside the drainFirst semiconductor substrateOn the other side ofFirst semiconductor substrateAfter depositing a metal layer composed of an element that reacts with an element that constitutes the element, heat treatment is performed, and the element that constitutes the metal layerFirst semiconductor substrateAnd the first conductive region and the second conductive region made of a metal compound are reacted with each other.Form.
[0024]
  In the method for manufacturing a transistor element according to the first or second aspect of the present invention, a structure in which a first semiconductor substrate and a second semiconductor substrate are bonded to each other is provided.Has an insulating layerIs a so-called bond SOI structure provided in the first semiconductor substrate in the vicinity of the bonded portion with the second semiconductor substrate.Form.
[0025]
  In the present invention,First and second aspectsIn the method for manufacturing a transistor element according to the present invention, the outside of the source and drain portionsFirst semiconductor substrateAre preferably replaced by first and second conductive regions of metal or metal compound. In the present invention, the first conductive region and the second conductive region can have not only a single layer structure but also a two-layer structure. In this case, the metal or metal compound in each layer constituting each conductive region may be the same or different.
[0026]
  Of the present inventionFirst and second aspectsIn the method for manufacturing a transistor element according to the present invention, the metal layer is made of a transition metal or a noble metal.First aspectThe method for producing a transistor element according to the aboveStep (b) or step (e)And the method for manufacturing a transistor element according to the second aspect of the present invention.Step (b) or step (f)Is
  (A)First semiconductor substrateThe elements constituting the metal and the transition metal or noble metal constituting the metal layer react, andFirst semiconductor substrateThe element constituting the metal layer and the oxide comprising the element constituting the metal layer at a temperature at which the transition metal or noble metal constituting the metal layer does not reactFirst semiconductor substratePerforming a first heat treatment to react with the elements constitutingThen
  (B) Remove the unreacted metal layerAfter,
  (C) Further, the elements constituting the metal layer andFirst semiconductor substrateA second heat treatment is performed to react with the elements constituting
It can be set as the aspect which consists of a process. The metal compound is preferably composed of cobalt silicide, titanium silicide, tungsten silicide, nickel silicide, platinum silicide, zirconium silicide, hafnium silicide, and the like. It is preferable to form cobalt silicide. Here, the metal layer is mainly composed of cobalt, or the silicide is mainly composed of cobalt silicide is that the metal layer may contain other metals or metal compounds, and the cobalt silicide is included. It means that other silicides (for example, titanium silicide) and other metal compounds may be contained.
[0027]
  In the present invention, since an insulating layer made of a material that does not easily react with the metal element constituting the first and second conductive regions is formed, the element constituting the metal layer andFirst semiconductor substrateIt is effective that voids are generated in the formed first and second conductive regions when the first conductive region and the second conductive region made of metal or a metal compound are formed by reacting with the elements constituting Can be suppressed.
[0028]
【Example】
  Hereinafter, with reference to the drawings, the embodimentAnd reference examplesThe present invention will be described based on the above. ExamplesAnd reference examplesWill be described by taking a MOS transistor as an example of the transistor element. still,Reference Example 1 and Reference Example 2 are for referenceThe present invention relates to a method for manufacturing a transistor element. That is, the first and second conductive regions are formed from the surface of the semiconductor layer on the side where the gate electrode portion is formed.Reference example 3Of the present inventionThe first aspect andMethod for manufacturing transistor element according to second aspectReference example to explainAbout. That is, the first and second conductive regions are formed from the surface of the semiconductor layer opposite to the side on which the gate electrode portion is formed.Example 1 and Example 2 relate to a method for manufacturing a transistor element according to the first and second aspects of the present invention, respectively.Also,Example 3The first aspect of the present inventionAnd the second aspectThe present invention relates to a method for manufacturing a transistor element.
[0029]
    (Reference example 1)
  Reference example 1As shown in the schematic partial cross-sectional view of FIG. 1, the transistor element of FIG. 1 includes an SOI structure in which a channel portion 45, a source portion 46, and a drain portion 47 are formed in a semiconductor layer 30 formed on an insulating layer 21. The gate electrode portion 41 is formed on the semiconductor layer 30. That is, it has a so-called bond SOI structure in which the first semiconductor substrate 10 and the second semiconductor substrate 11 are bonded together, the semiconductor layer 30 is composed of the first semiconductor substrate 10, and the insulating layer 21 is the second layer. The semiconductor substrate 11 is provided on the first semiconductor substrate 10 in the vicinity of the bonded portion. The channel part 45 is formed under the gate electrode part 41. The source part 46 is formed in contact with one side of the channel part 45, and the drain part 47 is formed in contact with the other side of the channel part 45.
[0030]
  Reference example 1The element characterizing the transistor element is that the first conductive region 51 made of a metal compound and formed in the semiconductor layer 30 outside the source part 46 and the metal compound formed in the semiconductor layer 30 outside the drain part 47. A second conductive region 52 made ofReference example 1These first and second conductive regions 51 and 52 in FIG. 1 are metal compounds composed of silicide, more specifically, cobalt silicide (CoSi).₂). Furthermore, the insulating layer 21 is made of a material that does not easily react with the metal element (Co) constituting the first and second conductive regions, specifically, silicon nitride (SiN). The first conductive region 51 is surrounded by the insulating layer 21 and the source portion 46. On the other hand, the second conductive region 52 is surrounded by the insulating layer 21 and the drain portion 47.
[0031]
  Reference example 1In addition, an insulating material (for example, SiO 2) is formed on the sidewall of the gate electrode portion 41.₂), And the gate side wall 44 covers the source part 46 and the drain part 47.
[0032]
  Reference example 1The transistor element ofExplained belowIt is manufactured by a manufacturing method of a transistor element. In addition, the process of forming the gate side wall 44 which consists of an insulating material in the side wall of the gate electrode part 41 is included.
[0033]
  Metal compounds (specifically, cobalt silicide, CoSi₂The first conductive region 51 and the second conductive region 52 are formed of an element (specifically, the semiconductor layer 30 on the other surface 30B of the semiconductor layer 30 where the first and second conductive regions are to be formed. Specifically, after depositing a metal layer 50 made of an element that reacts with Si) (specifically, Co), a heat treatment is performed to form an element (specifically Co) that constitutes the metal layer and a semiconductor layer. It is formed by reacting with an element (specifically, Si).
[0034]
  Hereinafter, referring to FIGS.Reference example 1A method for manufacturing the transistor element will be described.
[0035]
    [Step-A-10]
  An insulating layer 21 is formed on one surface of the semiconductor layer 30. Specifically, first, a first semiconductor substrate 10 made of Si (100) is prepared. And after apply | coating and drying a resist to one side 10A of this 1st semiconductor substrate 10, a resist is patterned using the photolithographic technique. Next, the first semiconductor substrate 10 is dry-etched using the patterned resist as a mask to form a groove 20 on one surface 10A of the first semiconductor substrate 10, and then the resist is removed. The etching conditions for the first semiconductor substrate 10 are exemplified below.
      Gas used: SiCl_Four/ N₂= 10 / 10sccm
      Pressure: 1.3Pa
      Microwave power: 850W
      RF power: 200W
[0036]
  Thereafter, an insulating layer 21 made of silicon nitride (SiN) is deposited on one surface 10A of the first semiconductor substrate 10 including the inside of the groove 20 by the LP-CVD method. Thus, the structure shown in FIG. 2A can be obtained. The deposition conditions for the insulating layer 21 are exemplified below. This insulating layer 21 will be described later.Step-A-80In the first and second heat treatments, the first and second conductive regions 51 and 52 are made of a material (specifically, SiN) that does not easily react with the metal element (specifically, Co). Therefore, the occurrence of voids in the first conductive region 51 and the second conductive region 52 can be reliably prevented.
    Gas used: SiH₂Cl₂/ NH_Three/ N₂= 90/600 / 1000sccm
    Pressure: 53Pa
    Temperature: 700 ° C
    Film thickness: 50 nm
[0037]
    [Step-A-20]
  Thereafter, silicon oxide (SiO 2) is formed on the insulating layer 21.₂The second insulating layer 22 made of) is deposited by the CVD method. The CVD conditions for the second insulating layer 22 are exemplified below. Note that the second insulating layer 22 embedded in the groove portion 20 functions as an element isolation region.
    Gas used: SiH_Four/ O₂= 100 / 1000sccm
              N₂= 30 slm
    Pressure: 13Pa
    Temperature: 420 ° C
    Film thickness: 0.4 μm
[0038]
  Alternatively, silicon oxide (SiO 2) is formed on the insulating layer 21 by the bias ECR CVD method under the following conditions.₂The second insulating layer 22 may be deposited.
    Gas used: SiH_Four/ N₂O / Ar = 14/35 / 72sccm
    Pressure: 0.093 Pa
    Temperature: 400 ° C
    Microwave: 1000W
    Film thickness: 0.4 μm
[0039]
    [Step-A-30]
  Next, a polysilicon layer 23 is deposited on the second insulating layer 22 by, for example, the LP-CVD method under the following conditions. The polysilicon layer 23 serves as an interface when the second semiconductor substrate 11 is bonded to the first semiconductor substrate 10 in a later step, and the first semiconductor substrate 10 and the second semiconductor substrate 11 are bonded together. It has a function as an adhesive layer.
      Gas used: SiH_Four/ H₂/ N₂= 100/400 / 200sccm
      Temperature: 610 ° C
      Pressure: 70Pa
      Film thickness: 0.2μm
[0040]
  Thereafter, a resist is applied to the surface of the polysilicon layer 23, and the entire surface is etched back to flatten the polysilicon layer 23. This state is shown in a schematic partial sectional view in FIG. The conditions for etch back are exemplified below.
      Gas used: C₂Cl_ThreeF_Three/ SF₆= 60 / 10sccm
      Pressure: 1.3Pa
      Microwave power: 850W
      RF power: 150W
[0041]
  Next, the surface of the polysilicon layer 23 is polished, and the surface of the polysilicon layer 23 is bonded to the second semiconductor substrate 11 made of silicon (see FIG. 2C). The bonding can be performed by performing a heat treatment of 1100 ° C. × 30 minutes, for example, in a state where the first and second semiconductor substrates 10 and 11 are overlapped.
[0042]
    [Step-A-40]
  Thereafter, the first semiconductor substrate 10 is polished from the back surface side 10B of the first semiconductor substrate 10, and silicon (more specifically, silicon constituting the first semiconductor substrate 10) is provided between the adjacent groove portions 20. The semiconductor layer 30 made of is exposed (see FIG. 3A). When polishing proceeds to the bottom surface 20A of the groove part 20, the insulating layer 21 made of SiN formed in the groove part 20 is exposed. Since SiN is harder than Si, SiN serves as a polishing stopper and can prevent the semiconductor layer 30 from being excessively polished. Thus, a substrate having an SOI structure in which the insulating layer 21 is formed on one surface 30A of the semiconductor layer 30 is manufactured.
[0043]
    [Step-A-50]
  Next, the gate electrode portion 41 having a polycide structure is formed on the other surface 30 </ b> B of the semiconductor layer 30. Therefore, on the other surface 30B of the semiconductor layer 30, first, a SiO 2 is used by using a conventional method.₂A gate oxide film 40 is formed. Thereafter, a polysilicon film (DOPOS) 42 doped with impurities is deposited on the gate oxide film 40 by a CVD method. For example, the polysilicon film 42 can be formed under the following conditions.
      Gas used: SiH_Four/ PH_Three/He=500/0.35/50sccm
      Temperature: 580 ° C
      Pressure: 80Pa
      Film thickness: 0.15 μm
[0044]
  Next, WSi is formed on the polysilicon film 42.₂The layer 43 is formed by a CVD method. WSi₂The layer 43 can be formed, for example, under the following conditions.
      Gas used: WF₆/ SiH_Four/ He = 10/1000 / 360sccm
      Temperature: 360 ° C
      Pressure: 27Pa
      Film thickness: 0.15 μm
[0045]
  Then WSi₂A resist is applied on the layer 43, the resist is patterned, and dry etching is performed to form WSi.₂The layer 43 and the polysilicon film 42 are etched, for example, under the following conditions to remove the resist. As a result, the gate oxide film 40, the polysilicon film 42, and the WSi.₂A gate electrode portion 41 composed of the layer 43 is formed (see FIG. 3B).
      Gas used: C₂Cl_ThreeF_Three/ SF₆= 65 / 5sccm
      Pressure: 1.3Pa
      Microwave power: 700W
      RF power: 100W
[0046]
    [Step-A-60]
  Thereafter, the source part 46 and the drain part 47 are formed in the semiconductor layer 30, and the channel part 45 is formed in the semiconductor layer 30 below the gate electrode part 41. Specifically, after forming a resist mask and forming the n-type or p-type source portion 46 / drain portion 47 by, for example, ion implantation (see FIG. 4A), 1000 ° C. A 10-second RTA (Rapid Thermal Annealing) process is performed to activate the implanted impurities. The ion-implanted region may extend outside the region where the source part 46 and the drain part 47 of the semiconductor layer 30 are to be formed. The conditions for ion implantation are exemplified below.
      Formation of n-type source / drain
            Ion: As
            Dose amount: 5 × 10¹⁴/ Cm²
            Accelerating voltage: 30 keV
      Formation of p-type source / drain
            Ion: BF₂
            Dose amount: 1 × 10¹⁴/ Cm²
            Accelerating voltage: 30 keV
[0047]
    [Step-A-70]
  Next, a gate side wall 44 made of an insulating material is formed on the side wall of the gate electrode portion 41 (see FIG. 4B). Specifically, the entire surface is SiO.₂An insulating material layer made of is deposited by the CVD method exemplified below.
      Gas used: SiH_Four/ O₂/ N₂= 250/250 / 100sccm
      Temperature: 420 ° C
      Film thickness: 0.35 μm
[0048]
  Thereafter, the gate sidewall 44 made of an insulating material is formed by anisotropic dry etching. The dry etching conditions can be set as follows, for example.
      Gas used: C_FourF₈= 50sccm
      Pressure: 2Pa
      RF power: 1200W
[0049]
  Thus,Reference example 1In FIG. 5, the source part 46 and the drain part 47 are covered with the gate side wall 44. In this state, the exposed region of the semiconductor layer 30 is a region sandwiched between the gate sidewall 44 and the groove 20. In this region, first and second conductive regions are formed by the following process.
[0050]
    [Step-A-80]
  That is, the first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion 46, and the second conductive region 52 made of a metal compound is also formed in the semiconductor layer 30 outside the drain portion 47. Form.Reference example 1For this purpose, after forming the metal layer 50 on the other surface 30B of the semiconductor layer 30 where the first and second conductive regions are to be formed, cobalt (Co) which is an element constituting the metal layer 50 and Si that is an element constituting the semiconductor layer 30 is reacted. That is, the metal layer 50 is made of cobalt (Co), and the first and second conductive regions 51 and 52 are made of cobalt silicide (CoSi).₂).
[0051]
  Specifically, first, a metal layer 50 made of cobalt is deposited on the entire surface by a sputtering method (see FIG. 5A). The thickness of the metal layer 50 is set to be equal to or greater than the thickness necessary for reacting all the Si corresponding to the thickness of the semiconductor layer 30 made of Si. For example, film forming conditions for the metal layer 50 made of Co having a thickness of 0.1 μm are exemplified below.
      Gas used: Ar = 100 sccm
      Pressure: 0.47Pa
      DC power: 8kW
      Film thickness: 0.1 μm
[0052]
  Next, Co, which is an element constituting the metal layer 50, is reacted with Si, which is an element constituting the semiconductor layer 30, to form a metal compound (specifically, cobalt silicide, CoSi).₂) Is generated. The region of the semiconductor layer 30 that reacts with the metal layer 50 is a region sandwiched between the gate sidewall 44 and the groove 20, and the first and second conductive regions are formed in this region. The reaction between the elements constituting the metal layer 50 and the elements constituting the semiconductor layer 30 is desirably performed in the following process, but the conditions are not limited to the following examples.
[0053]
  First, an element (specifically, Si) constituting the semiconductor layer 30 reacts with a transition metal (specifically, Co) constituting the metal layer 50, and an element (specifically, the semiconductor layer 30 is constituted). Is an oxide composed of Si (specifically, SiO₂) And a transition metal (specifically, Co) constituting the metal layer 50 are desirably reacted with an element constituting the metal layer 50 and an element constituting the semiconductor layer 30 at a temperature at which the metal does not react. This process is referred to as a first heat treatment. Specifically, for example, heat treatment is performed at 550 ° C. for 30 seconds in nitrogen gas (flow rate: 5 liters / minute). As a result, CoSi_XIs generated.
[0054]
  Next, the unreacted metal layer is treated with, for example, ammonia perwater (NH_FourOH and H₂O₂For about 10 minutes. This unreacted metal layer is a metal layer deposited on the trench 20, on the gate sidewall 44 and on the gate electrode 41. In this way, the first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion 46, and at the same time, the second conductive region 52 made of a metal compound is formed in the semiconductor layer 30 outside the drain portion 47. It is formed.
[0055]
  Thereafter, a second heat treatment is performed in an argon gas atmosphere, for example, 700 ° C. × 30 seconds, and CoSi_XCoSi₂And In these first and second heat treatments, a material (specifically SiN) that does not easily react with the metal element (specifically Co) constituting the first and second conductive regions 51 and 52 is used. Since the insulating layer 21 formed is formed, it is possible to reliably prevent the generation of voids in the first conductive region 51 and the second conductive region 52. As a result, the resistance values of the first and second conductive regions 51 and 52 do not vary and a highly reliable transistor element can be manufactured. Thus, the transistor element shown in FIG. 1 is manufactured.
[0056]
    [Step-A-90]
  Next, SiO₂An interlayer insulating layer 60 made of is deposited on the entire surface by, for example, a CVD method under the following conditions.
      Gas used: TEOS = 50sccm
      Temperature: 720 ° C
      Pressure: 40Pa
      Film thickness: 0.6μm
[0057]
  Thereafter, an opening 61 is formed in the interlayer insulating layer 60 above the first and second conductive regions 51 and 52 as necessary. The conditions for anisotropic etching of the interlayer insulating layer 60 are exemplified below.
      Gas used: C_FourF₈= 50sccm
      Pressure: 2Pa
      RF power: 1200W
[0058]
    [Step-A-95]
  Next, a metal wiring material layer 62 is deposited on the interlayer insulating layer 60 including the opening 61. (See FIG. 5B). still,Reference example 1In this case, tungsten is embedded in the opening 61 by a so-called blanket tungsten CVD method. A metal wiring material made of an aluminum alloy is deposited on the interlayer insulating layer 60. In FIG. 5B, illustration of various layers constituting the wiring layer is omitted.
[0059]
  Specifically, prior to embedding tungsten in the opening 61, first, a contact layer made of Ti and a barrier metal layer made of TiN are formed on the interlayer insulating layer 60 including the inside of the opening 61 by, for example, sputtering. Form. The contact layer is formed for the purpose of reducing the contact resistance between tungsten embedded in the opening 61 and the first and second conductive regions 51 and 52. The barrier metal layer is formed for the purpose of preventing the tungsten buried in the opening 61 from reacting with the first and second conductive regions 51 and 52. Thereafter, tungsten is deposited on the entire surface by a blanket tungsten CVD method, and then the tungsten deposited on the interlayer insulating layer 60 is removed by etching back.
      Contact layer formation conditions
            Gas used: Ar = 100 sccm
            Temperature: 150 ° C
            Film thickness: 30nm
            Pressure: 0.47Pa
            Power: 4kW
    Barrier metal layer formation conditions
            Gas used: N₂/ Ar = 70 / 40sccm
            Temperature: 150 ° C
            Film thickness: 70nm
            Pressure: 0.47Pa
            Power: 5kW
    Blanket tungsten CVD conditions
            Gas used: WF₆/ H₂/ N₂/ Ar = 75/500/300 / 2200sccm
            Temperature: 450 ° C
            Pressure: 1.1 × 10^FourPa
            Film thickness: 0.4μm
    Etch-back conditions for tungsten
            Gas used: SF₆= 50sccm
            Pressure: 1.3Pa
            RF power: 150W
[0060]
  Next, a Ti layer is formed on the entire surface by sputtering, and a metal wiring material made of, for example, Al-Si (1%) is deposited thereon by sputtering. The Ti layer is formed for the purpose of improving the adhesion and wettability between the metal wiring material and the interlayer insulating layer 60. Thereafter, the metal wiring material and the Ti layer are etched. As a result, a wiring having a desired pattern is formed on the interlayer insulating layer 60. The wiring made of the metal wiring material and the Ti layer, and the source part 46 and the drain part 47 are connected via the opening 61 (that is, the contact hole) in which tungsten is embedded and the first and second conductive regions 51 and 52. Are electrically connected.
      Ti layer formation conditions
            Gas used: Ar = 100 sccm
            Temperature: 150 ° C
            Film thickness: 30nm
            Pressure: 0.47Pa
            Power: 4kW
      Film formation conditions for Al-Si metal wiring materials
            Gas used: Ar = 40 sccm
            Temperature: 300 ° C
            Film thickness: 0.5μm
            Pressure: 0.47Pa
            Power: 22.5kW
      Etching conditions for Al-Si / Ti layer
            Gas used: BCl_Three/ Cl₂= 60 / 90sccm
            Pressure: 0.016Pa
            Microwave power: 1000W
            RF power: 50W
[0061]
  More thanReference example 1The manufacturing method of the transistor element is summarized as follows.
(1)  A groove 20 is formed in the first semiconductor substrate 10, and an insulating layer 21 is formed on the surface of the first semiconductor substrate 10 including the groove 20. This step corresponds to a step of forming an insulating layer on one surface 30A of the semiconductor layer 30. The insulating layer 21 is made of a material that does not easily react with the metal elements constituting the first and second conductive regions, and examples thereof include silicon nitride (SiN) and silicon oxynitride (SiON).
(2)  A second insulating layer 22 and a polysilicon layer 23 are formed on the insulating layer 21. After the polysilicon layer 23 is planarized, the first semiconductor substrate 10 and the second semiconductor are interposed via the polysilicon layer 23. The substrate 11 is attached. Thereafter, polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom portion of the groove portion 20 formed in the first semiconductor substrate 10. Thereby, a substrate having a so-called SOI structure is manufactured.
(3)  A gate electrode part 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30).
(4)  A source part 46 and a drain part 47 are formed in the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), and a channel part 45 is formed under the gate electrode part 41.
(5)  A gate sidewall 44 made of an insulating material is formed on the side wall of the gate electrode portion 41.
(6)  After the metal layer 50 is formed on the entire surface, the elements constituting the metal layer 50 and the elements constituting the semiconductor layer 30 are reacted by heat treatment, then the unreacted metal layer is removed, and the metal layer 50 is further removed. In order to react the element constituting the element and the element constituting the semiconductor layer 30, heat treatment is performed. As a result, a first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion 46, and at the same time, a second conductive region 52 made of a metal compound is formed in the semiconductor layer 30 outside the drain portion 47. Is formed.
[0062]
    (Reference example 2)
  Reference example 1In FIG. 1, the first conductive region 51 and the second conductive region 52 are made of cobalt silicide. On the contrary,Reference example 2The first conductive region 51 and the second conductive region 52 are mainly made of cobalt silicide, and titanium silicide and TiO._Xincluding. The metal layer has a two-layer structure of a cobalt (Co) layer and a titanium (Ti) layer from the top. In particular,Reference Example 2 is the same as [Step-A-80] in Reference Example 1.Is different. Only the differences will be described below.
[0063]
  Instead of [Step-A-80] in Reference Example 1, Reference Example 21, the first conductive region 51 made of a metal compound is formed in the semiconductor layer 30 outside the source portion 46, and the second conductive region 52 made of a metal compound is also formed in the semiconductor layer 30 outside the drain portion 47. In order to form the metal layer 50, the metal layer 50 made of Ti and Co is formed from the bottom on the other surface 30B of the semiconductor layer 30 where the first and second conductive regions are to be formed. The element and the element constituting the semiconductor layer 30 are reacted. The first and second conductive regions 51 and 52 are mainly made of cobalt silicide (CoSi).₂In addition, titanium silicide (TiSi)₂) And TiO_XIs included. Titanium is a natural oxide film SiO present on the surface of the semiconductor layer 30.₂It reacts with oxygen atoms therein, and the surface (top surface) of the first and second conductive regions 51 and 52 has TiO._XIs formed.
[0064]
  Specifically, first, under the conditions exemplified below, a Ti layer is deposited on the entire surface by sputtering, and a cobalt layer is further deposited thereon. The thickness of the cobalt layer is set to a thickness greater than that required for reacting all the Si corresponding to the thickness of the semiconductor layer 30 made of Si.
  (Ti layer deposition)
      Gas used: Ar = 100 sccm
      Pressure: 0.47Pa
      Temperature: 150 ° C
      DC power: 4kW
      Film thickness: 10 μm
  (Co layer deposition conditions)
      Gas used: Ar = 100 sccm
      Pressure: 0.47Pa
      Temperature: 150 ° C
      DC power: 8kW
      Film thickness: 0.1 μm
[0065]
  Next, Co / Ti constituting the metal layer 50 and Si constituting the semiconductor layer 30 are reacted to form a metal compound (specifically, mainly cobalt silicide, CoSi₂Others, titanium silicide, TiSi₂And TiO_X) Is generated. Specifically, this process is[Step-A-80] of Reference Example 1The first heat treatment step, the unreacted metal layer removal step, and the second heat treatment step in FIG.
[0066]
    (Reference example 3)
  Reference example 3The structure of this transistor element is basically shown in FIG.Reference example 1It is the same. That is,Reference example 3In FIG. 2, the first conductive region 51 and the second conductive region 52 are mainly composed of cobalt silicide. In addition, the first conductive region 51 and the second conductive region 52 include titanium silicide (TiSi).₂) And TiO_XIs included.Reference example 3In the case of the insulating material (for example, SiO 2)₂) Is formed.
[0067]
  Reference example 3The transistor element ofReference example 1OrReference example 2Unlike the present inventionFirst aspectIn a method for manufacturing a transistor element according toSimilar fabrication methodIt is produced by. In addition, the process of forming the gate side wall 44 which consists of an insulating material in the side wall of the gate electrode part 41 is included.
[0068]
  Metal compounds (specifically, mainly cobalt silicide, CoSi₂The first conductive region 51 and the second conductive region 52 are formed on the semiconductor layer 30 on one surface 30A of the semiconductor layer 30 in a region outside the region of the semiconductor layer where the source portion and the drain portion are to be formed. After forming a metal layer 50 (specifically, a cobalt layer and a titanium layer) having an element that reacts with an element (specifically, Si) constituting the metal, heat treatment is performed, and an element (specifically, the metallic layer 50 is constituted). Is formed by reacting an element (specifically, Si) constituting the semiconductor layer 30 with cobalt.
[0069]
  Hereinafter, referring to FIGS.Reference example 3A transistor element and a manufacturing method thereof will be described.
[0070]
  First, the first conductive region 51 made of a metal compound is formed in a region outside the region where the source portion of the semiconductor layer 30 is to be formed, and at the same time, the region outside the region where the drain portion of the semiconductor layer 30 is to be formed. Then, a second conductive region 52 made of a metal compound is formed. Metal compounds are mainly cobalt silicide (CoSi₂In addition, titanium silicide (TiSi)₂) And TiO_XIs included.
[0071]
    [Step-C-10]
  To that end, first[Step-A-10] of Reference Example 1The groove 20 is formed on one surface 30A of the semiconductor layer 30 (specifically, on one surface 10A of the first semiconductor substrate 10) by the same process as in the previous step.
[0072]
    [Process-C-20]
  Thereafter, the silicon nitride (SiN) layer 100 and the silicon oxide (SiO 2) are formed on the one surface 10A of the first semiconductor substrate 10 including the inside of the groove 20.₂The layer 101 is sequentially deposited by the LP-CVD method and the bias ECR-CVD method, and then a planarization process is performed to leave the silicon oxide layer 101 and the silicon nitride layer 100 only in the trench 20. Thereby, an element isolation region is formed. This state is shown in a schematic partial sectional view in FIG.
  (Silicon nitride film formation conditions)
    Gas used: SiH₂Cl₂/ NH_Three/ N₂= 90/600 / 1000sccm
    Pressure: 53Pa
    Temperature: 700 ° C
    Film thickness: 50 nm
  (Silicon oxide layer deposition conditions)
    Gas used: SiH_Four/ N₂O / Ar = 14/35 / 72sccm
    Microwave: 1000W
    Temperature: 400 ° C
    Pressure: 0.093 Pa
    Film thickness: 0.4 μm
[0073]
    [Step-C-30]
  Next, after forming the metal layer 50 on one surface 30A of the semiconductor layer 30 (specifically, on one surface 10A of the first semiconductor substrate 10), the metal layer 50 is patterned, After leaving the metal layer 50 on one surface 30A of the semiconductor layer 30 where the second conductive region is to be formed, Co / Ti that is an element constituting the metal layer 50 and Si that is an element constituting the semiconductor layer 30 And react. The metal layer 50Reference example 2The first and second conductive regions 51 and 52 are mainly made of cobalt silicide (CoSi).₂In addition, titanium silicide (TiSi)₂) And TiO_XIs included.
[0074]
  Specifically, first,Reference example 2Then, titanium and cobalt are sequentially deposited on the entire surface of one surface 30A of the semiconductor layer 30 by the sputtering method under the same conditions as above to form the metal layer 50 (see FIG. 6B). The thickness of the Co layer constituting the metal layer 50 may be set to a thickness greater than that necessary for reacting all the Si corresponding to the thickness of the semiconductor layer 30 made of Si, for example, 0.1 μm. In FIGS. 6B and 6C, the first semiconductor substrate 10 is roughly shaded to clearly show the semiconductor layer 30.
[0075]
  Next, the metal layer 50 made of Co / Ti is patterned to leave the metal layer 50 on one surface 30A of the semiconductor layer 30 where the first and second conductive regions are to be formed ((C) in FIG. 6). reference). Note that the metal layer on the groove 20 may or may not be removed. That is, the metal layer 50 above the region of the semiconductor layer where the channel part, the source part and the drain part are to be formed is removed. The dry etching conditions for the metal layer 50 are exemplified below.
      Gas used: BCl_Three/ Cl₂= 60 / 90sccm
      Pressure: 0.016Pa
      Microwave power: 1000W
      RF power: 50W
[0076]
  Thereafter, Co / Ti constituting the metal layer 50 and Si constituting the semiconductor layer 30 are reacted to form a metal compound (specifically, mainly cobalt silicide, titanium silicide, and TiO)._XIs included). The region of the semiconductor layer 30 that reacts with the metal layer 50 is a region sandwiched between the source portion formation planned region and the groove portion 20, and a region sandwiched between the drain portion formation planned region and the groove portion 20. Second conductive regions 51 and 52 are formed (see FIG. 6D). The reaction between the elements constituting the metal layer 50 and the elements constituting the semiconductor layer 30 is as follows:[Step-A-80] of Reference Example 1The detailed process is omitted because it can be performed by the same process.
[0077]
    [Step-C-40]
  Then, for example, SiH₂Cl₂/ N₂O / N₂An insulating layer 21 made of silicon oxynitride (SiON) is deposited on the entire surface by the CVD method using the LP-CVD method. This insulating layer 21 is made of [Step-C-30] Formed of a material (specifically, SiON) that does not easily react with the metal element (specifically, Co) that constitutes the first and second conductive regions 51, 52 formed in the above. This insulating layer 21 is formed of silicon oxide (SiO2) formed in the next step.₂) And a function of preventing the first and second conductive regions 51 and 52 from reacting with each other. Therefore, the occurrence of voids in the first conductive region 51 and the second conductive region 52 can be reliably prevented.
  (Deposition conditions for insulating layer 21 made of silicon oxynitride)
    Gas used: SiH₂Cl₂/ NH_Three/ N₂/ O₂= 50/200/200 / 50sccm
    Pressure: 600Pa
    Temperature: 400 ° C
    Film thickness: 100 nm
[0078]
    [Process-C-50]
  Thereafter, on the insulating layer 21, for example, silicon oxide (SiO 2 having a thickness of 0.4 μm)₂The second insulating layer 22 made ofProcess-C-20] By the bias ECR-CVD method under the same conditions as exemplified above.
[0079]
    [Process-C-60]
  Then[Step-A-30] of Reference Example 1After the polysilicon layer 23 is formed on the second insulating layer 22 under the same conditions as described above, the polysilicon layer 23 is planarized by an etch back method (see FIG. 7A). The surface and the second semiconductor substrate 11 made of silicon are bonded together (see FIG. 7B). afterwards,[Step-A-40] of Reference Example 1In the same manner as described above, the first semiconductor substrate 10 is polished from the back surface side 10B of the first semiconductor substrate 10, and silicon (more specifically, the first semiconductor substrate 10 is formed between the adjacent groove portions 20). The semiconductor layer 30 made of silicon is exposed (see FIG. 8A). Thus, the insulating layer 21 is formed on the one surface 30A of the semiconductor layer 30, and a substrate having an SOI structure is manufactured. First and second conductive regions 51 and 52 are formed in the semiconductor layer 30 of the substrate. Note that when the first semiconductor substrate 10 is polished from the back surface side 10B of the first semiconductor substrate 10, the silicon nitride (SiN) existing on the bottom surfaces of the first and second conductive regions 51 and 52 and the groove portion 20 is removed. As a polishing stopper, it is possible to reliably prevent the semiconductor layer 30 from being excessively shaved.
[0080]
    [Step-C-70]
  Or later,[Step-A-50] to [Step-A-70] of Reference Example 1(This state is shown in FIG. 8B),[Step-A-90] and [Step-A-95]To complete the MOS transistor having the SOI structure shown in FIG. The first conductive regions 51 </ b> A and 51 </ b> B are surrounded by the insulating layer 21, the silicon nitride layer 100, and the source part 46. On the other hand, the second conductive regions 52 </ b> A and 52 </ b> B are surrounded by the insulating layer 21, the silicon nitride layer 100, and the drain portion 47. FIG. 9 shows a state in which a metal wiring material layer 62 is deposited on the interlayer insulating layer 60 including the opening 61. Note that the width of the source portion 46 and the drain portion 47 to be formed in the semiconductor layer 30 is at least twice the total of the limit misalignment amounts in the exposure apparatus used for the patterning of the metal layer 50 and the patterning of the gate electrode portion 41, respectively. It is preferable to design so that it becomes the width | variety. Without such a width, due to misalignment in the exposure apparatus, the region of the semiconductor layer in which the source part 46 or the drain part 47 is to be formed becomes too narrow. In the worst case, the source part 46 or the drain part 47 is formed. This is because the region of the semiconductor layer to be lost is lost.
[0081]
  More thanReference example 3The manufacturing method of the transistor element is summarized as follows.
(1)  A trench 20 is formed in the first semiconductor substrate 10 and the trench 20 is filled with an insulating material to form an element isolation region.
(2)  A metal layer 50 is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51 and 52 are to be formed. That is, after the metal layer 50 is formed on the first semiconductor substrate 10, the metal layer above the region of the semiconductor layer where the channel portion, the source portion, and the drain portion are to be formed is removed. Then, the elements constituting the metal layer 50 and the elements constituting the semiconductor layer 30 (first semiconductor substrate 10) are reacted by heat treatment, then the unreacted metal layer is removed, and further the metal layer 50 is removed. In order to react the element constituting the element and the element constituting the semiconductor layer 30, heat treatment is performed. As a result, a first conductive region 51 made of a metal compound is formed in a region outside the region of the semiconductor layer 30 where the source portion 46 is to be formed, and at the same time, the region of the semiconductor layer 30 where the drain portion 47 is to be formed. A second conductive region 52 made of a metal compound is formed in the outer region.
(3)  An insulating layer 21 is formed on the entire surface. This step corresponds to a step of forming the insulating layer 21 on one surface 30A of the semiconductor layer 30. The insulating layer 21 is made of a material that does not easily react with the metal elements constituting the first and second conductive regions 51 and 52, and examples thereof include silicon nitride (SiN) and silicon oxynitride (SiON). .
(4)  A second insulating layer 22 and a polysilicon layer 23 are formed on the insulating layer 21. After the polysilicon layer 23 is planarized, the polysilicon layer 23 and the second semiconductor substrate 11 are bonded together. Thereafter, polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom portion of the groove portion 20 formed in the first semiconductor substrate 10. Thereby, a substrate having a so-called SOI structure is manufactured.
(5)  A gate electrode part 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30).
(6)  A source portion 46 and a drain portion 47 are formed in the exposed region of the first semiconductor substrate 10 (corresponding to a semiconductor layer), and a channel portion 45 is formed under the gate electrode portion 41. Further, a gate sidewall 44 made of an insulating material is formed on the side wall of the gate electrode portion 41.
[0082]
    (Example 1)
  Example 1 is a modification of Reference Example 3 and relates to a method for manufacturing a transistor element according to the first aspect of the present invention. [Step-100], [Step-110], [Step-120], [Step-130], [Step-140], [Step-150], [Step] in the method for manufacturing the transistor element of Example 1 -160] are [Step-C-10], [Step-C-20], [Step-C-30], [Step-C-40], and [Step-C-50] in Reference Example 3, respectively. , [Step-C-60] and [Step-C-70]. That is, Example 1First of all,[Step-C-10] to [Step-C-60] of Reference Example 3Execute. 10 and 11 are schematic partial cross-sectional views of the semiconductor substrate and the like obtained in these steps. 10 (A) to (D) and FIG. 11 (A) and (B) correspond to FIG. 6 (A) to (D) and FIG. 7 (A) and (B). Yes.Example 1InReference example 3Unlike the first embodiment, it is not necessary to form the first conductive region 51A and the second conductive region 52A based on the metal layer 50A in all the thickness directions of the semiconductor layer 30. That is, the thickness of the metal layer 50A isReference example 3Can be made thinner.
[0083]
  Thereafter, the upper portion (the remaining portion in the thickness direction) of the first conductive region 51A and the second conductive region 52A of the semiconductor layer 30 is silicided. In particular,Reference example 3of[Step-C-30] And a similar process may be executed. That is, after the metal layer 50B is formed on the other surface 30B of the semiconductor layer 30 (see FIG. 12A), the metal layer 50B is patterned to form the first and second conductive regions. After leaving the metal layer 50B on the other surface 30B of the layer 30, Co / Ti that is an element constituting the metal layer 50B and Si that is an element constituting the semiconductor layer 30 are reacted. The metal layer 50B isReference example 3The first and second conductive regions 51 and 52 are mainly composed of cobalt silicide, and in addition to titanium silicide and TiO._XIs included. A state in which the first conductive region 51B and the second conductive region 52B are formed is shown in FIG.
[0084]
  afterwards,[Step-A-50], [Step-A-60], [Step-A-70] of Reference Example 1By executing the above, the SOI structure shown in FIG. 13A can be obtained. Furthermore,[Step-A-90] and [Step-A-95] of Reference Example 1As a result, the MOS transistor having the SOI structure shown in FIG. 13B is completed.Example 1Since the first and second conductive regions 51A, 51B, 52A, and 52B are formed from both sides of the semiconductor layer 30, all of the semiconductor layer 30 in the thickness direction can be surely made conductive regions. still,Example 1The metal layer 50A and the metal layer 50B may be made of the same kind of metal or different kinds of metals.
[0085]
  More thanExample 1The manufacturing method of the transistor element is summarized as follows.
(1)  A trench 20 is formed in the first semiconductor substrate 10 and the trench 20 is filled with an insulating material to form an element isolation region.
(2)  A metal layer 50A is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51A and 52A are to be formed. That is, after the metal layer 50A is formed on the first semiconductor substrate 10, the metal layer above the region of the semiconductor layer where the channel part, the source part, and the drain part are to be formed is removed. Then, the elements constituting the metal layer 50A and the elements constituting the semiconductor layer 30 (first semiconductor substrate 10) are reacted by heat treatment, then the unreacted metal layer is removed, and further the metal layer 50A. In order to react the element constituting the element and the element constituting the semiconductor layer 30, heat treatment is performed. As a result, a first conductive region 51A partially made of a metal compound is formed in a region outside the region of the semiconductor layer 30 where the source portion 46 is to be formed (in the thickness direction of the semiconductor layer 30). A second conductive region 52A partially made of a metal compound is formed in a region outside the region of the semiconductor layer 30 where the drain portion 47 is to be formed (in the thickness direction of the semiconductor layer 30).
(3)  An insulating layer 21 is formed on the entire surface. This step corresponds to a step of forming the insulating layer 21 on one surface 30A of the semiconductor layer 30. The insulating layer 21 is made of a material that does not easily react with the metal elements constituting the first and second conductive regions 51 and 52, and examples thereof include silicon nitride (SiN) and silicon oxynitride (SiON). .
(4)  A second insulating layer 22 and a polysilicon layer 23 are formed on the insulating layer 21. After the polysilicon layer 23 is planarized, the polysilicon layer 23 and the second semiconductor substrate 11 are bonded together. Thereafter, polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom portion of the groove portion 20 formed in the first semiconductor substrate 10. Thereby, a substrate having a so-called SOI structure is manufactured.
(5)  A metal layer 50B is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51B and 52B are to be formed. That is, after forming the metal layer 50B on the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30), the region above the region of the semiconductor layer in which the channel portion, the source portion, and the drain portion are to be formed. Remove the metal layer. And the element which comprises the metal layer 50B, and the element which comprises the semiconductor layer 30 (1st semiconductor substrate 10) are made to react by heat-processing, Then, the unreacted metal layer 50B is removed, and also a metal layer In order to react the element constituting 50B and the element constituting the semiconductor layer 30, heat treatment is performed. As a result, the first conductive region 51B made of a metal compound is formed in the remaining portion in the thickness direction of the region outside the region of the semiconductor layer 30 where the source portion 46 is to be formed, and the drain portion 47 is also formed. A second conductive region 52B made of a metal compound is formed in the remaining portion in the thickness direction of the region outside the region of the semiconductor layer 30 to be formed.
(6)  A gate electrode part 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30).
(7)  In the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30 and in the region of the semiconductor layer sandwiched between the first conductive regions 51A and 51B and the gate electrode portion 41), the source portion 46 and the drain portion 47 The channel portion 45 is formed under the gate electrode portion 41. Further, a gate sidewall 44 made of an insulating material is formed on the side wall of the gate electrode portion 41.
[0086]
    (Example 2)
  Example 2 is also a modification of Reference Example 3 and relates to a method for manufacturing a transistor element according to the second aspect of the present invention.. That is,Example 2First of all,[Step-C-10] to [Step-C-60] of Reference Example 3Execute. However,Example 2Also inReference example 3Unlike the first embodiment, it is not necessary to form the first conductive region 51A and the second conductive region 52A based on the metal layer 50A in all the thickness directions of the semiconductor layer 30. That is, the thickness of the metal layer 50A isReference example 3Can be made thinner. Thus, the structure shown in FIG. 14A can be obtained.
[0087]
  Example 1Thereafter, the upper portion (the remaining portion in the thickness direction) of the first conductive region 51A and the second conductive region 52A of the semiconductor layer 30 was silicided. on the other hand,Example 2Then in[Step-A-50], [Step-A-60], [Step-A-70] of Reference Example 1By executing the above, the SOI structure shown in FIG. 14B can be obtained.
[0088]
  Thereafter, the upper portion (the remaining portion in the thickness direction) of the first conductive region 51A and the second conductive region 52A of the semiconductor layer 30 is silicided. In particular,Reference example 3of[Step-C-30] And a similar process may be executed. That is, after the metal layer 50B is formed on the entire surface of the semiconductor layer 30 (see FIG. 15A), Co / Ti that is an element constituting the metal layer 50B and Si that is an element constituting the semiconductor layer 30 are formed. React. The metal layer 50B isReference example 3The first and second conductive regions 51 and 52 are mainly composed of cobalt silicide, and in addition to titanium silicide and TiO._XIs included. FIG. 15B shows a state in which the first conductive region 51B and the second conductive region 52B are formed.
[0089]
  After that,[Step-A-90] and [Step-A-95] of Reference Example 1As a result, a MOS transistor having the same SOI structure as shown in FIG. 13B is completed.Example 2Also, since the first and second conductive regions 51A, 51B, 52A, and 52B are formed from both surfaces of the semiconductor layer 30, all of the semiconductor layer 30 in the thickness direction can be reliably set as the conductive regions. still,Example 2In this case, the metal layer 50A and the metal layer 50B may be made of the same kind of metal or different kinds of metals.
[0090]
  More thanExample 2The manufacturing method of the transistor element is summarized as follows.
(1)  A trench 20 is formed in the first semiconductor substrate 10 and the trench 20 is filled with an insulating material to form an element isolation region.
(2)  A metal layer 50A is formed on a region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30) where the first and second conductive regions 51A and 52A are to be formed. That is, after the metal layer 50A is formed on the first semiconductor substrate 10, the metal layer above the region of the semiconductor layer where the channel part, the source part, and the drain part are to be formed is removed. Then, the elements constituting the metal layer 50A and the elements constituting the semiconductor layer 30 (first semiconductor substrate 10) are reacted by heat treatment, then the unreacted metal layer is removed, and further the metal layer 50A. In order to react the element constituting the element and the element constituting the semiconductor layer 30, heat treatment is performed. As a result, a first conductive region 51A partially made of a metal compound is formed in a region outside the region of the semiconductor layer 30 where the source portion 46 is to be formed (in the thickness direction of the semiconductor layer 30). A second conductive region 52A partially made of a metal compound is formed in a region outside the region of the semiconductor layer 30 where the drain portion 47 is to be formed (in the thickness direction of the semiconductor layer 30).
(3)  An insulating layer 21 is formed on the entire surface. This step corresponds to a step of forming the insulating layer 21 on one surface 30A of the semiconductor layer 30. The insulating layer 21 is made of a material that does not easily react with the metal elements constituting the first and second conductive regions 51 and 52, and examples thereof include silicon nitride (SiN) and silicon oxynitride (SiON). .
(4)  A second insulating layer 22 and a polysilicon layer 23 are formed on the insulating layer 21. After the polysilicon layer 23 is planarized, the polysilicon layer 23 and the second semiconductor substrate 11 are bonded together. Thereafter, polishing is performed from the back surface of the first semiconductor substrate 10 to expose the bottom portion of the groove portion 20 formed in the first semiconductor substrate 10. Thereby, a substrate having a so-called SOI structure is manufactured.
(5)  A gate electrode part 41 is formed on the exposed region of the first semiconductor substrate 10 (corresponding to the other surface 30B of the semiconductor layer 30).
(6)  A source part 46 and a drain part 47 are formed in the exposed region of the first semiconductor substrate 10 (corresponding to the semiconductor layer 30), and a channel part 45 is formed under the gate electrode part 41. Further, a gate sidewall 44 made of an insulating material is formed on the side wall of the gate electrode portion 41.
(7)  After the metal layer 50B is formed on the entire surface, the elements constituting the metal layer 50B and the elements constituting the semiconductor layer 30 are reacted by heat treatment, then the unreacted metal layer is removed, and the metal layer 50B is further removed. In order to react the element constituting the element and the element constituting the semiconductor layer 30, heat treatment is performed. As a result, the first conductive region 51B made of a metal compound is formed in the remaining portion in the thickness direction of the region of the semiconductor layer outside the source portion 46. At the same time, the region of the semiconductor layer outside the drain portion 47 is formed. A second conductive region 52B made of a metal compound is formed in the remaining portion in the thickness direction.
[0091]
    (Example 3)
  Example 3Is a modification of the first embodiment.Example 3In[Step-A-80] of Reference Example 1Instead, the selective tungsten CVD method illustrated below is performed to replace the semiconductor layer 30 with a metal layer made of tungsten. As a result, a first conductive region made of metal is formed in the semiconductor layer outside the source portion, and a second conductive region made of metal is formed in the semiconductor layer outside the drain portion.
    Gas used: WF₆/ H₂/ SiH_Four= 10/500 / 10sccm
    Temperature: 260 ° C
    Pressure: 26.6Pa
[0092]
  The operation of executing the selective tungsten CVD method and replacing the semiconductor layer 30 with a metal layer made of tungsten is as follows.In the step corresponding to [Step-C-30] in Reference Example 3 and [Step-120] twice in Example 1 and Example 2It can also be applied.
[0093]
  The present invention has been described as a preferred embodiment.And reference examplesHowever, the present invention is not limited to these examples. ExampleAnd reference examplesThe various conditions described in the above are examples and can be changed as appropriate.
[0094]
  FIG.As shown in the schematic partial cross-sectional view of (A), the thickness of the semiconductor layer 30 in which the channel portion 45 is formed is set to be larger than the thickness of the semiconductor layer 30 in which the source portion 46 and the drain portion 47 are formed. It may be thinned. Accordingly, even when the semiconductor layer 30 is thinned, it is possible to prevent the conductive region from being lost by dry etching when the contact hole is formed, and to prevent an increase in contact resistance. To make such a structure,[Step-A-10] of Reference Example 1Similarly, first, the groove portion 20 is formed on one surface 10A of the first semiconductor substrate 10 (FIG.Next, after applying and drying a resist again on one surface 10A of the first semiconductor substrate 10, the resist is patterned using a photolithography technique. Next, the first semiconductor substrate 10 is etched using the patterned resist as a mask to form a recess in the semiconductor layer 30 in the region where the channel part is to be formed (FIG.(See (C)). The etching conditions can be the same as the groove formation conditions. As a result, finally above the recess (FIG.In (C), the channel portion 45 is formed (below the concave portion). The thickness of the semiconductor layer 30 in which the channel portion 45 is formed is equal to the thickness of the semiconductor layer 30 in which the source portion 46 and the drain portion 47 are formed. It can be made thinner than the thickness.
[0095]
  In the embodiments, the description has been made by taking a MOS transistor as an example as a transistor element. However, as other transistor elements, a bipolar transistor, a TFT, and a CCD can be cited. In addition to cobalt, examples of the transition metal constituting the metal layer include Ti, Ni, Mo, W, Cu, Zr, and Hf. Examples of the metal compound include TiW, TiN, TiB, and WB other than silicide. On the other hand, examples of the noble metal constituting the metal layer include Pt and Au. The second insulating layer is made of SiO₂In addition to the above, a known insulating material such as BPSG, PSG, BSG, AsSG, PbSG, SbSG, or SOG, or a laminate of these insulating layers can be used. The structure of the wiring layer is also an example, and can be changed as appropriate. The gate side wall 44 may not be provided depending on circumstances.
[0096]
【The invention's effect】
  Since the insulating layer made of a material that does not easily react with the metal elements constituting the first and second conductive regions is formed, it is effective that voids are generated in the formed first and second conductive regions. Can be suppressed.
[0097]
  In addition, in the transistor element of the present invention, since the first and second conductive regions are formed outside the source part and the drain part, the transistor element is in an on state and holes or electrons move in the semiconductor layer. In this case, silicon atoms in the region where holes or electrons move are ionized, but are absorbed by the first and second conductive regions from the channel portion via the source portion and the drain portion, and can be deposited on the channel portion. Absent. As a result, it is possible to avoid the problem that the breakdown voltage between the source part and the drain part occurs. In addition, since the first and second conductive regions are formed, the sheet resistance of the source and drain portions is 2 to 4 digits as compared with the conventional transistor element even if the semiconductor layer is thinned. The response speed of the transistor element can be improved.
[0098]
  Conventionally, as much as the design rule allows, the source / drain portion is made as large as possible, and the resistance value of the source / drain portion is kept low. When titanium silicide is formed, it is necessary to make the source / drain portions large enough not to cause a fine line effect. However, when cobalt silicide is used, the problem of the fine line effect can be avoided, so that the size of the source / drain portion can be reduced. As a result, the resistance value of the source / drain portion can be reduced and the MOS transistor can be reduced. The driving ability can be improved.
[Brief description of the drawings]
[Figure 1]Reference example 1It is a typical fragmentary sectional view of this transistor element.
[Figure 2]Reference example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 3 continues from FIG.Reference example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 4 continues from FIG.Reference example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 5 continues from FIG.Reference example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
[Fig. 6]Reference example 3FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 7 continues from FIG.Reference example 3FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 8 continues from FIG.Reference example 3FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 9 continues from FIG.Reference example 3FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 10Example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 11 continues from FIG.Example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 12 continues from FIG.Example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 13 continues from FIG.Example 1FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 14Example 2FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
FIG. 15 continues from FIG.Example 2FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like in each step for explaining a method for manufacturing the transistor element.
[FIG.]Reference example 1It is a typical partial cross section figure of the modification of this transistor element.
[FIG.FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method of manufacturing a MOS transistor using conventional SOI technology.
[FIG.]FIG.FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate and the like for explaining a method for manufacturing a MOS transistor using conventional SOI technology.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10,11 ... Silicon semiconductor substrate, 20 ... Groove part, 21, 21A ... Insulating layer, 22, 22A ... Second insulating layer, 23 ... Polysilicon layer, 30 ... Semiconductor Layer, 40 ... gate oxide film, 41 ... gate electrode part, 42 ... polysilicon film, 43 ... WSi₂Layer 44... Gate side wall 45. Channel part 46. Source part 47. Drain part 50 50 A 50 B metal layer 51 51 A 51 B 52. 52A, 52B ... conductive region, 60 ... interlayer insulating layer, 61 ... opening, 62 ... metal wiring material layer, 120 ... element isolation region

Claims (23)

(A) After forming a groove in the first semiconductor substrate, filling the groove with an insulating material, and forming an element isolation region,
(B) A part of the first conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the source part is to be formed and in the thickness direction from the surface. In addition, a part of the second conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the drain part is to be formed and in the thickness direction from the surface. And then
(C) An insulating layer made of silicon nitride or silicon oxynitride is formed on the entire surface, and then
(D) The first semiconductor substrate is bonded to the second semiconductor substrate through the insulating layer, and then polished from the back surface of the first semiconductor substrate, and the bottom of the groove formed in the first semiconductor substrate After exposing
(E) The remaining portion of the region outside the first semiconductor substrate region where the source portion is to be formed, in which the first conductive region has already been formed, is made of a metal or metal compound. In addition to the first conductive region, a region outside the region of the first semiconductor substrate where the drain portion is to be formed, the second conductive region below the region where the second conductive region has already been formed Forming a second conductive region of metal or metal compound, then
(F) forming a gate electrode portion on the exposed region of the first semiconductor substrate, and then forming a source portion and a drain portion in the exposed region of the first semiconductor substrate;
A method for manufacturing a transistor element.   In the step (b), a metal layer made of an element that reacts with an element constituting the first semiconductor substrate is formed on the surface of a region outside the region of the first semiconductor substrate where the source part and the drain part are to be formed. After the formation, heat treatment is performed to react the element constituting the metal layer with the element constituting the first semiconductor substrate, thereby forming the first conductive region and the second conductive region made of the metal compound. The method for manufacturing a transistor element according to claim 1, comprising the steps of: The metal layer is made of transition metal or noble metal,
The step (b)
(A) The transition metal which forms the metal layer with the oxide which comprises the element which comprises the element which comprises the 1st semiconductor substrate, and the transition metal or noble metal which comprises the metal layer reacts, and comprises the 1st semiconductor substrate Alternatively, a first heat treatment is performed to react an element constituting the metal layer and an element constituting the first semiconductor substrate at a temperature at which the noble metal does not react, and then
(B) After removing the unreacted metal layer,
(C) Further, a second heat treatment is performed to react an element constituting the metal layer with an element constituting the first semiconductor substrate.
3. The method of manufacturing a transistor element according to claim 2, comprising a process.   3. The method for manufacturing a transistor element according to claim 2, wherein the metal compound is made of silicide.   5. The method of manufacturing a transistor element according to claim 4, wherein the metal layer is mainly made of cobalt, and the silicide is mainly made of cobalt silicide.   In the step (e), a metal layer made of an element that reacts with an element constituting the first semiconductor substrate is formed on an exposed surface of a region outside the region of the first semiconductor substrate where the source part and the drain part are to be formed. Then, heat treatment is performed to react the element constituting the metal layer with the element constituting the first semiconductor substrate, thereby forming the first conductive region and the second conductive region made of the metal compound. The method for manufacturing a transistor element according to claim 1, comprising forming the transistor element. The metal layer is made of transition metal or noble metal,
The step (e)
(A) The transition metal which forms the metal layer with the oxide which comprises the element which comprises the element which comprises the 1st semiconductor substrate, and the transition metal or noble metal which comprises the metal layer reacts, and comprises the 1st semiconductor substrate Alternatively, a first heat treatment is performed to react an element constituting the metal layer and an element constituting the first semiconductor substrate at a temperature at which the noble metal does not react, and then
(B) After removing the unreacted metal layer,
(C) Further, a second heat treatment is performed to react an element constituting the metal layer with an element constituting the first semiconductor substrate.
The method of manufacturing a transistor element according to claim 6, comprising a process.   The method for manufacturing a transistor element according to claim 6, wherein the metal compound is made of silicide.   9. The method of manufacturing a transistor element according to claim 8, wherein the metal layer is mainly made of cobalt, and the silicide is mainly made of cobalt silicide.   2. The method for manufacturing a transistor element according to claim 1, further comprising a step of forming a gate sidewall made of an insulating material on a side wall of the gate electrode portion after the step (f).   In the step (b), a portion in the thickness direction from the surface of the region of the first semiconductor substrate where the source portion and the drain portion are to be formed is replaced with a metal layer by a CVD method, 2. The method of manufacturing a transistor element according to claim 1, further comprising a step of forming a part of the first conductive region and a part of the second conductive region made of metal. The step (e) is a region outside the region of the first semiconductor substrate where the source portion and the drain portion are to be formed by the CVD method, and the first conductive region and the second conductive region are already present below. 2. The method of claim 1, further comprising the step of replacing a remaining portion of the formed region with a metal layer, thereby forming a first conductive region and a second conductive region made of metal. A method for manufacturing a transistor element. (A) After forming a groove in the first semiconductor substrate, filling the groove with an insulating material, and forming an element isolation region,
(B) A part of the first conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the source part is to be formed and in the thickness direction from the surface. In addition, a part of the second conductive region made of a metal or a metal compound is formed in a region outside the region of the first semiconductor substrate where the drain part is to be formed and in the thickness direction from the surface. And then
(C) An insulating layer made of silicon nitride or silicon oxynitride is formed on the entire surface, and then
(D) The first semiconductor substrate is bonded to the second semiconductor substrate through the insulating layer, and then polished from the back surface of the first semiconductor substrate, and the bottom of the groove formed in the first semiconductor substrate After exposing
(E) forming a gate electrode portion on the exposed region of the first semiconductor substrate, then forming a source portion and a drain portion in the exposed region of the first semiconductor substrate, and then insulating the sidewall of the gate electrode portion; Forming a gate sidewall made of material, then
(F) A region made of metal or a metal compound is formed in the remaining portion of the region outside the region of the first semiconductor substrate in which the source portion is to be formed, where the first conductive region has already been formed below. 1 is formed in the remaining region of the region where the second conductive region is already formed below the region of the first semiconductor substrate where the drain portion is to be formed. Forming a second conductive region of metal or metal compound;
A method for manufacturing a transistor element.   In the step (b), a metal layer made of an element that reacts with an element constituting the first semiconductor substrate is formed on the surface of a region outside the region of the first semiconductor substrate where the source part and the drain part are to be formed. After the formation, heat treatment is performed to react the element constituting the metal layer with the element constituting the first semiconductor substrate, thereby forming the first conductive region and the second conductive region made of the metal compound. The method for manufacturing a transistor element according to claim 13, comprising the steps of: The metal layer is made of transition metal or noble metal,
The step (b)
(A) The transition metal which forms the metal layer with the oxide which comprises the element which comprises the element which comprises the 1st semiconductor substrate, and the transition metal or noble metal which comprises the metal layer reacts, and comprises the 1st semiconductor substrate Alternatively, a first heat treatment is performed to react an element constituting the metal layer and an element constituting the first semiconductor substrate at a temperature at which the noble metal does not react, and then
(B) After removing the unreacted metal layer,
(C) Further, a second heat treatment is performed to react an element constituting the metal layer with an element constituting the first semiconductor substrate.
The method of manufacturing a transistor element according to claim 14, comprising a process.   15. The method for manufacturing a transistor element according to claim 14, wherein the metal compound is made of silicide.   17. The method for manufacturing a transistor element according to claim 16, wherein the metal layer is mainly made of cobalt, and the silicide is mainly made of cobalt silicide.   In the step (f), a metal layer made of an element that reacts with an element constituting the first semiconductor substrate is formed on an exposed surface of a region outside the region of the first semiconductor substrate where the source part and the drain part are to be formed. Then, heat treatment is performed to react the element constituting the metal layer with the element constituting the first semiconductor substrate, thereby forming the first conductive region and the second conductive region made of the metal compound. The method for manufacturing a transistor element according to claim 13, comprising a forming step. The metal layer is made of transition metal or noble metal,
The step (f)
(A) The transition metal which forms the metal layer with the oxide which comprises the element which comprises the element which comprises the 1st semiconductor substrate, and the transition metal or noble metal which comprises the metal layer reacts, and comprises the 1st semiconductor substrate Alternatively, a first heat treatment is performed to react an element constituting the metal layer and an element constituting the first semiconductor substrate at a temperature at which the noble metal does not react, and then
(B) After removing the unreacted metal layer,
(C) Further, a second heat treatment is performed to react an element constituting the metal layer with an element constituting the first semiconductor substrate.
The method for manufacturing a transistor element according to claim 18, comprising a process.   19. The method for manufacturing a transistor element according to claim 18, wherein the metal compound is made of silicide.   21. The method of manufacturing a transistor element according to claim 20, wherein the metal layer is mainly made of cobalt, and the silicide is mainly made of cobalt silicide.   In the step (b), a portion in the thickness direction from the surface of the region of the first semiconductor substrate where the source portion and the drain portion are to be formed is replaced with a metal layer by a CVD method, 14. The method of manufacturing a transistor element according to claim 13, further comprising forming a part of the first conductive region and a part of the second conductive region made of metal. In the step (f), the first conductive region and the second conductive region are already formed below the region of the first semiconductor substrate where the source and drain portions are to be formed by CVD. 14. The transistor of claim 13, comprising the step of replacing the remaining portion of the formed region with a metal layer, thereby forming a first conductive region and a second conductive region made of metal. A method for manufacturing the element.

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