JP2007019205A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a uniform silicide layer without the abnormal growth of a nickel silicide in a semiconductor device formed with a nickel silicide layer. <P>SOLUTION: A semiconductor device manufacturing method is provided with a process for forming a gate electrode on a silicone substrate, a process for forming side walls on both sides of the gate electrode, and a process for forming a silicide region on the silicon substrate. A reaction inhibition layer of silicification is formed in a surface region of the silicone substrate below the side walls before the formation process of the silicide region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a silicided region (silicide region), and more particularly to a method of manufacturing a semiconductor device having nickel silicide and a semiconductor device manufactured by the method.

  Conventionally, in order to increase the speed of a semiconductor integrated circuit, a technique for reducing wiring resistance by siliciding an element region has been used. Tungsten silicide, molybdenum silicide, etc. using CVD method or sputtering method were used, but the salicide method, which can form silicide in a self-aligned manner with the progress of miniaturization of semiconductor elements, is a common silicide formation today. It has become a method. In this method, after a metal such as titanium or cobalt is formed on the entire surface of the wafer, a silicidation reaction is performed by performing a first heat treatment. Then, after removing the remaining metal without reacting with the portion other than the polysilicon of the electrode and the silicon substrate region of the element using a chemical solution, the resistance of the silicide is reduced by subsequently performing a heat treatment. . By using this method, the metal silicide can be formed in a self-aligned manner only in the polysilicon of the electrode and the silicon substrate region of the element. Recently, along with miniaturization of semiconductor elements, nickel silicide, which can obtain low resistance at a lower temperature, has been used instead of titanium and cobalt.

  In addition, when an analog resistance element is formed as a semiconductor element, the specific resistance of the silicide layer is very small for use as a resistance element. Therefore, when a resistance element is used, only a specific element region used as the resistance element is used. A method is used in which no silicidation is performed. Against this background, in recent years, by using a process in which a specific element region used as a resistance element is not silicided, the element region is used as a resistance element.

  A method for manufacturing a semiconductor device having a silicide region as described above is disclosed in Patent Document 1 (first conventional example). Hereinafter, an example of a conventional method for manufacturing a semiconductor device will be described with reference to FIG.

  First, as shown in FIG. 15A, a MOS transistor including a gate electrode 102 and sidewalls 103 formed on both sides thereof is formed on a silicon substrate 101 via a gate insulating film (not shown). Has been. Subsequently, a silicon oxide film 104 as an insulating film is deposited so as to cover the transistor formed on the silicon substrate 101.

  Subsequently, a resist pattern 105 is formed on the silicon oxide film 104 by lithography. Note that the resist pattern 105 is formed on the silicon oxide film 104 at a position that covers a region (non-salicide region) that does not require formation of a silicide layer, which will be described later, for use as the resistance element 106.

  Next, as shown in FIG. 15B, when the silicon oxide film 104 is etched by anisotropic ion etching, the silicon oxide film 104 other than the portion immediately below the resist pattern 105 is removed using the resist pattern 105 as a mask. .

  Subsequently, as shown in FIG. 15C, the resist pattern 105 is removed by a normal method. As a result, the silicon oxide film 104 for silicidation block is left only on a specific element region used as the resistance element 106.

  Next, as shown in FIG. 15D, when a refractory metal such as Ti (titanium), Co (cobalt), Ni (nickel) or the like is deposited by sputtering, the refractory metal is deposited on the entire surface of the silicon substrate 101. A film 107 is formed. Subsequently, when the silicon substrate 101 and the refractory metal film 107 are reacted by performing a silicidation annealing process by an appropriate heat treatment process, a silicide layer 108 is formed.

  In this silicidation annealing process, the side surface of the gate electrode 102 and the surface of a specific element region used as the resistance element 106 are covered with the sidewall 103 and the silicon oxide film 104, so that the silicon substrate 101 has a high melting point. Since the metal film 107 is not in contact, the silicide layer 108 is not formed on the side surface of the gate electrode 102 and a specific element region used as the resistance element 106.

  Next, as shown in FIG. 15E, after the unreacted refractory metal film 107 is removed by selective etching, a low resistance annealing treatment is performed. Through the above steps, the silicide layer 108 is formed on the surface of the source / drain layer (not shown) of the silicon substrate 101 on which the silicon oxide film 104 for silicidation block has not been formed. The resistive element 106 in the region is formed.

  By the way, when anisotropic etching is performed so as to form the silicon oxide film 104 for the silicidation block by the conventional technique as described above, the carbon and oxygen in the mixed gas used at that time are ionized. There is a problem that the wafer is driven into the silicon substrate 101 due to acceleration by self-bias of the wafer generated during etching.

  A damage layer containing carbon and oxygen is formed in the vicinity of the surface of the silicon substrate 101 due to such implantation of carbon and oxygen into the silicon substrate 101 or charging damage caused by plasma. It will be formed unevenly.

  Therefore, a method for forming a silicide layer that does not form the damaged layer is disclosed in Patent Document 2 (second conventional example). This is a method of reducing the amount of over-etching during etching by forming the insulating film for the silicidation block into two layers. In this method, etching for removing the second insulating film is performed by a RIE (Reactive Ion Etching) method, and the first insulating film is removed by wet etching. Hereinafter, a description will be given with reference to FIG.

  First, as shown in FIG. 16A, a MOS transistor including a gate electrode 202 and sidewalls 203 formed on both sides thereof is formed on a silicon substrate 201 via a gate insulating film (not shown). Has been. Subsequently, a silicon oxide film 204 as a first insulating film and a silicon nitride film 205 as a second insulating film are deposited so as to cover the transistor formed on the silicon substrate 201. Subsequently, a resist pattern 206 is formed on the silicon nitride film 205 by lithography. Note that the resist pattern 206 is formed on the silicon nitride film 205 at a position covering a region (non-salicide region) where a later-described silicide layer for use as the resistance element 207 is not required.

  Next, as shown in FIG. 16B, when only the silicon nitride film 205 is removed by anisotropic ion etching, the underlying silicon oxide film 204 is not removed, so that the surface of the silicon substrate 201 is exposed by RIE. There is no damage.

  Subsequently, using the resist pattern 206 and the silicon nitride film 205 as a mask, the silicon oxide film 204 is removed by wet etching. At this time, hydrogen fluoride is mainly used for wet etching of the silicon oxide film 204. As a result, the silicon nitride film 205 and the silicon oxide film 204 for silicidation block are formed only on a specific element region used as the resistance element 207.

  Next, as shown in FIG. 16C, the resist pattern 206 is removed by a normal method. Thereafter, as shown in FIGS. 16D to 16E, a refractory metal film 208 is deposited by an ordinary method, and then a silicide layer 209 is formed.

  By the way, when the insulating film for the silicidation block as described above is formed in two layers, the damage layer to the silicon substrate 201 by anisotropic etching can be reduced, but depending on the film thickness of the silicon oxide film 204, silicon When the nitride film 205 is dry-etched by RIE, the silicon oxide film 204 is pierced to damage the silicon substrate 201, or a thin oxide film or resist residue is also formed in a portion where the silicide layer 209 is formed by a residue of the resist pattern 206 or the like. There was a problem that remained.

  If such a non-uniform resist residue or oxide film residue is present on the surface of the silicon substrate 201, the silicide layer 209 is formed non-uniformly.

Furthermore, in the formation of silicide such as titanium and cobalt, a clean and uniform silicon surface of a silicon substrate can be obtained by performing reverse sputtering using Ar gas before sputtering titanium or cobalt. In reverse sputtering using Ar gas, non-uniform silicide is formed, and Ar reverse sputtering cannot be used. For this reason, in the silicide formation of nickel, it is suggested that the silicidation reaction is affected by a trace amount of oxygen, carbon, nitrogen, fluorine and the like on the substrate surface.
Japanese Patent Application Laid-Open No. 11-097649 JP 2004-146616 A

  As described above, in the first conventional example, the silicidation reaction at the interface between the refractory metal film and the silicon substrate is locally inhibited by the carbon and oxygen implanted into the silicon substrate, and as a result, There was a problem that the silicidation reaction did not proceed sufficiently. Also in the second conventional example, although the damage layer to the silicon substrate due to etching can be reduced, depending on the thickness of the silicon oxide film, the silicon oxide film is broken through the silicon oxide film during dry etching by RIE of the silicon nitride film. There is a problem that a thin oxide film or a resist residue remains in a portion where a silicide region is to be formed due to damage or a resist film residue.

  The non-uniformity of these silicidation reactions is not only a problem that silicidation does not proceed, but also when a part where silicidation is likely to proceed and a part where it is difficult to proceed coexist, it is a portion where silicidation is likely to proceed. A silicidation reaction occurs. At this time, as shown in FIG. 17, the abnormally grown silicide layer 109 proceeds under the sidewall 103, part of the silicide layer 109 reaches under the gate electrode 102, or breaks through the source / drain layer (not shown). , Causing an increase in leakage current to the silicon substrate and an increase in leakage current between the source and drain, degrading the characteristics of the transistors formed on the silicon substrate as a logic circuit, resulting in a decrease in the performance of the logic LSI, It has caused a drop in quality.

  The present invention has been made in order to solve the above-described problems. The interface between a refractory metal film and a silicon substrate, such as carbon and oxygen implanted in the silicon substrate, or an organic substance due to a resist residue on the substrate surface. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the problem that the silicidation reaction is locally inhibited and the silicidation reaction does not proceed sufficiently.

  The inventors of the present invention have found that, in addition to carbon and oxygen, fluorine and nitrogen similarly inhibit silicidation reaction as non-uniform silicide formation in the case of nickel. Nickel was deposited on the silicon substrate implanted with these elements, and the temperature at which the silicidation reaction occurred was investigated in detail. As a result, it was found that the nickel silicidation reaction was slow in any of the substrates implanted with any element. It was also found that with the miniaturization of the device, the resist film embedded in the fine element portion could not be sufficiently removed even if the resist was removed, and a part remained as a residue.

  The present invention has been made in view of these results, and a first semiconductor device according to the present invention includes a gate electrode formed on a silicon substrate and a gate electrode in a semiconductor device having an insulated gate transistor. Sidewalls formed on both sides and silicide regions formed on the silicon substrate are included, and the surface region of the silicon substrate below the sidewalls includes an element that inhibits silicidation reaction.

  According to the above configuration, the presence of an element that inhibits the silicidation reaction in the portion under the sidewall can suppress a rapid silicidation reaction that proceeds to the surface region under the sidewall.

  A second semiconductor device according to the present invention is a semiconductor device having an insulated gate transistor, wherein a gate electrode formed on a silicon substrate, sidewalls formed on both sides of the gate electrode, and an upper portion of the silicon substrate And a silicide region formed on the source / drain layer, and the source / drain layer contains an element that inhibits a silicidation reaction.

  According to the above configuration, the presence of an element that inhibits the silicidation reaction in the portion of the source / drain layer can suppress a rapid silicidation reaction that proceeds to the bottom of the source / drain layer.

  In the above configuration, the element that inhibits the silicidation reaction is preferably composed of one or more elements of carbon, nitrogen, fluorine, and oxygen.

  The first method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having an insulated gate transistor, wherein a step of forming a gate electrode on a silicon substrate and a side wall are formed on both sides of the gate electrode. And forming a silicide region on the silicon substrate, and forming a silicidation reaction inhibition layer on the surface region of the silicon substrate below the sidewall before the silicide region forming step. To do.

  According to the above configuration, by forming the silicidation reaction inhibition layer in the surface region under the sidewall, it is possible to suppress a rapid silicidation reaction proceeding to the surface region under the sidewall.

  In the above configuration, the reaction inhibition layer is preferably formed by injecting an element that inhibits the silicidation reaction into the surface region of the silicon substrate before the sidewall formation step.

  In the above configuration, the reaction inhibition layer is preferably formed by rotationally injecting an element that inhibits the silicidation reaction into the surface region of the silicon substrate after the sidewall formation step.

  In the above configuration, the element that inhibits the silicidation reaction is preferably composed of one or more elements of carbon, nitrogen, fluorine, and oxygen.

  The second method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having an insulated gate transistor, wherein a step of forming a gate electrode on a silicon substrate and a side wall are formed on both sides of the gate electrode. A step of forming a source / drain layer on the silicon substrate, and a step of forming a silicide region on the source / drain layer. Before the step of forming the silicide region, a region of the source / drain layer is provided. And a silicidation reaction inhibition layer is formed.

  According to the above configuration, by forming the silicidation reaction inhibition layer in the source / drain layer portion, it is possible to suppress a rapid silicidation reaction proceeding to the bottom of the source / drain layer.

  In the above configuration, in the step of forming the source / drain layer, the reaction inhibition layer is preferably formed by implanting an element that inhibits the silicidation reaction after the source / drain implantation.

  In the above configuration, the silicide region forming step further includes a step of forming a refractory metal film on the silicon substrate and a step of reacting the silicon substrate with the refractory metal film, wherein the reaction inhibition layer has a high melting point. It is preferable to form the source / drain layer by injecting an element that inhibits the silicidation reaction before the metal film forming step.

  In the above configuration, the element that inhibits the silicidation reaction is preferably composed of one or more elements of carbon, nitrogen, fluorine, and oxygen.

  In the above configuration, the silicide region forming step further includes a step of forming a refractory metal film on the silicon substrate and a step of reacting the silicon substrate with the refractory metal film, wherein the reaction inhibition layer has a high melting point. Prior to the metal film formation step, the source / drain layer is preferably formed by plasma irradiation in a gas containing an element that inhibits the silicidation reaction.

In the above configuration, the gas containing an element that inhibits the silicidation reaction is preferably composed of one or more of CxFy, NF ₃ , NOx, and COx.

  The third method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having an insulated gate transistor, wherein a step of forming a gate electrode on a silicon substrate and sidewalls on both sides of the gate electrode are formed. A step of forming a source / drain layer on the silicon substrate, a step of forming a refractory metal film on the silicon substrate, a reaction between the silicon substrate and the refractory metal film, and And a step of forming a silicide region, and before the step of forming the refractory metal film, the surface of the silicon substrate is subjected to plasma irradiation in a mixed gas of fluorine-containing gas and oxygen gas.

In the above configuration, the gas containing fluorine is preferably CHF ₃ or CxFy having a high C / F ratio.

  According to the above configuration, by depositing carbon on the surface of the silicon substrate, a rapid silicidation reaction that progresses to the bottom of the source / drain layer can be suppressed and the silicidation can be uniformly reacted.

In the above configuration, the gas containing fluorine is preferably CxFy or NF ₃ .

  According to the above configuration, the abrupt silicidation reaction that proceeds to the bottom of the source / drain layer by removing the resist residue remaining on the surface of the silicon substrate and the carbon contained in the atmosphere attached to the substrate surface. And silicidation can be made to react uniformly.

  According to the present invention, a rapid silicidation reaction that progresses locally, such as the substrate region under the sidewall and the source / drain layer, is suppressed, and a uniform silicide layer is formed. Or break through the source / drain layer. As a result, the leakage current to the silicon substrate and the leakage current between the source and drain do not increase, so that the performance, yield and reliability of the system LSI can be improved.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to each embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
One embodiment which is the 1st invention of the present invention is shown. 1 to 2 are sectional views showing a manufacturing process for forming the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a main part of the semiconductor device.

  First, as shown in FIG. 1A, a gate electrode 12 is formed in an element region on a silicon substrate 11 via a gate insulating film (not shown).

Next, as shown in FIG. 1B, carbon is ion-implanted into the surface of the silicon substrate 11 with an acceleration energy of 3 keV and an injection amount of 3E14 atoms / cm ² . At this time, the source / drain implantation of the extension is performed at the same time. However, it is desirable that the carbon implantation is performed after the source / drain implantation of the extension so that the carbon is uniformly diffused. Thereafter, annealing is performed at 900 ° C.

  Next, as shown in FIG. 1C, sidewalls 13 made of a multilayer insulating film are formed. The sidewall 13 may have a single layer structure.

  Next, as shown in FIG. 1D, after performing source / drain implantation so as to form a normal element, activation annealing of a source / drain layer (not shown) is performed at 1050.degree.

  Next, as shown in FIG. 1E, a silicon oxide film 14 as an insulating film is deposited so as to cover the transistor formed on the silicon substrate 11.

  Next, as shown in FIG. 2A, a resist pattern 15 is formed on the silicon oxide film 14 by lithography. The resist pattern 15 is formed on the silicon oxide film 14 at a position covering a region (non-salicide region) that does not require formation of a silicide layer, which will be described later, for use as the resistance element 16.

  Next, as shown in FIG. 2B, when the silicon oxide film 14 is etched by anisotropic ion etching, the silicon oxide film 14 other than the portion immediately below the resist pattern 15 is removed using the resist pattern 15 as a mask. .

  Subsequently, as shown in FIG. 2C, the resist pattern 15 is removed by a normal method. As a result, the silicon oxide film 14 for silicidation block is left only on a specific element region used as the resistance element 16.

  Next, as shown in FIG. 2D, when a refractory metal such as Ni (nickel) is deposited by sputtering to a thickness of 10 nm, a refractory metal film 17 is formed on the entire surface of the silicon substrate 11. . Subsequently, when a silicon substrate 11 and the refractory metal film 17 are reacted by performing a heat treatment at 300 ° C. as a silicidation annealing process, a silicide layer 18 is formed.

  In this silicidation annealing process, the side surface of the gate electrode 12 and the surface of a specific element region used as the resistance element 16 are covered with the side wall 13 and the silicon oxide film 14, so that the silicon substrate 11 and the high melting point are high. Since the metal film 17 is not in contact, the silicide layer 18 is not formed on the side surface of the gate electrode 13 and the specific element region used as the resistance element 16.

  Next, as shown in FIG. 2E, after the unreacted refractory metal film 17 is removed by selective etching, a low resistance annealing treatment is performed. Through the above steps, the silicide layer 18 is formed on the surface of the source / drain layer (not shown) of the silicon substrate 11 where the silicon oxide film 14 for silicidation block is not formed, and the surface region under the sidewall 13 is formed. A uniform nickel silicide that does not grow abnormally is formed.

  In the present embodiment, the case where carbon atoms are implanted has been described. However, the present invention is not limited to this, and similar effects can be obtained with fluorine, nitrogen, and oxygen. Moreover, although the case where nickel silicide was formed was demonstrated, the same effect is acquired not only by this but silicide, such as titanium and cobalt.

  As described above, the semiconductor device formed by the manufacturing method according to the present embodiment includes a gate electrode 12 formed on the silicon substrate 11 and a gate in a semiconductor device having an insulated gate transistor as shown in FIG. A side wall 13 formed on both sides of the electrode 12 and a silicide region (not shown) formed on the silicon substrate 11 are provided, and the silicidation reaction is inhibited in the surface region of the silicon substrate 11 below the side wall 13. A silicidation reaction inhibition layer 19 containing one or more elements of carbon, nitrogen, fluorine, and oxygen as elements is formed. Thus, by making the above-described elements exist in the portion under the sidewall (providing the reaction inhibition layer 19), a rapid silicidation reaction that proceeds to the surface region under the sidewall can be suppressed.

(Modification of the first embodiment)
In the semiconductor device of the first embodiment, the implantation of an element such as carbon under the sidewall can also be realized by the following manufacturing method. 4 to 5 are cross-sectional views illustrating manufacturing steps for forming a semiconductor device according to a modification of the first embodiment.

  First, as shown in FIG. 4A, the gate electrode 22 is formed in the element region on the silicon substrate 21. Next, as shown in FIG. 4B, sidewalls 23 made of a multilayer insulating film are formed.

Next, as shown in FIG. 4 (c), the acceleration energy 3keV ion implantation of carbon, so that the injection amount 3E14atoms / cm ^2, performing angle implant at an angle of 45 degrees. At this time, in consideration of the gate electrode 22, if rotation injection is performed four or more times, carbon can be injected under the sidewall 23 so as to reduce the non-objectivity.

  Next, as shown in FIG. 4D, after performing source / drain implantation by a normal method, activation annealing of the source / drain layer (not shown) is performed at 1050.degree.

  Next, as shown in FIG. 4E, a silicon oxide film 24 as an insulating film is deposited so as to cover the transistor formed on the silicon substrate 21.

  Next, as shown in FIG. 5A, a resist pattern 25 is formed on the silicon oxide film 24 by lithography. Note that the resist pattern 25 is formed on the silicon oxide film 24 at a position covering a region (non-salicide region) where a later-described silicide layer for use as the resistance element 26 is not required.

  Next, as shown in FIG. 5B, the silicon oxide film 24 is etched by anisotropic ion etching, and the silicon oxide film 24 other than the portion immediately below the resist pattern 25 is removed as a mask. .

  Subsequently, as shown in FIG. 5C, the resist pattern 25 is removed by a normal method. As a result, the silicon oxide film 24 for silicidation block is left only on a specific element region used as the resistance element 26.

  Next, as shown in FIG. 5D, when a refractory metal such as Ni (nickel) is deposited by sputtering to a thickness of 10 nm, a refractory metal film 27 is formed on the entire surface of the silicon substrate 21. . Subsequently, when the silicon substrate 21 and the refractory metal film 27 are reacted by performing a heat treatment at 300 ° C. as a silicidation annealing process, a silicide layer 28 is formed.

  Next, as shown in FIG. 5E, after the unreacted refractory metal film 27 is removed by selective etching, a low resistance annealing treatment is performed. Through the above steps, the silicide layer 28 is formed on the surface of the source / drain layer (not shown) of the silicon substrate 21 where the silicon oxide film 24 for silicidation block is not formed, and the surface region under the sidewall 23 is formed. A uniform nickel silicide that does not grow abnormally is formed.

(Second Embodiment)
One embodiment which is the 2nd invention of the present invention is shown. 6 to 7 are cross-sectional views illustrating manufacturing steps for forming the semiconductor device according to the second embodiment. FIG. 8 is a cross-sectional view showing a main part of the semiconductor device.

  First, as shown in FIG. 6A, the gate electrode 32 is formed on the element region of the silicon substrate 31 through a gate insulating film (not shown). Next, as shown in FIG. 6B, a sidewall 33 made of a multilayer insulating film is formed.

Next, as shown in FIG. 6C, source / drain implantation is performed by a normal method. Next, as shown in FIG. 6 (d), after implanting carbon ions at an acceleration energy of 3 keV and an implantation amount of 8E14 atoms / cm ² , source / drain layers (not shown) The activation annealing is performed at 1050 ° C.

  Next, as shown in FIG. 6E, a silicon oxide film 34 as an insulating film is deposited so as to cover the transistor formed on the silicon substrate 31.

  Next, as shown in FIG. 7A, a resist pattern 35 is formed on the silicon oxide film 34 by lithography. Note that the resist pattern 35 is formed on the silicon oxide film 34 at a position covering a region (non-salicide region) where a later-described silicide layer for use as the resistance element 36 is not required.

  Next, as shown in FIG. 7B, the silicon oxide film 34 is etched by anisotropic ion etching, and the silicon oxide film 34 other than the portion immediately below the resist pattern 35 is removed using the resist pattern 35 as a mask. .

  Subsequently, as shown in FIG. 7C, the resist pattern 35 is removed by a normal method. As a result, the silicon oxide film 34 for silicidation block is left only on a specific element region used as the resistance element 36.

  Next, as shown in FIG. 7D, when a refractory metal such as Ni (nickel) is deposited by sputtering to a thickness of 10 nm, a refractory metal film 37 is formed on the entire surface of the silicon substrate 11. . Subsequently, when a silicon substrate 31 and the refractory metal film 37 are reacted by performing a heat treatment at 350 ° C. as a silicidation annealing process, a silicide layer 38 is formed.

  In this silicidation annealing process, the silicide layer 38 can be normally formed even in the source / drain layer (not shown) into which carbon has been implanted by raising the processing temperature. Further, since the side surface of the gate electrode 32 and the surface of a specific element region used as the resistance element 36 are covered with the sidewall 33 and the silicon oxide film 34, the silicon substrate 31 and the refractory metal film 37 do not contact each other. Therefore, the silicide layer 38 is not formed on the side surface of the gate electrode 32 and the specific element region used as the resistance element 36.

  Next, as shown in FIG. 7E, after the unreacted refractory metal film 37 is removed by selective etching, a low resistance annealing treatment is performed. Through the above steps, the silicide layer 38 is formed on the surface of the source / drain layer (not shown) of the silicon substrate 31 where the silicon oxide film 34 for silicidation block is not formed, and the bottom of the source / drain layer is formed. Uniform nickel silicide that does not grow abnormally is formed.

  In the present embodiment, the case where carbon atoms are ion-implanted has been described. Moreover, although the case where nickel silicide was formed was demonstrated, the same effect is acquired not only by this but silicide, such as titanium and cobalt.

  As described above, the semiconductor device formed by the manufacturing method according to the present embodiment includes a gate electrode 32 formed on the silicon substrate 31 and a gate in the semiconductor device having an insulated gate transistor as shown in FIG. Side walls 33 formed on both sides of the electrode 32, source / drain layers (not shown) formed on the silicon substrate 31, and silicide regions (not shown) formed on the source / drain layers. And a silicidation reaction inhibiting layer 39 containing at least one element of carbon, nitrogen, fluorine, and oxygen as an element inhibiting the silicidation reaction is formed in the source / drain layer. As described above, by making the above-described element exist in the source / drain layer portion (providing the reaction inhibition layer 39), it is possible to suppress a rapid silicidation reaction proceeding to the bottom of the source / drain layer.

(Modification of the second embodiment)
In the semiconductor device of the second embodiment, the implantation of an element such as carbon into the source / drain layer can also be realized by the following manufacturing method. 9 to 10 are cross-sectional views showing a manufacturing process for forming a semiconductor device according to a modification of the second embodiment.

  First, as shown in FIG. 9A, the gate electrode 42 is formed on the element region of the silicon substrate 41 via a gate insulating film (not shown). Next, as shown in FIG. 9B, sidewalls 43 made of a multilayer insulating film are formed.

  Next, as shown in FIG. 9C, after performing source / drain implantation by a normal method, activation annealing of the source / drain layer (not shown) is performed at 1050.degree.

  Next, as shown in FIG. 9D, a silicon oxide film 44 as an insulating film is deposited so as to cover the transistor formed on the silicon substrate 41.

  Next, as shown in FIG. 10A, a resist pattern 45 is formed on the silicon oxide film 44 by lithography. The resist pattern 45 is formed on the silicon oxide film 44 at a position that covers a region (non-salicide region) that does not require formation of a silicide layer, which will be described later, for use as the resistance element 46.

  Next, as shown in FIG. 10B, the silicon oxide film 44 is etched by anisotropic ion etching, and the silicon oxide film 44 other than the portion immediately below the resist pattern 45 is removed using the resist pattern 45 as a mask. .

Subsequently, as shown in FIG. 10C, the resist pattern 45 is removed by a normal method. As a result, the silicon oxide film 44 for silicidation block is left only on a specific element region used as the resistance element 46. Next, carbon ion implantation is performed at 0 degree so that the acceleration energy is 3 keV and the implantation amount is 8E14 atoms / cm ² .

  Next, as shown in FIG. 10D, when a refractory metal such as Ni (nickel) is deposited by sputtering to a thickness of 10 nm, a refractory metal film 47 is formed on the entire surface of the silicon substrate 41. . Subsequently, when the silicon substrate 41 and the refractory metal film 47 are reacted by performing a heat treatment at 350 ° C. as a silicidation annealing process, a silicide layer 48 is formed.

  In this silicidation annealing process, the silicide layer 48 can be normally formed even in the source / drain layer (not shown) into which carbon has been implanted by raising the processing temperature.

  Next, as shown in FIG. 10E, after the unreacted refractory metal film 47 is removed by selective etching, a low resistance annealing treatment is performed. Through the above steps, the silicide layer 48 is formed on the surface of the source / drain layer (not shown) of the silicon substrate 41 where the silicon oxide film 44 for silicidation block is not formed, and the bottom of the source / drain layer is formed. Uniform nickel silicide that does not grow abnormally is formed.

In this embodiment, the case where carbon atoms are ion-implanted has been described. Instead, for example, carbon is introduced into the surface of the source / drain layer by performing plasma irradiation in a CF-based gas. You can also. Similar effects can be obtained by introducing fluorine, nitrogen, or oxygen using a gas such as NF ₃ , NOx, or COx instead of introducing carbon.

(Third embodiment)
One embodiment which is the 3rd invention of the present invention is shown. 11 to 12 are cross-sectional views illustrating manufacturing steps for forming the semiconductor device according to the third embodiment.

  First, as shown in FIG. 11A, a gate electrode 52 is formed on an element region of a silicon substrate 51 via a gate insulating film (not shown). Next, as shown in FIG. 11B, a sidewall 53 made of a multilayer insulating film is formed.

  Next, as shown in FIG. 11C, after performing source / drain implantation by a normal method, activation annealing of the source / drain layer (not shown) is performed at 1050.degree.

  Next, as shown in FIG. 11D, a silicon oxide film 54 as an insulating film is deposited so as to cover the transistor formed on the silicon substrate 51.

  Next, as shown in FIG. 12A, a resist pattern 55 is formed on the silicon oxide film 54 by lithography. Note that the resist pattern 55 is formed on the silicon oxide film 54 at a position covering a region (non-salicide region) where a later-described silicide layer for use as the resistance element 56 is not required.

  Next, as shown in FIG. 12B, the silicon oxide film 54 is etched by anisotropic ion etching, and the silicon oxide film 54 other than the portion immediately below the resist pattern 55 is removed using the resist pattern 55 as a mask. .

Subsequently, as shown in FIG. 12C, the resist pattern 55 is removed by a normal method. As a result, the silicon oxide film 54 for silicidation block is left only on a specific element region used as the resistance element 56. Then, a mixed gas containing _{O 2} of CHF ₃ and the flow rate 30sccm flow 3 sccm, using a 13.56MHz high-frequency power source, the power 3 kW, the plasma irradiation of 15 seconds at a substrate temperature of 100 ° C., Carbon is deposited on the surface of the silicon substrate 51 in the element region other than that covered with the silicon oxide film 54.

  Next, as shown in FIG. 12D, when a refractory metal such as Ni (nickel) is deposited by sputtering to a thickness of 10 nm, a refractory metal film 57 is formed on the entire surface of the silicon substrate 51. . Subsequently, when the silicon substrate 51 and the refractory metal film 57 are reacted by performing a heat treatment at 350 ° C. as a silicidation annealing process, a silicide layer 58 is formed.

  In this silicidation annealing process, the silicide layer 58 can be normally formed even in the source / drain layer (not shown) on which carbon is deposited by raising the processing temperature.

  Next, as shown in FIG. 12E, after the unreacted refractory metal film 57 is removed by selective etching, a low resistance annealing treatment is performed. Through the above steps, the silicide layer 58 is formed on the surface of the source / drain layer (not shown) of the silicon substrate 51 where the silicon oxide film 54 for silicidation block is not formed, and the bottom of the source / drain layer is formed. Uniform nickel silicide that does not grow abnormally is formed.

In the present embodiment has described the case of depositing carbon using CHF ₃ gas, the same effect can be obtained by CxFy gas such as high C / F ratio C ₄ F ₈ is not limited thereto.

(Fourth embodiment)
An embodiment which is the fourth invention of the present invention will be described. 13 to 14 are cross-sectional views illustrating manufacturing steps for forming the semiconductor device according to the fourth embodiment.

  First, as shown in FIG. 13A, the gate electrode 62 is formed on the element region of the silicon substrate 61 through a gate insulating film (not shown). Next, as shown in FIG. 13B, a sidewall 63 made of a multilayer insulating film is formed.

  Next, as shown in FIG. 13C, after performing source / drain implantation by a normal method, activation annealing of the source / drain layer (not shown) is performed at 1050.degree.

  Next, as shown in FIG. 13D, a silicon oxide film 64 as an insulating film is deposited so as to cover the transistor formed on the silicon substrate 61.

  Next, as shown in FIG. 14A, a resist pattern 65 is formed on the silicon oxide film 64 by lithography. Note that the resist pattern 65 is formed on the silicon oxide film 64 at a position that covers a region (non-salicide region) that does not require formation of a silicide layer, which will be described later, for use as the resistance element 66.

  Next, as shown in FIG. 14B, the silicon oxide film 64 is etched by anisotropic ion etching, and the silicon oxide film 64 other than the portion immediately below the resist pattern 65 is removed using the resist pattern 65 as a mask. .

Subsequently, as shown in FIG. 14C, the resist pattern 65 is removed by a normal method. As a result, the silicon oxide film 64 for silicidation block is left only on a specific element region used as the resistance element 66. Next, using a mixed gas containing CF ₄ with a flow rate of 3 sccm and O ₂ with a flow rate of 30 sccm, using a 13.56 MHz high-frequency power source, and performing plasma irradiation for 30 seconds under conditions of a power of 1 kW and a substrate temperature of 100 ° C., Resist residues remaining on the surface of the silicon substrate 61 and carbon contained in the atmosphere attached to the substrate surface are removed.

  Next, as shown in FIG. 14D, when a refractory metal such as Ni (nickel) is deposited by sputtering to a thickness of 10 nm, a refractory metal film 67 is formed on the entire surface of the silicon substrate 61. . Subsequently, when a silicon substrate 61 and the refractory metal film 67 are reacted by performing a heat treatment at 300 ° C. as a silicidation annealing process, a silicide layer 68 is formed.

  In this silicidation annealing process, the side surface of the gate electrode 62 and the surface of a specific element region used as the resistance element 66 are covered with the sidewall 63 and the silicon oxide film 64, so that the silicon substrate 61 has a high melting point. Since the metal film 67 does not contact, the silicide layer 68 is not formed on the side surface of the gate electrode 63 and the specific element region used as the resistance element 66.

  Next, as shown in FIG. 14E, after the unreacted refractory metal film 67 is removed by selective etching, a low resistance annealing treatment is performed. Through the above steps, the silicide layer 68 is formed on the surface of the source / drain layer (not shown) of the silicon substrate 61 where the silicon oxide film 64 for silicidation block is not formed, and the bottom of the source / drain layer is formed. Uniform nickel silicide that does not grow abnormally is formed.

In the present embodiment, the case of removing carbon using a mixed gas of CF ₄ and O ₂ has been described. However, the present invention is not limited to this, and the same effect can be obtained with a mixed gas of NF ₃ and O ₂ .

  As described above, the present invention is useful for a semiconductor device having a silicide region.

Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment Sectional drawing which shows the principal part of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the modification of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the modification of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing which shows the principal part of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the modification of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the modification of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 4th Embodiment Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 4th Embodiment Sectional drawing which shows the manufacturing process of the semiconductor device of the 1st prior art example Sectional drawing which shows the manufacturing process of the semiconductor device of the 2nd prior art example Sectional drawing which shows the principal part of the semiconductor device of the 1st prior art example

Explanation of symbols

11, 21, 31, 41, 51, 61 Silicon substrate 12, 22, 32, 42, 52, 62 Gate electrode 13, 23, 33, 43, 53, 63 Side wall 14, 24, 34, 44, 54, 64 Silicon oxide film 15, 25, 35, 45, 55, 65 Resist pattern 16, 26, 36, 46, 56, 66 Resistive element 17, 27, 37, 47, 57, 67 Refractory metal film 18, 28, 38, 48, 58, 68 Silicide layer 19, 39 Reaction inhibition layer

Claims (15)

In a semiconductor device having an insulated gate transistor,
A gate electrode formed on a silicon substrate;
Sidewalls formed on both sides of the gate electrode;
A silicide region formed on the silicon substrate,
A semiconductor device comprising an element that inhibits a silicidation reaction in a surface region of the silicon substrate under the sidewall. In a semiconductor device having an insulated gate transistor,
A gate electrode formed on a silicon substrate;
Sidewalls formed on both sides of the gate electrode;
A source / drain layer formed on the silicon substrate;
A silicide region formed on the source / drain layer,
A semiconductor device, wherein the source / drain layer contains an element that inhibits a silicidation reaction. The semiconductor device according to claim 1, wherein the element that inhibits the silicidation reaction includes one or more of carbon, nitrogen, fluorine, and oxygen. In a method for manufacturing a semiconductor device having an insulated gate transistor,
Forming a gate electrode on the silicon substrate;
Forming sidewalls on both sides of the gate electrode;
Forming a silicide region on the silicon substrate,
A method of manufacturing a semiconductor device, comprising: forming a silicidation reaction inhibition layer in a surface region of the silicon substrate below the sidewall before the step of forming the silicide region. 5. The semiconductor device according to claim 4, wherein the reaction inhibition layer is formed by injecting an element that inhibits a silicidation reaction into a surface region of the silicon substrate before the sidewall formation step. 6. Production method. 5. The semiconductor device according to claim 4, wherein the reaction inhibition layer is formed by rotationally injecting an element that inhibits a silicidation reaction into a surface region of the silicon substrate after the sidewall formation step. 6. Production method. In a method for manufacturing a semiconductor device having an insulated gate transistor,
Forming a gate electrode on the silicon substrate;
Forming sidewalls on both sides of the gate electrode;
Forming a source / drain layer on the silicon substrate;
Forming a silicide region on the source / drain layer,
A method of manufacturing a semiconductor device, comprising: forming a silicidation reaction inhibition layer in the source / drain layer region before the step of forming the silicide region. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the source / drain layer, the reaction inhibition layer is formed by implanting an element that inhibits a silicidation reaction after source / drain implantation. Method. The step of forming the silicide region further includes a step of forming a refractory metal film on the silicon substrate, and a step of reacting the silicon substrate and the refractory metal film,
8. The semiconductor device according to claim 7, wherein the reaction inhibition layer is formed by implanting an element that inhibits a silicidation reaction into the source / drain layer before the step of forming the refractory metal film. Manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 4, wherein the element inhibiting the silicidation reaction is one or more of carbon, nitrogen, fluorine, and oxygen. The step of forming the silicide region further includes a step of forming a refractory metal film on the silicon substrate, and a step of reacting the silicon substrate and the refractory metal film,
The reaction inhibition layer is formed by performing plasma irradiation in a gas containing an element that inhibits silicidation reaction on the source / drain layer before the step of forming the refractory metal film. 8. A method for producing a semiconductor device according to 7. The method for manufacturing a semiconductor device according to claim 11, wherein the gas containing an element that inhibits the silicidation reaction includes one or more of CxFy, NF ₃ , NOx, and COx. In a method for manufacturing a semiconductor device having an insulated gate transistor,
Forming a gate electrode on the silicon substrate;
Forming sidewalls on both sides of the gate electrode;
Forming a source / drain layer on the silicon substrate;
Forming a refractory metal film on the silicon substrate;
Reacting the silicon substrate with the refractory metal film to form silicide regions on the source / drain layers,
Before the step of forming the refractory metal film, the surface of the silicon substrate is subjected to plasma irradiation in a mixed gas of fluorine-containing gas and oxygen gas. The method for manufacturing a semiconductor device according to claim 13, wherein the gas containing fluorine is CHF ₃ or CxFy having a high C / F ratio. The method for manufacturing a semiconductor device according to claim 13, wherein the gas containing fluorine is CxFy or NF ₃ .

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