KR100595461B1 - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device Download PDF

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KR100595461B1
KR100595461B1 KR1020000077008A KR20000077008A KR100595461B1 KR 100595461 B1 KR100595461 B1 KR 100595461B1 KR 1020000077008 A KR1020000077008 A KR 1020000077008A KR 20000077008 A KR20000077008 A KR 20000077008A KR 100595461 B1 KR100595461 B1 KR 100595461B1
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oxide film
tungsten
depositing
semiconductor device
titanium
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Korean (ko)
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KR20020046699A (en
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신진홍
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치 제조방법에 관한 것으로, 종래 반도체 장치 제조방법은 반도체 장치의 고집적화가 심화됨에 따라 배선과 반도체 소자의 특정영역간의 접촉면적이 줄어들게 되며, 이에 따라 접촉저항이 증가하는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 모스 트랜지스터가 제조된 기판의 상부전면에 산화막을 증착하고, 그 산화막을 패터닝하여 상기 모스 트랜지스터의 게이트 상부에 산화막을 잔존시키는 단계와; 상기 구조의 상부전면에 티타늄/질화티타늄층을 증착하고 열처리하여 상기 모스 트랜지스터의 소스 및 드레인영역의 상부에 실리사이드를 형성하는 단계와; 상기 구조의 상부전면에 텅스텐을 증착하고, 그 텅스텐을 평탄화하여 상기 게이트의 수준과 동일 수준의 텅스텐 패드를 형성하고, 상기 산화막의 상부에 증착된 티타늄/질화티타늄층을 식각하는 단계와; 상기 구조의 상부전면에 층간절연막을 증착하고, 사진식각공정을 통해 그 층간절연막에 콘택홀을 형성하여 상기 텅스텐 패드를 노출시키는 단계로 구성되어 반도체 소자의 실리콘 영역보다 표면적이 넓은 텅스텐 패드를 형성하여 배선과의 접촉저항을 줄일 수 있는 효과와 아울러 식각방지막을 사용하지 않음으로써, 보다 안정된 공정을 수행할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and according to the related art, as the integration of semiconductor devices increases, the contact area between a wiring and a specific region of the semiconductor device is reduced, thereby increasing the contact resistance. In view of the above problems, the present invention includes the steps of depositing an oxide film on an upper surface of a substrate on which a MOS transistor is manufactured, and patterning the oxide film to leave an oxide film on the gate of the MOS transistor; Depositing and heat treating a titanium / titanium nitride layer on the upper surface of the structure to form silicide on top of the source and drain regions of the MOS transistor; Depositing tungsten on the upper surface of the structure, planarizing the tungsten to form a tungsten pad at the same level as the gate level, and etching the titanium / titanium nitride layer deposited on the oxide film; Depositing an interlayer insulating film on the upper surface of the structure, and forming a contact hole in the interlayer insulating film through a photolithography process to expose the tungsten pad to form a tungsten pad having a surface area larger than that of a silicon region of a semiconductor device. In addition to reducing the contact resistance with the wiring and by not using an etching prevention film, there is an effect that can perform a more stable process.

Description

반도체 장치 제조방법{MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE}MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

도1a 내지 도1c는 종래 반도체 장치의 제조공정 수순단면도.1A to 1C are cross-sectional views of a manufacturing process of a conventional semiconductor device.

도2a 내지 도2d는 본 발명 반도체 장치의 제조공정 수순단면도.2A to 2D are cross-sectional views of a manufacturing process of the semiconductor device of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:기판 2:트랜지스터1: Substrate 2: Transistor

3:산화막 4:티타늄/질화티타늄층3: oxide film 4: titanium / titanium nitride layer

5:실리사이드 6:텅스텐 패드5: silicide 6: tungsten pad

7:층간절연막7: interlayer insulation film

본 발명은 반도체 장치 제조방법에 관한 것으로, 특히 반도체 소자의 특정영역에 접속되는 패드의 면적을 증가시켜, 공정의 용이성을 향상시킴과 아울러 접촉저항을 줄일 수 있는 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can increase the area of a pad connected to a specific region of a semiconductor device, thereby improving the ease of processing and reducing the contact resistance.

도1a 내지 도1c는 종래 반도체 장치의 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자(2)가 형성된 기판(1)의 상부에 금속을 증착하고, 열처리하여 상기 반도체 소자(2)의 실리콘영역의 상부에 실리사이드(3)를 형성하고, 그 상부전면에 식각방지막(4)과 층간절연막(5)을 순차적으로 증착하는 단계(도1a)와; 사진식각공정을 통해 상기 층간절연막(5)에 콘택홀을 형성하여 그 하부의 식각방지막(4)을 노출시키는 단계(도1b)와; 상기 노출된 식각방지막(4)을 식각하여 그 하부의 실리사이드(3)를 노출시키는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views of a manufacturing process of a conventional semiconductor device. As shown in FIG. 1A to 1C, a metal is deposited on a substrate 1 on which a semiconductor device 2 is formed and heat-treated to form silicon. Forming a silicide (3) on top of the region, and sequentially depositing an etch stop film (4) and an interlayer insulating film (5) on the upper surface thereof (FIG. 1A); Forming a contact hole in the interlayer insulating film 5 through a photolithography process to expose the lower etch stop film 4 (FIG. 1B); The exposed etch stop layer 4 is etched to expose the lower silicide 3 (FIG. 1C).

이하, 상기와 같이 구성된 종래 반도체 장치 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing a conventional semiconductor device configured as described above will be described in more detail.

먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 반도체 소자(2)를 제조한다.First, as shown in FIG. 1A, a semiconductor device 2 is fabricated on top of a substrate 1.

그 다음, 상기 반도체 소자(2)의 각 영역에 접촉저항을 줄이기 위해 금속을 증착하고, 그 금속과 상기 반도체 소자(2)의 실리콘 영역간에 반응이 일어나도록 열처리한 후, 잔존하는 금속을 제거하여, 상기 반도체 소자(2)의 실리콘 영역 상에 실리사이드를 형성한다.Then, a metal is deposited on each region of the semiconductor element 2 to reduce contact resistance, and heat-treated to cause a reaction between the metal and the silicon region of the semiconductor element 2, and then the remaining metal is removed. The silicide is formed on the silicon region of the semiconductor device 2.

그 다음, 상기 실리사이드(3)가 형성된 기판(1)의 상부전면에 식각방지막(4)과 층간절연막(5)을 순차적으로 증착한다.Next, the etch stop layer 4 and the interlayer dielectric layer 5 are sequentially deposited on the upper surface of the substrate 1 on which the silicide 3 is formed.

그 다음, 도1b에 도시한 바와 같이 상기 층간절연막(5)의 상부전면에 포토레지스트(도면 미도시)를 도포하고, 노광 및 현상하여 상기 층간절연막(5)의 상부일부를 노출시키는 패턴을 형성한다.Next, as shown in FIG. 1B, a photoresist (not shown) is coated on the upper surface of the interlayer insulating film 5, and exposed and developed to form a pattern for exposing a portion of the upper part of the interlayer insulating film 5. do.

그 다음, 상기 포토레지스트 패턴을 식각마스크로 사용하는 식각공정으로 상기 층간절연막(5)에 콘택홀을 형성하여 하부의 식각방지막(4)의 일부를 노출시킨다.Next, a contact hole is formed in the interlayer insulating layer 5 by an etching process using the photoresist pattern as an etching mask to expose a portion of the lower etch stop layer 4.

그 다음, 도1c에 도시한 바와 같이 상기 층간절연막(5)을 식각마스크로 사용하는 식각공정으로 상기 노출된 식각방지막(4)을 식각하여 실리사이드(3)의 일부를 노출시킨다.Next, as shown in FIG. 1C, a portion of the silicide 3 is exposed by etching the exposed etch stop layer 4 by an etching process using the interlayer insulating layer 5 as an etch mask.

이후의 공정에서는 상기 노출된 실리사이드(3)에 접속되는 배선을 형성하게 된다.In a later step, a wiring connected to the exposed silicide 3 is formed.

그러나, 종래 반도체 장치 제조방법은 반도체 장치의 고집적화가 심화됨에 따라 배선과 반도체 소자의 특정영역간의 접촉면적이 줄어들게 되며, 이에 따라 접촉저항이 증가하는 문제점이 있었다.However, the conventional semiconductor device manufacturing method has a problem that the contact area between the wiring and the specific region of the semiconductor device is reduced as the integration of the semiconductor device is increased, and thus the contact resistance is increased.

이와 같은 문제점을 감안한 본 발명은 반도체 장치의 고집적화가 심화되어도 반도체 소자의 특정영역과 배선이 접촉되는 면적을 일정면적 이상 확보할 수 있는 반도체 장치 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of securing a predetermined area or more in an area in which a specific region of a semiconductor element contacts a wiring even if the integration of semiconductor devices is increased.

상기와 같은 목적은 모스 트랜지스터가 제조된 기판의 상부전면에 산화막을 증착하고, 그 산화막을 패터닝하여 상기 모스 트랜지스터의 게이트 상부에 산화막을 잔존시키는 단계와; 상기 구조의 상부전면에 티타늄/질화티타늄층을 증착하고 열처리하여 상기 모스 트랜지스터의 소스 및 드레인영역의 상부에 실리사이드를 형성하는 단계와; 상기 구조의 상부전면에 텅스텐을 증착하고, 그 텅스텐을 평탄화하여 상기 게이트의 수준과 동일 수준의 텅스텐 패드를 형성하고, 상기 산화막의 상부에 증착된 티타늄/질화티타늄층을 식각하는 단계와; 상기 구조의 상부전면에 층간절연막을 증착하고, 사진식각공정을 통해 그 층간절연막에 콘택홀을 형성하여 상기 텅스텐 패드를 노출시키는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to deposit an oxide film on the upper surface of the substrate on which the MOS transistor is manufactured, and to pattern the oxide film so that the oxide film remains on the gate of the MOS transistor; Depositing and heat treating a titanium / titanium nitride layer on the upper surface of the structure to form silicide on top of the source and drain regions of the MOS transistor; Depositing tungsten on the upper surface of the structure, planarizing the tungsten to form a tungsten pad at the same level as the gate level, and etching the titanium / titanium nitride layer deposited on the oxide film; It is achieved by depositing an interlayer insulating film on the upper surface of the structure, and forming a contact hole in the interlayer insulating film through a photolithography process to expose the tungsten pad, referring to the accompanying drawings of the present invention. When described in detail as follows.

도2a 내지 도2d는 본 발명 반도체 장치 제조공정 수순단면도로서, 이에 도시한 바와 같이 모스 트랜지스터(2)가 제조된 기판(1)의 상부전면에 산화막(3)을 증착하고, 그 산화막(3)을 패터닝하여 상기 모스 트랜지스터(2)의 게이트 상부에 산화막(3)을 잔존시키는 단계(도2a)와; 상기 구조의 상부전면에 티타늄/질화티타늄층(4)을 증착하고 열처리하여 상기 모스 트랜지스터(2)의 소스 및 드레인영역의 상부에 실리사이드(5)를 형성하는 단계(도2b)와; 상기 구조의 상부전면에 텅스텐을 증착하고, 그 텅스텐을 평탄화하여 상기 게이트의 수준과 동일 수준의 텅스텐 패드(6)를 형성하고, 상기 산화막(3)의 상부에 증착된 티타늄/질화 티타늄층(4)을 식각하는 단계(도2c)와; 상기 구조의 상부전면에 층간절연막(7)을 증착하고, 사진식각공정을 통해 그 층간절연막(7)에 콘택홀을 형성하여 상기 텅스텐 패드(6)를 노출시키는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a semiconductor device manufacturing process of the present invention, in which an oxide film 3 is deposited on the upper surface of the substrate 1 on which the MOS transistor 2 is manufactured, and the oxide film 3 is formed. Patterning and leaving an oxide film (3) on the gate of the MOS transistor (2); Depositing and thermally treating a titanium / titanium nitride layer (4) on the upper surface of the structure to form silicide (5) on top of the source and drain regions of the MOS transistor (2); Tungsten is deposited on the upper surface of the structure, and the tungsten is planarized to form a tungsten pad 6 having the same level as that of the gate, and a titanium / titanium nitride layer 4 deposited on the oxide film 3. Etching) (FIG. 2C); The interlayer insulating film 7 is deposited on the upper surface of the structure, and a contact hole is formed in the interlayer insulating film 7 through a photolithography process to expose the tungsten pad 6 (FIG. 2D).

이하, 상기와 같이 구성된 본 발명 반도체 장치 제조방법을 좀 더 상세히 설명한다.Hereinafter, the semiconductor device manufacturing method of the present invention configured as described above will be described in more detail.

먼저, 도2a에 도시한 바와 같이 기판(1)의 상부에 필드산화막을 형성하여 소자형성영역을 정의하고, 그 소자형성영역에 모스 트랜지스터(2)를 형성한다.First, as shown in FIG. 2A, a field oxide film is formed on the substrate 1 to define an element formation region, and a MOS transistor 2 is formed in the element formation region.

그 다음, 상기 구조의 상부전면에 산화막(3)을 증착하고, 그 산화막(3)의 상부전면에 포토레지스트(도면 미도시)를 도포하고, 노광 및 현상하여 상기 산화막(3)의 일부영역을 노출시키는 패턴을 형성한다.Then, an oxide film 3 is deposited on the upper surface of the structure, a photoresist (not shown) is applied to the upper surface of the oxide film 3, and exposed and developed to expose a portion of the oxide film 3. Form a pattern to expose.

이때, 산화막(3)의 두께는 1000~3000Å의 두께로 증착한다.At this time, the thickness of the oxide film 3 is deposited to a thickness of 1000 ~ 3000Å.

그 다음, 상기 포토레지스트 패턴을 식각마스크로 사용하는 식각공정으로 상기 노출된 산화막(3)을 식각하여 상기 모스 트랜지스터(2)의 게이트 상부에 산화막(3)을 잔존시킨다.Next, the exposed oxide film 3 is etched by using the photoresist pattern as an etch mask, and the oxide film 3 remains on the gate of the MOS transistor 2.

이때, 상기 산화막(3)을 식각하는 공정은 C-F계열의 가스를 사용하며 압력 30~100mT가 되도록 하고, 전력을 300~700W, 자기장을 0~50G로 인가한 상태의 건식식각방법으로 식각하며, 필드산화막이 식각되지 않도록 주의하여야 한다.At this time, the process of etching the oxide film (3) using a CF-based gas to be a pressure of 30 ~ 100mT, etching by dry etching method with a power of 300 ~ 700W, a magnetic field of 0 ~ 50G, Care must be taken not to etch the field oxide film.

그 다음, 도2b에 도시한 바와 같이 상기 구조의 상부전면에 티타늄/질화티타늄층(4)을 증착하고 열처리하여 상기 모스 트랜지스터(2)의 소스 및 드레인영역의 상부에 실리사이드(5)를 형성한다.Next, as illustrated in FIG. 2B, a titanium / titanium nitride layer 4 is deposited on the upper surface of the structure and heat-treated to form silicide 5 on the source and drain regions of the MOS transistor 2. .

이때, 티타늄/질화티타늄층(4)은 그 두께가 300~600Å의 두께가 되도록 스퍼터링법을 이용하여 티타늄을 증착한 후, 질소분위기에서 열처리하여 형성한다.At this time, the titanium / titanium nitride layer 4 is formed by depositing titanium using a sputtering method so that the thickness of the titanium / titanium nitride layer to a thickness of 300 ~ 600Å, heat treatment in a nitrogen atmosphere.

그 다음, 도2c에 도시한 바와 같이 상기 구조의 상부전면에 텅스텐을 증착하고, 그 텅스텐을 평탄화하여 상기 게이트의 수준과 동일 수준의 텅스텐 패드(6)를 형성한다.Then, as shown in Fig. 2C, tungsten is deposited on the upper surface of the structure, and the tungsten is planarized to form a tungsten pad 6 at the same level as that of the gate.

이때, 증착되는 텅스텐은 화학 기상 증착법을 이용하여 3000~5000Å의 두께로 증착하고, 상기 평탄화공정은 5~50mT의 압력과, 200~600W의 전력, 자기장 50~100G의 분위기에서 SF6가스 50~200sccm, Cl2 20~50sccm을 사용한다.At this time, the deposited tungsten is deposited to a thickness of 3000 ~ 5000Å by chemical vapor deposition method, the planarization process is a SF 6 gas 50 ~ in the atmosphere of 5 ~ 50mT, 200 ~ 600W power, magnetic field 50 ~ 100G Use 200 sccm, Cl 2 20-50 sccm.

그 다음, 상기 산화막(3)의 상부에 증착된 티타늄/질화티타늄층(4)을 식각한다.Next, the titanium / titanium nitride layer 4 deposited on the oxide film 3 is etched.

이때의 식각공정은 5~50mT의 압력과, 200~500W의 전력, 자기장 50~100G의 분위기에서 Ar 50~200sccm, Cl2 20~50sccm을 사용한다.At this time, the etching process uses Ar 50 ~ 200sccm, Cl 2 20 ~ 50sccm in the pressure of 5 ~ 50mT, 200 ~ 500W power, 50 ~ 100G magnetic field.

그 다음, 도2d에 도시한 바와 같이 상기 구조의 상부전면에 층간절연막(7)을 증착하고, 사진식각공정을 통해 그 층간절연막(7)에 콘택홀을 형성하여 상기 텅스텐 패드(6)를 노출시킨다.Next, as shown in FIG. 2D, an interlayer insulating film 7 is deposited on the upper surface of the structure, and a contact hole is formed in the interlayer insulating film 7 through a photolithography process to expose the tungsten pad 6. Let's do it.

이후의 공정에서는 상기 텅스텐패드(6)에 접속되는 배선을 형성하게 된다.In a later step, a wiring connected to the tungsten pad 6 is formed.

상기한 바와 같이 본 발명 반도체 장치 제조방법은 반도체 소자의 실리콘 영역보다 표면적이 넓은 텅스텐 패드를 형성하여 배선과의 접촉저항을 줄일 수 있는 효과와 아울러 식각방지막을 사용하지 않음으로써, 보다 안정된 공정을 수행할 수 있는 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention forms a tungsten pad having a surface area larger than that of the silicon region of the semiconductor device, thereby reducing contact resistance with the wiring, and not using an etching prevention film, thereby performing a more stable process. It can work.

Claims (1)

모스 트랜지스터가 제조된 기판의 상부전면에 산화막을 증착하고, 그 산화막을 패터닝하여 상기 모스 트랜지스터의 게이트 상부에 산화막을 잔존시키는 단계와; 상기 구조의 상부전면에 티타늄/질화티타늄층을 증착하고 열처리하여 상기 모스 트랜지스터의 소스 및 드레인영역의 상부에 실리사이드를 형성하는 단계와; 상기 구조의 상부전면에 텅스텐을 증착하고, 그 텅스텐을 평탄화하여 상기 게이트의 수준과 동일 수준의 텅스텐 패드를 형성하고, 상기 산화막의 상부에 증착된 티타늄/질화티타늄층을 식각하는 단계와; 상기 구조의 상부전면에 층간절연막을 증착하고, 사진식각공정을 통해 그 층간절연막에 콘택홀을 형성하여 상기 텅스텐 패드를 노출시키는 단계를 포함하여 된 것을 특징으로 하는 반도체 장치 제조방법.Depositing an oxide film on an upper surface of the substrate on which the MOS transistor is manufactured, and patterning the oxide film to leave an oxide film on the gate of the MOS transistor; Depositing and heat treating a titanium / titanium nitride layer on the upper surface of the structure to form silicide on top of the source and drain regions of the MOS transistor; Depositing tungsten on the upper surface of the structure, planarizing the tungsten to form a tungsten pad at the same level as the gate level, and etching the titanium / titanium nitride layer deposited on the oxide film; And depositing an interlayer insulating film on the upper surface of the structure, and forming a contact hole in the interlayer insulating film through a photolithography process to expose the tungsten pad.
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