JP3666192B2 - Burn-in test method - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a burn-in test method for a test sample such as a semiconductor device.
[0002]
[Prior art]
In recent years, with the high integration of LSI devices, the internal structure of the LSI has been miniaturized. For this reason, multilayering of wirings and thinning of insulating films between wiring layers are progressing. For example, an application-specific device such as an ASIC is required to be multi-functional, and a memory having a large capacity is also required. Specifically, 64 MDRAM is required under the 0.35 μm rule.
[0003]
In such a semiconductor device, a method for improving the quality in the process is adopted, but in order to guarantee the reliability of the product by eliminating the initial failure, for example, to guarantee the reliability of the gate oxide film An accelerated reliability test called a burn-in test has been conducted. This burn-in test is a technique of accelerating the clarification of potential defective parts by applying stress due to a predetermined high temperature, high voltage, etc., and eliminating defective products by a subsequent operation test or the like.
[0004]
This burn-in test is performed by mounting a packaged semiconductor device on a socket attached on a substrate called a burn-in board and supplying a predetermined voltage to the terminals.
[0005]
[Problems to be solved by the invention]
However, as described above, the burn-in probe is in electrical contact with the terminal and the pad electrode, so that physical contact is always made, so mechanical wear is severe, and the pad electrode may be damaged. There is a problem. In addition, when the voltage applied to the probe is high, the probe wears more severely. When the probe is consumed heavily, frequent cleaning and replacement are required, which causes problems such as an increase in running cost and a reduction in the operation rate of the apparatus.
[0006]
Furthermore, in recent years, with the higher integration, higher speed, and higher functionality of devices, it has become unavoidable to increase the number of pins of a chip. For pad electrodes provided in each circuit formation region of a semiconductor wafer, Also, burn-in tests at the wafer stage, such as bringing the probe into electrical pressure contact, are actively performed. However, this is not a basic solution for probe wear.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a burn-in test method capable of suppressing damage to the electrode to be inspected and the test probe.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has taken the following measures. That is, the present invention is, burn-is disposed a probe for burn-in test on the electrode of the test sample with electrodes, performing burn-in test by applying a bias in a non-contact state between the electrode and the probe In the test method, a burn-in test method is provided , wherein an insulating film is formed on the electrode .
[0009]
According to these configurations, the burn-in test can be performed in a state where the electrode of the sample to be inspected and the test probe are not in contact with each other, so that the electrode and the test probe can be prevented from being damaged and highly reliable. The burn-in test can be performed stably.
[0010]
In the method of the present invention, the bias is preferably performed by corona discharge. In the apparatus of the present invention, the bias applying means is preferably corona discharge generating means. Corona discharge has a track record in SPV analysis and the like, and it is easy to stabilize the measurement. Further, since a certain amount of charge is generated by corona discharge, one of the probe and the electrode may not be grounded and may be in a floating state. Even in this case, it is preferable that one is grounded.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, a case where the burn-in test method and the burn-in test apparatus are applied to a burn-in test on a semiconductor wafer will be described.
[0012]
FIG. 1 is a schematic sectional view showing a burn-in test apparatus according to the present embodiment. First, as shown in FIG. 1, a burn-in test apparatus 10 has a high-temperature thermostatic chamber 1 that accommodates a semiconductor wafer W that is a sample to be inspected, and a stage in which the semiconductor wafer W is held and can be moved up and down. 2 and a vacuum suction line 3 for vacuum-sucking the wafer W onto the stage 2. The stage 2 includes heating means (not shown), and temperature control is possible.
[0013]
A plurality of semiconductor elements are formed on the semiconductor wafer W, and a large number of pad electrodes are formed on each semiconductor element in an exposed state. The shape of the pad electrode may be any shape as long as the charge is not biased.
[0014]
The high-temperature thermostatic chamber 1 has a configuration capable of raising and maintaining the semiconductor wafer W at a predetermined temperature, and can apply temperature stress. Further, since the vacuum suction lines 3 are provided at least at a plurality of locations, for example, the central portion and the peripheral portion of the semiconductor wafer W to be mounted, the warp of the semiconductor wafer W even after being subjected to thermal stress. It is the structure which can suppress generation | occurrence | production of this.
[0015]
Further, above the semiconductor wafer W, the cantilever 4 is held at a position floating about several μm to 1000 μm from the surface of the wafer W. Thereby, the flying height of the probe 5 described later can be controlled to a desired value.
[0016]
In addition, the probe 5 is disposed above the semiconductor wafer W so as to face the semiconductor wafer W, and is configured to be movable in the vertical and horizontal directions with respect to the semiconductor wafer W. For this position control, based on position information from the cantilever 4, mobile controllable control means 6 is provided to a desired position. Therefore, the probe 5 can be scanned on the semiconductor wafer W.
[0017]
Further, as shown in FIG. 2, a bias is applied to the probe 5 so that a high voltage, for example, a voltage due to corona discharge can be applied to the Al pad electrode 8 covered with the passivation film 7 in the semiconductor element. Means 9 are provided. Since a high voltage is applied to the probe 5 as described above, the probe 5 is preferably made of a W alloy such as W or WTix. The size of the probe 5 is preferably substantially the same as that of the pad electrode 8, but the size of the probe 5 is such that it does not electrically interfere with the adjacent pad electrode, for example, if it does not overlap with a plurality of adjacent pad electrodes. It may be larger than the electrode.
[0018]
In the burn-in test apparatus having such a configuration, a desired burn-in test, for example, a thermal stress test or an electrical stress test is performed in a state where a semiconductor wafer W on which a predetermined semiconductor element is formed is first vacuum-adsorbed on the stage 2. Apply. In the present invention, by applying a desired bias to the probe 5 from the bias applying means 9, a corona discharge is generated and a burn-in test is performed.
[0019]
In this case, first, the probe 5 is moved onto the predetermined pad electrode 8 based on the position information from the cantilever 4. Then, after controlling to a desired height position, corona discharge is generated for the pad electrode 8. Thus, since the burn-in test can be performed in a non-contact state, mechanical damage to the semiconductor wafer W that is the sample to be inspected can be suppressed. In addition, since corona discharge is used, the test can be performed even when an insulating film such as an oxide film is formed on the electrode.
[0020]
Thus, the method of the present invention can use the wafer burn-in apparatus currently used for production by changing only the probe. In addition, since the probe is not mechanically consumed, the running cost of measurement is reduced and the reliability is improved. In addition, the method of the present invention has less positional accuracy than a method using a conventional needle probe. Therefore, both methods can be shared in multiple generations.
[0021]
As shown in FIGS. 3A to 3C, the bias voltage applied to the probe 5 can be selected from a DC bias or an AC bias having an arbitrary polarity. Due to such a configuration, an optimum bias can be applied according to the difference in element structure and various electrode materials. The bias application may be performed continuously on the electrodes, or may be performed intermittently by scanning.
[0022]
Further, the probe 5 is configured to be controllable to a desired discharge gap. The position of the optimum discharge gap can be controlled by the control means 6 depending on the type of bias to be applied and the element structure to be tested. In the present embodiment, the probe 5 is controlled to be positioned when the optimum discharge position is controlled. However, the stage 2 may be controlled to the optimum position by controlling the position of the stage 2.
[0023]
Further, as shown in FIG. 4, a scan may be performed in which the stage 2 and the probe 5 are relatively rotated. By doing so, the bias application time can be effectively shortened.
[0024]
The present invention can be variously modified without being limited to the above embodiment. For example, as shown in FIG. 5, a plurality of semiconductor elements may be collectively tested by a burn-in test apparatus equipped with a multichip probe 11. In this case, for example, by arranging the probes in a honeycomb shape, or by producing them in accordance with the layout of the pad electrodes to which the probes are applied, a burn-in test can be performed in a lump and throughput can be improved.
[0025]
Further, in the above embodiment, the burn-in test in the state of the semiconductor wafer has been described. However, the present invention can also be applied to a burn-in test of a resin-encapsulated semiconductor device.
[0026]
【The invention's effect】
As described above, according to the present invention, the burn-in test is performed by conducting electrical continuity in a non-contact state between the terminal under test and the burn-in test probe. A burn-in test method capable of suppressing mechanical damage can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing the structure of a burn-in test apparatus as one embodiment of the present invention.
FIG. 2 is an enlarged sectional view of the burn-in test apparatus shown in FIG.
3 is a schematic diagram showing a state of discharge of the burn-in test apparatus shown in FIG. 1. FIG.
4 is a schematic diagram showing the operation of the burn-in test apparatus shown in FIG.
FIG. 5 is a schematic cross-sectional view showing the structure of a burn-in test apparatus as another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... High temperature thermostatic chamber, 2 ... Stage, 3 ... Vacuum suction line, 4 ... Cantilever, 5 ... Probe, 6 ... Control means, 7 ... Passivation film, 8 ... Pad electrode, 9 ... Bias application means, 10 ... Burn-in test apparatus , 11 ... multi-chip probe, W ... semiconductor wafer.

Claims (1)

In the burn-in test method of performing a burn-in test by placing a probe for burn-in test on the electrode of the sample to be inspected having an electrode and applying a bias in a non-contact state between the electrode and the probe ,
A burn-in test method, wherein an insulating film is formed on the electrode .

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