JP3625523B2 - Single electronic element, semiconductor memory device, and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a structure of a single electronic memory using a single electronic element and a manufacturing method thereof.
[0002]
[Prior art]
Single-electron devices are expected as the ultimate highly integrated low-power devices, but there has been a major obstacle that they can only operate at extremely low temperatures. In 1993, Hitachi's Yano et al. Successfully used a single-electron device (single-electron memory) at room temperature for the first time in the world by using an ultra-thin polycrystalline silicon (hereinafter referred to as Si) transistor (IEEE Int. Electron Devices). Meet. 1993, pp 541-544). Hereinafter, the structure of the single electronic memory developed by Yano et al. And the outline of the operation principle will be described with reference to FIGS.
FIG. 17 shows a plan view (a) and a sectional view (b) of an ultra-thin polycrystalline Si transistor. Here, the cross-sectional view shows a cross-section at aa ′ in the plan view. First, the single crystal Si substrate 801 is thermally oxidized to form a 500 nm SiO film.₂After forming the film 802, a polycrystalline Si film 803 containing phosphorus is deposited to a thickness of 100 nm by chemical vapor deposition (CVD). Next, the phosphorus-doped polycrystalline film 803 is processed into a desired shape by well-known lithography and dry etching methods to form a source 803 (a) and a drain 803 (b). Subsequently, after depositing 4 nm of an amorphous Si film to be the channel layer 804 by CVD, heat treatment is performed in a nitrogen atmosphere at 750 ° C. to convert the amorphous Si film into a polycrystalline Si film 804.
One of the key points that determine the characteristics of the ultra-thin polysilicon transistor is the thickness of the channel polycrystalline Si film 804 and its local film thickness non-uniformity. It is desirable that the film thickness non-uniformity is large.
Next, the channel polycrystalline Si film 804 is processed using electron beam (EB) lithography and dry etching technology. At this time, the channel polycrystalline Si width W is desirably as small as possible, and specifically, is preferably about 100 nm or less. Finally, SiO which becomes the gate insulating film 805 by the CVD method₂  After depositing about 100 nm of the film 805 and 100 nm of phosphorus-doped polycrystalline Si 806 to be the gate electrode 806, the gate electrode 806 is formed by a well-known technique, and the formation of the ultra-thin polycrystalline Si transistor is completed.
[0003]
An ultra-thin polycrystalline Si transistor having a very thin channel polycrystalline Si film (about 2 to 10 nm) exhibits characteristics different from those of a polycrystalline Si transistor (30 to 40 nm) conventionally used as a load element of SRAM. As shown in FIG. 18A, when a voltage is applied to the gate electrode, the current path (channel) of the ultra-thin polycrystalline Si transistor is along the path with the smallest resistance, that is, along the thick polycrystalline Si film. It is formed. This channel width is as large as the grain size of the polycrystalline Si film, and an extremely narrow channel of about 5 to 10 nm is formed. As the gate bias is further applied, electrons are ejected from the channel and injected into the grains (storage nodes) near the channel. This electron eliminates the potential difference between the channel and the storage node, and the electron is confined in the storage node. This corresponds to the writing of information. In such a state (FIG. 18B), the drain current decreases due to the Coulomb repulsion with the confined electrons. This means that the threshold value of the transistor shifts depending on the presence or absence of electrons in the storage node, and information (1 or 0) can be determined by measuring the threshold value.
The above-mentioned phenomenon occurs under the limited condition that the channel polycrystalline Si film is extremely thin (10 nm or less) and the channel width is about 100 nm or less, and is used as a load element of SRAM. Such a phenomenon does not occur in the Si transistor.
[0004]
[Problems to be solved by the invention]
One of the technical problems of single-electron memory using ultra-thin polycrystalline Si transistors is stable channel formation. As shown in FIG. 19, when the width W of the polycrystalline Si film in which the channel is formed is large, the possibility that a plurality of channels are formed in the same layer increases. If a plurality of channels are blocked simultaneously, no particular problem occurs. However, if there are channels that are not blocked, the amount of change in current density becomes small, making determination difficult. Further, since the threshold shift amount increases as the capacitance related to the channel decreases, the width of the polycrystalline Si film is preferably as small as possible. Specifically, a width of 100 nm or less is required.
However, electron beam (EB) lithography or X-ray lithography is the only method for patterning 100 nm thin lines with current lithography technology. These methods not only require a great deal of processing time, but also have many problems in terms of reproducibility and technical aspects, and become a bottleneck when mass-producing large-capacity memories.
[0005]
An object of the present invention is to provide a single electronic device having a structure capable of easily forming a channel layer of a polycrystalline Si film having a width of 100 nm or less, a semiconductor memory device using the same, and a method for manufacturing the same.
[0006]
[Means for Solving the Problems]
To achieve the above object, the single electronic device of the present invention is a single electronic device as an insulated gate field effect transistor having a thin polycrystalline silicon film channel layer connected to a source and a drain. As shown in the insulating film 405 in the sectional view of FIG. 8, the insulating film having a thickness corresponding to the width of the channel layer (for example, FIG. 8) spans the source (404 (a)) and the drain (404 (b)). Then, an insulating film 405 having a thickness of 70 nm is provided, and the channel layer (407 (a) or 407 (b)) is formed on the sidewall thereof.
[0007]
Here, the thickness of the channel layer is preferably 10 nm or less, and the width of the channel layer is preferably 100 nm or less.
[0008]
In this case, it is one feature that the underlying insulating film is formed so that the channel layer has a U-shaped cross-sectional shape.
[0009]
Further, it is preferable that a nitrogen atom is contained on the surface of the insulating film underlying the channel layer in contact with the channel layer in order to form a thin stable channel layer.
[0010]
Furthermore, it is desirable to provide a good quality channel layer free from damage and contamination by providing an insulating film as a protective film on the surface of the channel layer.
[0011]
According to another aspect of the present invention, there is provided a semiconductor memory device having a memory array configuration having a plurality of data lines, word lines crossing the data lines, and memory elements at the crossing positions. The storage element is the above-described single electronic element of the present invention. As shown in FIG. 13, for example, the single electronic element has its source and drain connected to adjacent data lines and its gate connected to a word line. Suppose that it has the composition which was done.
[0012]
Here, as seen in FIG. 13 or FIG. 14, for example, a plurality of single electronic elements connect each source to a common data line, and each adjacent data line across the common data line. It is also possible to provide a configuration in which the drain is connected and each gate is connected to a common word line.
[0013]
Alternatively, for example, as shown in FIG. 15 or FIG. 16, if a plurality of sets of the plurality of single electronic elements are further provided with a configuration in which a word line is shared, a plurality of elements are controlled by the same gate electrode. be able to.
[0014]
Further, in the method for manufacturing a single electronic device of the present invention for achieving the above object, as a step of forming a channel layer, for example, as shown in FIG. A first insulating film 102 for forming a surface layer of the substrate, a second insulating film 103 having a thickness corresponding to the width of the channel layer as a base film for the channel layer, and an etching rate slower than that of the second insulating film A step of sequentially forming the third insulating film 104; a step of processing the second and third insulating films into a predetermined shape; and etching the sidewall of the second insulating film 103 to form a third insulating film A step of forming a U-shaped cross-sectional shape by retreating from the edge portion of 104, a step of forming a polycrystalline silicon film 105 on the insulating film, as shown in FIG. As seen in the anisotropic dry etch By then etching the polycrystalline silicon film 105, the side walls of the second insulating film polycrystalline silicon film 105 (a), and comprise at least a step of leaving a 105 (b).
[0015]
In order to achieve the above object, a semiconductor memory device manufacturing method according to the present invention includes a plurality of data lines, a word line crossing the data line, and a memory array structure having a memory element at the crossing position. In the manufacturing method, the process for forming the memory element includes the process of the method for manufacturing a single electronic element of the present invention as shown in FIGS.
[0016]
[Action]
The structure of the single electronic device according to the present invention includes a structure in which a channel layer is formed on the side wall of an insulating film having a thickness corresponding to the width of the channel layer as an underlayer for forming the channel layer. Therefore, according to the present invention, the width of the ultra-thin polycrystalline silicon film can be controlled by the thickness of the underlying insulating film. Therefore, it can be formed very easily even with a width of 100 nm or less. In addition, since ordinary optical lithography and excimer laser lithography techniques can be applied, mass productivity is dramatically improved.
In this case, the channel layer is formed on the side wall of the insulating film by the method for manufacturing a single electronic device of the present invention, on the second insulating film serving as a base for forming the channel layer, with a slower etching rate. The third insulating film is formed, and after etching these insulating films into a predetermined shape, the second insulating film is retracted from the edge portion of the third insulating film, and a U-shaped cross-sectional shape is formed. Can be easily formed. As a result, a U-shaped channel layer remains on the side wall of the underlying insulating film by forming a subsequent polycrystalline silicon film on these insulating film surfaces and anisotropic dry etching, and the channel layer can be easily formed. Will be formed.
As described above, according to the present invention, since a channel layer having a width of 100 nm or less can be easily formed, not only a single electronic element but also a semiconductor memory device using the same can be easily configured.
[0017]
【Example】
Example 1
Hereinafter, a first embodiment of channel formation according to the present invention will be described with reference to FIG.
First, in FIG. 1A, a P-type (100) single crystal Si substrate 101 is first thermally oxidized in a water vapor atmosphere at 1000 ° C.₂After forming the film 102, 100 nm of SiO is formed by the CVD method.₂Film 103, 30 nm Si₃N₄A film 104 is sequentially deposited. In this example, SiO₂The film 103 is monosilane (SiH₄) And nitrous oxide (N₂O) at a temperature of 750 ° C.₃N₄The film 104 is made of dichlorosilane (SiH₂Cl₂) And ammonia (NH₃) At a temperature of 770 ° C.
Next, the Si film is formed by a well-known photolithography and dry etching method.₃N₄104 / SiO₂After sequentially etching the layered film 103, the above-described SiO 2 was added with 1% HF aqueous solution.₂The side wall of the film 103 is etched to form Si₃N₄The film 104 is made to recede from the pattern edge. In this case, Si₃N₄104 is SiO₂Since the etching rate is slower than 103, the SiO₂The side wall of the film is Si₃N₄Retreat from the edge of the film. In this example, the recession of about 15 nm was performed by etching.
Subsequently, in FIG. 1B, after depositing an amorphous Si film having a thickness of 4 nm by the CVD method, heat treatment is performed in a nitrogen atmosphere at 800 ° C. to convert the amorphous Si film into the polycrystalline Si film 105. Convert. In this embodiment, monosilane (SiH) is used for depositing an amorphous Si film.₄) At a temperature of 520 ° C., but disilane (Si₂H₆) Is of course possible.
Next, in FIG. 1C, the polycrystalline Si film 105 is etched by anisotropic dry etching. According to anisotropic dry etching, Si₃N₄Since the portion serving as a mask in the film 104 is not etched, SiO 2₂The film 103 pattern side wall is almost SiO.₂Polycrystalline Si film patterns 105 (a) and 105 (b) corresponding to the film thickness are formed.
What is important in this embodiment is that the Si film is more than the thickness of the ultra-thin polycrystalline Si105.₃N₄Film 104 pattern edge to SiO₂The film 103 is retracted. SiO₂A method for preventing the film 103 from retreating, that is, Si₃N₄When the film 104 is not used as a mask, SiO₂Since the polycrystalline Si film 105 on the sidewall of the film 103 is also etched, a desired width cannot be ensured.
This method is characterized in that a width of 100 nm or less can be formed with good controllability, and that the cross-sectional shape of the ultra-thin polycrystalline Si film 105 is a U-shape.
[0018]
(Example 2)
Next, a second channel forming embodiment of the present invention will be described with reference to FIG.
In FIG. 2A, a 500 nm SiO film is formed on the single crystal Si substrate 201 by the same method as in the first embodiment.₂Film 202, SiO₂Film 203 and Si₃N₄After forming the film 204, Si₃N₄204 / SiO₂The 203 laminated film is patterned. After this, the exposed SiO using 1% HF aqueous solution₂The side wall of the film 203 is etched by 15 nm.
Subsequently, in FIG. 2B, a 4 nm amorphous Si film and a 10 nm SiO film are formed by CVD.₂A film 206 is sequentially deposited (FIG. 2B). The amorphous Si film is made of 10 nm SiO.₂When the film 206 is deposited, the film 206 is converted into the polycrystalline Si film 205 depending on the temperature in the furnace (750 ° C.).
Next, in FIG. 2 (c), the SiO 2 is etched by anisotropic dry etching.₂The film 206 and the polycrystalline Si film 205 are sequentially etched to obtain SiO₂The polycrystalline Si film 205 is left on the side wall of the film 203 pattern.
According to this method, when the polycrystalline Si film 205 is etched, 10 nm of SiO₂Since the film 206 serves as a protective film, it is possible to obtain a high-quality polycrystalline Si film 205 that is completely free from plasma damage and contamination.
[0019]
(Example 3)
Next, a third embodiment of channel formation according to the present invention will be described with reference to FIG.
3A, a P-type (100) single crystal Si substrate 301 is thermally oxidized in a water vapor atmosphere at 1000 ° C.₂After forming the film 302, 50 nm Si is formed by CVD.₃N₄Film 303, 50 nm SiO₂Film 304, 30 nm Si₃N₄A film 305 is sequentially deposited.
Next, the Si film is formed by a known photolithography and dry etching method.₃N₄305 / SiO₂After sequentially etching the 304 laminated film, the above-described SiO 2 was added with 1% HF aqueous solution.₂The side wall of the film 304 is etched to form Si₃N₄Retreat from the film 305. In this example, etching of about 10 nm was performed. Subsequently, 800 ° C. ammonia (NH₃) Heat treatment for 10 minutes in atmosphere, CVD-SiO₂The side wall of the film 304 is nitrided.
Next, in FIG. 3B, after depositing an amorphous Si film having a thickness of 2.5 nm by the CVD method, heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 seconds using a short-time lamp annealing method. The amorphous Si film is converted into a polycrystalline Si film 306. In this embodiment, disilane (Si₂H₆) At a temperature of 450 ° C.
The thin Si film deposited by the CVD method is closely related to the nucleation density of the underlying surface, and a thin continuous film cannot be obtained on a film having a low nucleation density. In general, SiO₂Si compared to the film₃N₄Since a thinner continuous film can be obtained by depositing on the film, the underlying film of the ultra-thin Si film is SiO.₂A membrane is not preferred. However, if thermal nitridation is performed in an ammonia atmosphere before depositing the Si film, a thin continuous film can be obtained regardless of the type of the underlying film. In this example, Si₃N₄305 / SiO₂After patterning 304, nitriding with ammonia was performed.₂Similar results can be obtained by performing nitriding immediately after deposition of 304.
On the other hand, the grain size of the polycrystalline Si film varies greatly depending on the film thickness and the crystallization method. In order to obtain a smaller grain size, it is effective to reduce the Si film thickness and to perform crystallization at a high temperature in a short time. The grain size of the polycrystalline Si film 306 produced in this example was 3 to 8 nm, and very fine crystal grains were obtained.
Next, in FIG. 3C, CVD-SiO serving as a protective film for etching the polycrystalline Si film 306 by the same method as in the second embodiment.₂After the film 307 is deposited to a thickness of 10 nm, the CVD-SiO 2 is formed by anisotropic dry etching.₂307 / Polycrystalline Si film 306 is sequentially etched to form nitrided SiO₂A polycrystalline Si film 306 is left on the side wall of the film 204 pattern.
[0020]
(Example 4)
Next, as a fourth example, an example of an ultra-thin polycrystalline Si transistor manufactured using the method shown in Examples 1 and 3 will be shown (FIGS. 4 to 8 and FIGS. 13 to 14). FIGS. 4 to 8 show the manufacturing process of this embodiment, FIG. 13 shows an equivalent circuit diagram of the memory array portion of the ultra-thin polycrystalline Si transistor prototyped in this embodiment, and FIG. 14 shows the plane of the memory array portion. Each layout diagram is shown.
4 and 14, a P-type (100) single crystal Si substrate 401 is thermally oxidized to form a 500 nm SiO film.₂After forming the film 402, 50 nm Si is formed by CVD.₃N₄A film 403 and a 70 nm phosphorus-doped polycrystalline Si film 404 containing phosphorus at a high concentration are sequentially deposited. Subsequently, the phosphorus-doped polycrystalline Si film 404 is patterned by krypton fluoride (KrF) excimer laser lithography and dry etching, and common source lines 404 (a), 601 serving as the source and drain of the polycrystalline Si transistor. And data lines 404 (b), 602 (a), and 602 (b). In this embodiment, monosilane (SiH) is used for depositing the phosphorus-doped polycrystalline Si films 404, 601, and 602.₄) And phosphine (PH₃) Gas was used for deposition at a temperature of 600 ° C. After this, 70 nm of SiO is formed by CVD.₂Film 405, 30 nm Si₃N₄After sequentially depositing the film 406, Si is perpendicular to the common source lines 404 (a) and 601 and the data lines 404 (b), 602, (a) and (b).₃N₄406 / SiO₂Patterning of the 405 laminated film is performed.
[0021]
Next, in FIGS. 5 and 14, the above-mentioned 70 nm SiO is used by using 1% hydrofluoric acid aqueous solution.₂The side wall of the film 405 is etched to form Si₃N₄After retreating about 15 nm from the pattern edge of the film 406, heat treatment is performed in an ammonia atmosphere at 750 ° C.₂The side wall portion of the film 405 is nitrided. Subsequently, an amorphous Si film having a thickness of about 3 nm is deposited by CVD, and then heat-treated at 900 ° C. for 30 seconds by short-time annealing to convert the amorphous Si film into polycrystalline Si films 407 and 603. Convert. In this embodiment, monosilane (SiH) is used for depositing the amorphous Si film.₄) At a temperature of 500 ° C.
[0022]
Next, in FIGS. 6 and 14, the polycrystalline Si films 407 and 603 are etched by anisotropic dry etching. Si₃N₄Since the portion where the film 406 serves as a mask is not etched, Si₃N₄406 / SiO₂A pattern of a polycrystalline Si film 407 having a thickness of about 3 nm and a width of about 70 nm is formed around the 405 laminated film.
[0023]
Next, in FIGS. 7 and 14, after a photoresist pattern 408 is formed in a predetermined shape by excimer lithography,IsotropicUnnecessary portions of the polycrystalline Si film 407 by dry etching technology (in FIG. 7B, common source line 404 (a), both end portions of 405 parallel to the wiring of the data line 404 (b), and the channel layer in FIG. Etch the removed part). In this step, the polycrystalline Si film patterns 407 (a), 407 (b), and 603 are individually insulated.
Next, after performing an oxygen plasma ashing process to remove the photoresist pattern 408, the wafer surface is cleaned with a dilute hydrofluoric acid aqueous solution.
[0024]
Next, in FIG. 8 and FIG. 14, the SiO which becomes the gate insulating film 409 by the CVD method.₂After depositing 20 nm of the film 409 and 50 nm of the phosphorus-doped polycrystalline Si films 410 and 604 to be the gate electrodes 410 and 604, the phosphor-doped polycrystalline Si films 410 and 604 are patterned by excimer laser lithography and dry etching to form word lines ( Gate electrode) 410 (a), 410 (b), 604.
[0025]
13 and 14, KrF excimer laser lithography and phase shift technology are applied to patterning the common source line 601, the data lines 602 (a) and (b), and the word line 604. A line / space of 16 μm (pitch 0.32 μm) was realized. Further, the line width of the ultra-thin polycrystalline Si film 603 in which the channel is formed has achieved 70 nm which is less than the optical lithographic fee resolution limit.
[0026]
(Example 5)
Next, a fifth embodiment of the present invention will be described with reference to FIGS. 9 to 12 and FIGS. 15 to 16. 9 to 12 show the manufacturing process of this embodiment, FIG. 15 shows an equivalent circuit diagram of the memory array portion of the ultra-thin polycrystalline Si transistor prototyped in this embodiment, and FIG. 16 shows a plan view of the memory array portion. A layout diagram is shown.
In FIG. 9, a 500 nm SiO film is formed on the single crystal Si substrate 501 in the same manner as in the third embodiment.₂Film 502, 50 nm CVD-Si₃N₄After forming the film 503 and the 50 nm phosphorus-doped polycrystalline Si film 504, the phosphorus-doped polycrystalline Si film 504 is patterned to obtain common source lines 504 (a) and 701, and data lines 504 (b) and 702 (a). , (B). Next, 50 nm CVD-SiO₂Film 505, 30 nm CVD-Si₃N₄After sequentially depositing film 506, Si₃N₄506 / SiO₂505 / Si₃N₄The 503 laminated insulating film is processed into a predetermined shape. Subsequently, the SiO of the laminated insulating film with 1% hydrofluoric acid aqueous solution₂The side wall portion of the film 505 is etched to recede 20 nm from the pattern edge. Thereafter, heat treatment is performed for 10 minutes in an ammonia atmosphere at 750 ° C., and SiO 2₂Nitridation is performed on the side wall portion of the film 505.
[0027]
Next, in FIGS. 10 and 16, disilane (Si₂H₆After depositing a 6 nm amorphous Si film by a CVD method using thermal decomposition of the above), the amorphous Si film is oxidized by a short-time oxidation method by lamp heating to be converted into polycrystalline Si films 507 and 703. And 6nm SiO₂A film 508 is formed. In this example, the SiO₂A film 508 was formed in a dry oxygen atmosphere at 1000 ° C. This SiO₂With the formation of the film 508, the thickness of the polycrystalline Si films 507 and 703 is reduced from 7 nm during deposition to 3 nm, and at the same time, the polycrystalline Si films 507 and 703 are protected from damage caused by dry etching, contamination, Become. Next, SiO serving as a protective film for etching the polycrystalline Si films 507 and 703₂508 film and polycrystalline Si films 507 and 703 are sequentially etched to form nitrided SiO₂Polycrystalline Si films 507 and 703 are left on the side walls of the film 505 pattern.
[0028]
Next, in FIGS. 11 and 16, the SiO 2 film on the polycrystalline Si film 507 is diluted with 1% dilute hydrofluoric acid aqueous solution.₂After removing the 508 film, a photoresist pattern is formed in a predetermined shape by an excimer lithography method as in Example 4, and unnecessary portions of the polycrystalline Si films 507 and 703 are formed by an isotropic dry etching technique (common in FIG. 11). The both end portions of 505 parallel to the wiring of the source line 504 (a) and the data line 504 (b) and the channel layer removal portion in FIG. 16) are etched. In this step, the polycrystalline Si film patterns 507 (a), 507 (b), and 703 are individually insulated.
[0029]
Next, in FIG. 12 and FIG. 16, SiO which becomes the gate insulating film 509 by the CVD method.₂After depositing a film 509 with a thickness of 20 nm and phosphorus-doped polycrystalline Si films 510 and 704 to be gate electrodes 510 and 704 with a thickness of 50 nm, the phosphorous-doped polycrystalline Si films 510 and 704 are patterned by excimer laser lithography and dry etching to form word lines ( Gate electrodes) 510 and 704.
[0030]
As shown in FIGS. 15 and 16, in this embodiment, two independent transistors operate with one gate electrode (word line) 704. That is, since the drain current is rate-controlled in a transistor having a lower threshold value, variation in threshold value between elements can be reduced as compared with the case of one transistor. In this embodiment, two transistors are controlled by the same gate electrode. However, two or more controls are possible. Further, the line width of the ultra-thin polycrystalline Si film 703 in which the channel is formed has reached 50 nm which is below the optical lithographic fee resolution limit.
[0031]
【The invention's effect】
According to the single electronic device of the present invention, the width of the ultra-thin polycrystalline Si film can be controlled by the thickness of the underlying insulating film, so that even a width of 100 nm or less can be controlled very easily. In addition, since ordinary optical lithography and excimer laser lithography techniques can be applied, mass productivity is dramatically improved. Therefore, a semiconductor memory element using a single electronic element can be easily configured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.
FIG. 2 is a sectional view showing a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a third embodiment of the present invention.
4A and 4B are a plan view and a sectional view showing a fourth embodiment of the present invention.
FIG. 5 is a plan view and a cross-sectional view showing a fourth embodiment of the present invention.
FIG. 6 is a plan view and a cross-sectional view showing a fourth embodiment of the present invention.
7A and 7B are a plan view and a cross-sectional view showing a fourth embodiment of the present invention.
FIG. 8 is a plan view and a cross-sectional view showing a fourth embodiment of the present invention.
9A and 9B are a plan view and a cross-sectional view showing a fifth embodiment of the present invention.
FIG. 10 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 11 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 12 is a plan view and a cross-sectional view showing a fifth embodiment of the present invention.
FIG. 13 is an equivalent circuit diagram of a memory array section showing a fourth embodiment of the present invention.
FIG. 14 is a plan layout view of a memory array section showing a fourth embodiment of the present invention.
FIG. 15 is an equivalent circuit diagram of a memory array section showing a fifth embodiment of the present invention.
FIG. 16 is a plan layout view of a memory array section showing a fifth embodiment of the present invention;
17A and 17B are a plan view and a cross-sectional view illustrating a conventional method.
FIG. 18 is a supplementary diagram illustrating a single electronic element.
FIG. 19 is a supplementary diagram for explaining problems of a single electronic device.
[Explanation of symbols]
101, 201, 301, 401, 501, 801 .......... Crystal Si substrate
102, 202, 302, 402, 502, 802 ............ Si thermal oxide film
103, 203, 304, 405, 505 ... CVD-SiO₂
104,204,303,305403,406,503,506 ......... CVD-Si₃N₄
105, 205, 306, 407, 507, 804 ... Ultra-thin polycrystalline Si (channel layer)
409, 509, 805 ……………………………… Gate oxide film
410, 510, 604, 704, 806 .................. Gate electrode (word line)
404 (a), 504 (a), 601, 701, 803 (a) ......... Source (common source line)
404 (b), 504 (b), 602, 702, 803 (b) ......... Drain (data line)

Claims (10)

Accumulation of electrons in the vicinity of the channel such that a channel serving as a current path is formed in the polycrystalline silicon thin film connected between the source, the drain, and the source and the drain, and electrons ejected from the channel can be injected. In a single electronic device as an insulated gate field effect transistor having a channel layer made of the polycrystalline silicon thin film in which grains acting as nodes are formed,
A single electronic device comprising an insulating film having a thickness corresponding to the width of a channel layer, straddling the source and drain, and the channel layer formed on a sidewall thereof. 2. The single electronic device according to claim 1, wherein the thickness of the channel layer is 10 nm or less and the width of the channel layer is 100 nm or less. 3. The single electronic device according to claim 1, wherein the channel layer has a U-shaped cross section. 4. The single electronic device according to claim 1, wherein nitrogen atoms are included in a surface of the side wall of the insulating film having a thickness corresponding to a width of the channel layer in contact with the channel layer. A single electronic device characterized by comprising: 5. The single electronic device according to claim 1, further comprising an insulating film as a protective film on a surface of the channel layer. 6. In a semiconductor memory device having a memory array configuration having a plurality of data lines, a word line intersecting with the data lines, and a memory element at the intersecting position,
The single electronic element according to any one of claims 1 to 5, wherein the storage element is connected to a data line adjacent to the source and drain of the single electronic element, and a gate is connected to a word line. A semiconductor memory device comprising the structure. The semiconductor memory device according to claim 6, wherein a plurality of single electronic elements connect each source to a common data line, and connect each drain to adjacent data lines across the common data line, Further, a semiconductor memory device characterized in that each gate is connected to a common word line. 8. The semiconductor memory device according to claim 7, further comprising a configuration in which a plurality of sets of the plurality of single electronic elements further share a word line. A first insulating film for forming a surface layer of the substrate is formed on a silicon substrate, and a conductor film serving as a source and drain of a single electronic device is formed on the first insulating film, and then the conductor A second insulating film having a thickness corresponding to the width of the channel layer as a base film of the channel layer on the film and the first insulating film, and a third insulating film having an etching rate slower than that of the second insulating film Using the difference in the etching rate between the third insulating film and the second insulating film, the step of sequentially forming, the step of processing the second and third insulating films into a shape orthogonal to the conductor film, and Etching the side wall of the second insulating film and retreating from the edge portion of the third insulating film to form a U-shaped cross-sectional shape of the first, second, and third insulating films; A process for forming a polycrystalline silicon film on the first, second, and third insulating films. When, wherein the polycrystalline silicon film is etched by anisotropic dry etching the first, third and removing the polycrystalline silicon film on the insulating film, a current path on the side wall of the second insulating film A polycrystalline silicon film in which grains acting as storage nodes for accumulating electrons are formed in the vicinity of the channel to the extent that electrons ejected from the channel can be injected and become the source and drain A method of manufacturing a single electronic device, comprising: a step of forming a channel portion connecting between conductor films; and a step of forming a gate insulating film and a gate electrode on the channel portion. 10. The method of manufacturing a semiconductor memory device having a memory array configuration having a plurality of data lines, word lines intersecting with the data lines, and memory elements at the intersecting positions, wherein the memory element forming step includes: A method of manufacturing a semiconductor memory device, comprising a step of a method of manufacturing an electronic element.

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